Introduction to FFT Processors. Chih-Wei Liu VLSI Signal Processing Lab Department of Electronics Engineering National Chiao-Tung University
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1 Itroductio to FFT Processors Chihei Liu VLSI Siga Processig Lab Departmet of Eectroics Egieerig atioa ChiaoTug Uiversity
2 FFT Desig FFT Cosists of a series of compe additios ad compe mutipicatios Agorithm CooeyTuey decompositio for power of two egth FFT Architecture Systematic mappig procedure
3 Agorithm Leve CooeyTuey decompositio Radi, decimatioifrequecy A A Variats based o CT agorithm Fied radi: Radi, Radi, Radi, Radi Mied radi: Spitradi, Radi, Radi umber of additio Same for ay miedradi or fiedradi agorithm. umber of mutipicatio Depeds o the reductio of trivia mutipicatios. A A Hece, icrease additios
4 FFT Agorithms Review of Radi r agorithm DIFdecimatio i frequecy ad DITdecimatio i time versio Radi agorithm Radi ad Radi agorithm Radi ad Radi agorithm Spitradi ad Spitradi
5 FFT Agorithms DFT X e π j,,, a a jb * jb * 5 7 j j [ a b [ b a j j b a] j b a]
6 FFT Agorithms Radi Agorithm DIF Radi Agorithm ] [ ] [ X X.,,, K Butterfy of Radi Agorithm DIF Form
7 FFT Agorithms Radi Agorithm Radi Agorithm X ] [ ` 6 ]} [ ] {[ ] [ j X,,,;,;, ; ~. ~
8 FFT Agorithms Butterfy of Radi Agorithm a a a a Data Orderig: Digit Reversed
9 FFT Agorithms Data Orderig of Radi 6, X, X X X X X X5 X9 X X X6 X X X X7 X X5... Digitreversed orderig
10 FFT Agorithms Butterfy of radi Agorithm a a a a Data Orderig: Bit Reversed
11 FFT Agorithms Data Orderig of Radi X X X X X X X X6 X X X9 X5 X X X X7 X5 6 Bitreversed orderig
12 m m m m m m X 7 7 } ] 7 5 [ ] 6 {[ ] [ FFT Agorithms DIF Radi Agorithm,,,,,5,6,7;. ~
13 } ] 7 5 [ ] 6 {[ } ] 7 5 [ ] 6 {[ FFT Agorithms DIF Radi Agorithm X,;,,. ~
14 FFT Agorithms Butterfy of Radi Agorithm
15 FFT Agorithms Butterfy of Radi Agorithm
16 j X j X X ]} [ { ]} [ { ] [ FFT Agorithms DIF SpitRadi Agorithm i X is from to, ad i X ad X are from to
17 FFT Agorithms Butterfy of SpitRadi Agorithm
18 FFT Agorithms Advatage of Radi Agorithm Low Computatioa Compeity Feibe as radi agorithm Bit reversed output whe ormay ordered iput
19 X X } ] 7 5 [ ] 6 {[ ] [ FFT Agorithms DIF SpitRadi Agorithm,,5,7
20 FFT Agorithms Butterfy of SpitRadi Agorithm j j
21 Mutipicative Compeity Trivia mutipicatios i FFT Mutipied by Radi: ± removed Radi: ± ad ±j partiay removed Spitradi: ± ad ±j removed Radi: ±, ±j, ±j partiay removed Radi: ±, ±j, ±j removed
22 Radi Siga Fow Graph
23 SpitRadi Siga Fow Graph
24 Mutipicative Compeity Radi Cost. Mu Cost. Mu Radi Spit Radi Radi Radi How to obtai reguar SR FFT architecture?
25 Architecture Leve Mappig procedure Systoic array techiques Operatio scheduig, resource sharig Pipeie architecture Oedimesioa iear array Deayfeedbac vs. Deaycommutator. Sige PE architecture Sharedmemory, Sige Processig Eemet PE
26 RMDC Radi MutiPath Deay Commutator X X w 6 w 6 X w 6 w 6 w 6 w 6 w 6 5 w 6 6 w 6 7 w 6 w 6 w 6 w 6 6 w 6 w 6 w 6 w 6 6 w 6 w 6 w 6 w 6 w 6 w 6 w 6 X X X X6 X X X9 X5 X X X X7 X5 Vertica Projectio S Z Z S Z S Z A Z Z Z Deay Commutator or DeaySwitch SwitchDeay Stage Stage Stage Stage
27 st ad d stages i RMDC 6 st A S Z Z B D F C Z E G 9 9 H 5 I Stage Stage Iput pairs : Iput pairs : Iput pairs : Iput pairs : 6 X X w 6 w 6 9 X w 6 w 6 w 6 w 6 w 6 5 w 6 6 w 6 7 w 6 w 6 w 6 w 6 6 w 6 w 6 w 6 w 6 6 w w 6 w 6 w 6 w 6 w 6 w 6 5 X X X X6 X X X9 X5 X X X X7 X5 Stage Stage Stage Stage
28 RMDC RMDC Radi adi Muti utipath ath Deay eay Commutator ommutator X X X X X X5 X9 X X X6 X X X X7 X X5 Stage Stage BF C O M M U T A T O R BF Coefficiets Coefficiets C O M M U T A T O R Stage Stage Iputs A B Cotro Cotro
29 RrMDC RrMDC Iput stage Iput stage th th stage stage stages r r stages r r r Computatioa Eemet Iput Outputs Coefficiets r r r Computatioa Eemet C O M M U T A T O R r r r r r r r r r r r r r Outputs from previous stage To et stage Coefficiets Commutator Cotro a b
30 Deay Feedbac RSDF RSDF R SDF
31 RSDF6 Radi SigePath Deay Feedbac
32 RSDF 6 vs. RSDF BF BF BF BF
33 Buffer Styes of pipeie architecture R deaycommutator: iefficiet 5% MEM usage. RMDC R deayfeedbac: % MEM usage.rsdf
34 Sige PE Architecture RAM BF BF_PE sige BF_PE radi shared memory architecture
35 Cocudig Remars The SpitRadi agorithm has ess computatio compeity, comparig with the fied Radi agorithm. However, its butterfy operatio is irreguar Lshape. The processig speed of pipeie architecture is faster tha sigepe architecture. However, the sige PE architecture is the most areaefficiet, especiay for og egth FFTIFFT appicatio.
36 Review Traditioa FFT Desig Steps. Give poit FFT spec., choose fiedradi agorithm. Desig radir butterfy, mutipier, etc.. Cascade og r stages to compute poit FFT. Arbitrary radi ca be used Base o CooeyTuey decompositio for ay composite umber
37 Probem of Traditioa Approach Caot drive architecture for miedradi agorithm The processig speed is o oger the critica issue ay more owadays. The chip area ad the power cosumptio domiate the desig quaity. Recofigurabe FFTIFFT architecture desig is ecessary for various appicatios. A egthscaabe ad atecyspecified FFTIFFT core is ecessary.
38 Proposed Soutio e impemet FFT modue by sige PE architecture Mutipeport Memory Reg Radir Butterfy Processig Eemet Reg Prefetch buffer
39 Desig Issue Performaceeough, Chip area, power cosumptio. Scaabe processig eemet. Limited Storage bocs. Efficiet memory address geerator.
40 Agorithm Leve e adopt spitradi agorithm to reaize the FFT modue. X X A X j X X j X X j X X j X A A
41 The Kere of Processig Eemet A A A A A A 5 A 6 A 7 A A 9 A A A A A A 5 j j j j j j j j j X X X X X X X 6 X X X 9 X 5 X X X X 7 X 5
42 Foded Butterfy Uits Comparig with RadiRadi, it saves haf memory access times. Feedbac path Mu Mu Mu Mu Butterfy uit Butterfy uit
43 Storage Bocs e use mutipe sigeport memory bas to repace the mutiport memory. The cocept of cofictfree memory. Verte coorig probem Ba 5 6 Ba 7
44 Scaabe Memory Address Geerator There must eist a soutio for such verte coorig probem. The best soutio The proposed Itereave Rotated Data Aocatio IRDA agorithm. Address GeeratorAG for 6egth AT AT AT AT Address Switcher AS Address GeeratorAG for 6egth Rotator RAM RAM RAM RAM RAM RAM RAM RAM
45 The IRDA Cocept A cofictfree memory bas. Simpe ad egthscaabe desig. The circuar shift rotator RAMA RAMB RAMC RAMD
46 LegthScaabe FFTIFFT Core Address geerator RAM A RAM B RAM C RAM D Adder Reg Rotator Reg Reg Reg Reg Mu Mu Mu Mu Radi butterfy processig eemet Radi butterfy processig eemet Reg Reg Reg Reg Mu Mu Mu Mu Rotator
47 Further Performace Improvemet Mutipe PEs architecture. pipeie PEs, for eampe RAM RAM RAM RAM Group RAM RAM 5 RAM 6 RAM 7 Group
48 The CachedFFT Agorithm
49 Overview. Iput data are oaded ito a word mai memory.. C of the words are oaded ito the cache.. As may butterfies as possibe are computed usig the data i the cache.. Processed data i the cache are fushed to mai memory. 5. Steps are repeated uti a words have bee processed oce. 6. Steps 5 are repeated uti the FFT has bee competed. Processor cache Mai Memory
50 Resut X X X X X 6 X 5 X 6 X 7 X X 9 X X X X X X 5
51 6, E, Radi CachedFFT
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Itroductio to FFT Processors Chih-ei Liu VLSI Siga Processig Lab Departmet of Eectroics Egieerig atioa Chiao-Tug Uiversity FFT Desig FFT Cosists of a series of compe additios ad compe mutipicatios Agorithm
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