Introduction to FFT Processors
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1 Itroductio to FFT Processors Chih-ei Liu VLSI Siga Processig Lab Departmet of Eectroics Egieerig atioa Chiao-Tug Uiversity FFT Desig FFT Cosists of a series of compe additios ad compe mutipicatios Agorithm Cooey-Tuey decompositio for power of two egth FFT Architecture Systematic mappig procedure
2 Agorithm Leve Cooey-Tuey decompositio Radi-, decimatio-i-frequecy A A Variats based o CT agorithm Fied radi: Radi-, Radi-, Radi-, Radi- Mied radi: Spit-radi, Radi-, Radi- umber of additio Same for ay mied-radi or fied-radi agorithm. umber of mutipicatio Depeds o the reductio of trivia mutipicatios. - A A Hece, icrease additios FFT Agorithms Review of Radi- r agorithm DIFdecimatio i frequecy ad DITdecimatio i time versio Radi- agorithm Radi- ad Radi- agorithm Radi- ad Radi- agorithm Spit-radi ad Spit-radi
3 FFT Agorithms DFT X e π j,,, a jb * a jb * 5 7 j j j [ a b j b a] [ b a j b a] FFT Agorithms Radi- Agorithm DIF Radi- Agorithm X [ ] X [ ] Butterfy of Radi- Agorithm,, K,. DIF Form
4 FFT Agorithms Radi- Agorithm X [ ] Radi- Agorithm X,,,,; ~ ; [ ] ` {[ ] j [ ]},; ~. FFT Agorithms Butterfy of Radi- Agorithm Data Orderig: Digit Reversed
5 FFT Agorithms Data Orderig of Radi-... Digit-reversed orderig FFT Agorithms Butterfy of radi- Agorithm Data Orderig: Bit Reversed 5
6 FFT Agorithms X Data Orderig of Radi- Bit-reversed orderig m m m m m m X 7 7 } ] 7 5 [ ] {[ ] [ FFT Agorithms DIF Radi- Agorithm,,,,,5,,7;. ~
7 7 } ] 7 5 [ ] {[ } ] 7 5 [ ] {[ FFT Agorithms DIF Radi- Agorithm X,;,,. ~ FFT Agorithms Butterfy of Radi- Agorithm
8 FFT Agorithms Butterfy of Radi- Agorithm FFT Agorithms DIF Spit-Radi Agorithm X [ ] X { j[ ]} X { j[ ]} i X is from to -, ad i X ad X are from to -
9 FFT Agorithms Butterfy of Spit-Radi Agorithm FFT Agorithms Advatage of Radi- Agorithm Low Computatioa Compeity Feibe as radi- agorithm Bit reversed output whe ormay ordered iput 9
10 X X } ] 7 5 [ ] {[ ] [ FFT Agorithms DIF Spit-Radi Agorithm,,5,7 FFT Agorithms Butterfy of Spit-Radi Agorithm
11 Mutipicative Compeity Trivia mutipicatios i FFT Mutipied by Radi-: removed Radi-: ad j partiay removed Spit-radi: ad j removed Radi-:, j, j partiay removed Radi-:, j, j removed Radi- Siga Fow Graph
12 Spit-Radi Siga Fow Graph Mutipicative Compeity Radi- Cost. Mu Cost. Mu Radi- Spit- Radi Radi- Radi How to obtai reguar SR FFT architecture?
13 Architecture Leve Mappig procedure Systoic array techiques Operatio scheduig, resource sharig Pipeie architecture Oe-dimesioa iear array Deay-feedbac vs. Deay-commutator. Sige PE architecture Shared-memory, Sige Processig Eemet PE RMDC Radi- Muti-Path Deay Commutator X X X X X X X X X X9 X5 X X X X7 X5 Z - Z - Z - Z - Z - Z - Z - Deay Commutator or Deay-Switch Switch-Deay
14 st st ad d stages i RMDC Iput pairs : Iput pairs : Iput pairs : Iput pairs : X X 9 X X X X X X X X9 X5 X X X X7 X5 Stage Stage Stage Stage RMDC Radi- Muti-Path Deay Commutator X X X X X 5 X5 X9 7 9 X X X X X X 9 X7 X 5 X5 Stage Stage
15 RrMDC r r r r Iput stage r th stage r r r r r r r r r r r r r r r r Deay Feedbac RSDF RSDF R SDF 5
16 RSDF Radi- Sige-Path Deay Feedbac RSDF vs. RSDF
17 Buffer Styes of pipeie architecture R deay-commutator: iefficiet 5% MEM usage. RMDC R deay-feedbac: % MEM usage.rsdf Sige PE Architecture 7
18 Cocudig Remars The Spit-Radi agorithm has ess computatio compeity, comparig with the fied Radi agorithm. However, its butterfy operatio is irreguar L-shape. The processig speed of pipeie architecture is faster tha sige-pe architecture. However, the sige PE architecture is the most areaefficiet, especiay for og egth FFTIFFT appicatio. Review Traditioa FFT Desig Steps. Give -poit FFT spec., choose fied-radi agorithm. Desig radi-r butterfy, mutipier, etc.. Cascade og r stages to compute poit FFT. Arbitrary radi ca be used Base o Cooey-Tuey decompositio for ay composite umber
19 Probem of Traditioa Approach Caot drive architecture for mied-radi agorithm The processig speed is o oger the critica issue ay more owadays. The chip area ad the power cosumptio domiate the desig quaity. Re-cofigurabe FFTIFFT architecture desig is ecessary for various appicatios. A egth-scaabe ad atecy-specified FFTIFFT core is ecessary. Proposed Soutio e impemet FFT modue by sige PE architecture Mutipe-port Memory Reg Radi-r Butterfy Processig Eemet Reg Pre-fetch buffer 9
20 Desig Issue Performace-eough, Chip area, power cosumptio. Scaabe processig eemet. Limited Storage bocs. Efficiet memory address geerator. Agorithm Leve e adopt spit-radi agorithm to reaize the FFT modue. X X A X j X X j X X j X X j X A A
21 The Kere of Processig Eemet A A A A A A 5 A A 7 A A 9 A A A A A A 5 j j j j j j 9 j j j X X X X X X X X X X 9 X 5 X X X X 7 X 5 Foded Butterfy Uits Comparig with Radi-Radi-, it saves haf memory access times. Feedbac path Mu Mu Mu Mu Butterfy uit Butterfy uit
22 Storage Bocs e use mutipe sige-port memory bas to repace the muti-port memory. The cocept of cofict-free memory. Verte coorig probem Scaabe Memory Address Geerator There must eist a soutio for such verte coorig probem. The best soutio --- The proposed Itereave Rotated Data Aocatio IRDA agorithm. Address GeeratorAG for -egth AT AT AT AT Address Switcher AS Address GeeratorAG for -egth Rotator RAM- RAM- RAM- RAM- RAM- RAM- RAM- RAM-
23 The IRDA Cocept A cofict-free memory bas. Simpe ad egthscaabe desig. The circuar shift rotator RAM-A RAM-B RAM-C RAM-D Legth-Scaabe FFTIFFT Core Address geerator RAM -A RAM -B RAM -C RAM -D Adder Reg Radi- butterfy processig eemet Radi- butterfy processig eemet
24 Further Performace Improvemet Mutipe PEs architecture. pipeie PEs, for eampe. RAM RAM RAM RAM Group RAM RAM 5 RAM RAM 7 Group The Cached-FFT Agorithm
25 Overview. Iput data are oaded ito a -word mai memory.. C of the words are oaded ito the cache.. As may butterfies as possibe are computed usig the data i the cache.. Processed data i the cache are fushed to mai memory. 5. Steps - are repeated uti a words have bee processed oce.. Steps -5 are repeated uti the FFT has bee competed. Processor cache Mai Memory Resut X X X X X X 5 X X 7 X X 9 X X X X X X 5 5
26 , E, Radi- Cached-FFT
Introduction to FFT Processors. Chih-Wei Liu VLSI Signal Processing Lab Department of Electronics Engineering National Chiao-Tung University
Itroductio to FFT Processors Chihei Liu VLSI Siga Processig Lab Departmet of Eectroics Egieerig atioa ChiaoTug Uiversity FFT Desig FFT Cosists of a series of compe additios ad compe mutipicatios Agorithm
Outline. Applications of FFT in Communications. Fundamental FFT Algorithms. FFT Circuit Design Architectures. Conclusions
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