Inverting Martin Synthesis for Verification

Transcription

1 Inverting Mrtin Synthesis for Verifiction Stephen Longfield, Jr., Rjit Mnohr School of Electricl nd omputer Engineering ornell University, Ithc, NY, 14853, U.S.A. Emil: {slongfield, Abstrct Qusi Dely-Insensitive (QDI) circuits cn be creted through the procedure of Mrtin Synthesis, series of trnsformtions tht begin with n executble specifiction nd end in trnsistor network. If these trnsformtions re properly pplied the circuits will be correct by construction; however if they re improperly pplied, finding design errors cn be quite difficult. We show tht the forwrd trnsformtions of Mrtin Synthesis re reversible, nd tht the inversion of these steps recretes the specifiction when pplied to correctly synthesized circuits. We hve creted tool to pply these inversions, nd show tht it cn lso be used to verify other compiltion methods for QDI circuits. This procedure presents n lterntive pproch to typicl VLSI verifiction by requiring little designer effort nd by reconstructing specifictions through trnsformtions. I. INTRODUTION AND MOTIVATION Verifying tht VLSI circuits will operte correctly is n importnt re of reserch, due both to the very high costs of filure, nd the high level of complexity. However, mny of the best methods to verify circuits require gret del of designer effort to set up the verifiction [1], nd ny errors in this specifiction cn be very difficult to dignose nd debug. Mrtin Synthesis for Qusi Dely-Insensitive (QDI) synchronous VLSI circuits begins with description of computtion in the ommunicting Hrdwre Processes (HP) lnguge, derivtive of Hore s ommunicting Sequentil Processes (SP) [2]. This description is trnsformed into severl smller HP progrms whose ctions re synchronized by ctions on communiction chnnels. These chnnels re replced with pproprite hndshkes, which my be reshuffled before being trnsformed into circuits [3]. When properly pplied, this procedure genertes correct synchronous circuits. For circuits generted through Mrtin Synthesis, the specifiction is the originl high-level description, which is itself simultble. urrently, the mjority of QDI circuits re verified by referencing their finl simulted behvior ginst simultions of this originl specifiction This is not sufficient for very lrge designs which my hve unknown rre cses tht re not exercised by simultions. A forml verifiction system for synchronous circuits hs long been desired [4], but most of the effort hs gone to verifying tht the synthesis steps cn be correctly pplied forwrds [5]. In the field of computer science, there hs been considerble work in the reverse engineering nd decompiltion of progrms, principlly for the purposes of understnding how they operte, either for modifiction of legcy progrms or for understnding unknown progrms [6]. These decompiltion procedures work best when the progrm ws produced through known progrm trnsformtions. We propose step towrd reverse-engineering QDI logic by developing techniques to invert Mrtin Synthesis for control circuits. This process cn be used for number of different pplictions, including (i) verifying tht synchronous circuits correspond to their higher-level specifictions, especilly in the context of mnul design; (ii) evluting the impct of circuit optimiztions on high-level design; (iii) reverse-engineering circuits. We hve built tool to utomticlly pply the proposed inverse trnsformtions, nd hve used it to reverseengineer number of different QDI circuits from the literture. II. MARTIN SYNTHESIS FOR ONTROL We summrize the stges of the Mrtin Synthesis pproch to QDI circuit design. The procedure strts with circuits described using the HP nottion (see Appendix A). To crete efficient circuits, bcktrcking between stges my be required, but for ny circuit creted by Mrtin Synthesis there exists strictly forwrd pth. In the description tht follows, we hve introduced two dditionl steps in the synthesis procedure: (i) the introduction of Two-phse HP [7], nd (ii) the introduction of the prtitioned repetitive event-rule system (PRER), derivtion of structures used for timing nlysis [8]. These steps mke spects of the synthesis procedure more explicit without chnging the procedure itself. They lso introduce certin limittions which restrict our description to the design of control circuits. 1 A. HP Two-phse HP Most QDI systems implement chnnel ctions with fourphse hndshkes s these hve been found to llow for effective nd efficient circuits, especilly when hndshkes re llowed to overlp [9]. Two-phse HP [7] ws creted to nlyze these overlps. The trnsltion from HP to Two-phse HP is strightforwrd. Ech HP chnnel ction,, is replced with two Twophse HP chnnel ctions ;, known s the up-going nd down-going chnnel ction, respectively. For dt-crrying chnnel ctions, the up-going chnnel ction is defined s the ction which sets dely-insensitive encoding of dt to vlid stte, nd the down-going ction is defined s the one tht resets it to neutrl stte. These communiction ctions my be pssive (beginning with wit) or ctive 1 This is not limittion of Mrtin synthesis, but rther limittion we hve introduced to simplify the inverse synthesis problem in this pper.

2 (beginning with stte chnge). Mrtin Synthesis permits delying the down-going ction of the hndshke, though it cnnot be delyed such tht it psses the next up-going ction on this chnnel [3]. This procedure is known s reshuffling, nd incorrect reshuffling cn led to dedlock. One difference between the procedure we present here nd Mrtin Synthesis without the trnsformtion to Two-phse HP is the use of the opertor insted of the opertor for simultneous composition of chnnel ctions. The opertor does not hve well-defined Two-phse HP definition, wheres is defined s: D D ; D If chnnel ctions re composed together with t most one of the chnnels cn be ctive [7]. Exmple. The D-element is commonly used component in QDI control circuits. This circuit corresponds to the HP progrm nd Two-phse HP progrm shown below: *[L; R] *[L ; L (R ; R )] B. Two-phse HP HSE The next step in Mrtin synthesis is the cretion of hndshking expnsions (HSE). HSE is strict subset of HP, where ll vribles re Boolens. This implies tht ll chnnel ctions hve been expnded into sets nd wits on Boolen vribles tht implement the chnnel. When trnslting to HSE, ll computtions on non-boolen vribles re first trnslted into Boolen ctions. This is done using stndrd dt representtion techniques [10]. After this trnsltion hs been mde, dely-insensitive dt encodings nd pssive/ctive ssignments re determined for ech chnnel, nd ech chnnel is trnslted into its respective representtions. For dtless chnnels, with output c o nd input c i, this expnsion tkes one of the following forms: c o ; [c i ] (ctive) [c i ]; c o (pssive) c o ; [ c i ] (ctive) [ c i ]; c o (pssive) Two further invisible trnsformtions re llowed t this level: (i) Fresh, locl vribles cn be dded to the computtion, but they cnnot ffect computtion or be ccessed by other processes. This is equivlent to the stte vrible insertion of Mrtin Synthesis [3]. (ii) Externlly invisible ordering chnges cn be mde. These include trnsformtions tht do not chnge the sequence of opertions (such s loop peeling nd unrolling [11]), s well s trnsformtions which reorder sequences of ssignments nd sequences of wits on Boolen vribles. Reordering sequence of ssignments or sequence of wits is permissible becuse QDI circuit must observe vribles through wires with rbitrry dely, nd thus would be unble to distinguish such chnges. These two trnsformtions re used in the stte ssignment procedure of Mrtin Synthesis. In this procedure, the HSE is modified into one where no ssignment to vribles cn be reched in two distinct progrm positions. Exmple. The HSE corresponding to the Two-phse HP for the D-element is given below. Note tht it includes stte vrible z introduced to enble production rule synthesis [3]. *[[l i ]; z ; l o ; [ l i ]; r o ; [r i ]; z ; r o ; [ r i ]; l o ]. HSE PRER Trnsltion from HSE to prtitioned repetitive event-rule system (PRER) is only defined for non-terminting HSE (those tht include single infinite loop) or HSEs without ny loops. This does not limit the clss of circuits we cn design, s progrms cn be re-written to stisfy this constrint [12]. The definition is lso limited to HSE without vcuous sets nd wits, which re defined s ones whose removl will not ffect the rechble sttes or dely computtion. This lso does not dd ny effective limits, nd is resonble restriction for control circuits. Prtitioned Repetitive Event Rule (PRER) systems re novel structure introduced here. They re derivtive of Repetitive Event Rule (RER) systems, which were creted to nlyze performnce of synchronous control circuits [8]. A PRER hs two event types, wit type events, which wit for vrible to be equl to Boolen vlue, nd set type events, which set vrible to Boolen vlue. These events re connected with rules tht represent cuslity. We forbid ny PRER from hving both wit nd set events on the sme vrible. This constrint is wht mkes these systems prtitioned vrible is either one tht is set by the PRER, or one tht is set by nother nd which my predicte events in the PRER. When events re represented s nodes nd the rules re represented s directed edges, the PRER cn be viewed s directed grph. To trnsform from HSE to PRER, we first crete events for ll set ctions (set events), nd wit events for ll wits. As PRER do not hve representtion for selection sttements or logic, ll selections sttements nd logicl opertions must be trnsformed into series or prllel wits nd sets. For logicl opertions, nd corresponds to prllel execution of wits while or opertions where the rguments re exclusive result in wits on the vribles tht will be true. This limits the set of possible HSE tht cn be represented with PRER, which is why this pper focuses on control circuits. Sequencing constructs from the HSE re used to crete edges. Sequencing between two ctions cretes direct edges, which distributes over prllel composition. The infinite loop construct, *[P], cretes n edge from the finl event bck to the first event which is lbelled s bck edge. These trnsformtions will not construct vlid PRER if the HSE contined wits on vribles tht were lso set by the computtion. Fortuntely, these wits re either superfluous or led to dedlock in the cse of most control circuits. If the vrible is never set to vlue tht would stisfy the wit, the wit nd ll of its successors cn be removed. We llow two trnsformtions to be mde on the PRER, which re equivlent to buffer nd inverter dditions from Mrtin Synthesis [3]. Adding buffer or inverter to vrible

3 l i z l o l i r o l o Fig. 1. r i r o z D-Element PRER is equivlent to dding successor set event on fresh vrible to ll events on the originl vrible, nd trnsferring ll of theses nodes successors to the fresh nodes. An isochronic brnch of forked wire is brnch where ll trnsitions will be cknowledged by nother trnsition. Wiring brnches don t hve cler prllel in PRER systems, but there is cler prllel to trnsitions. Adding buffer or inverter on n isochronic brnch is identicl to dding set event on fresh vrible s successor to ll events (either wits or sets) on single vrible, nd then moving one or more of the outgoing edges of the originl nodes onto these new nodes. If the new edges re not implied by trnsitivity, then it must be the cse tht ll sets on the fresh vrible will be cknowledged by sets on this successor. Exmple. Figure 1 shows the PRER system tht corresponds to the D-element hndshking expnsion. In this digrm, wit events re boxed, while set events re not. The initil node is the one shown on the top left corner. D. PRER PRS A Production Rule Set (PRS) tht implements PRER is the PRS tht hs the sme requirements for ordering nd cuslity s the PRER. The PRS tht corresponds to PRER need not be unique. The synthesis procedure from PRER to PRS cn use the sme technique s conventionl Mrtin synthesis [3], since the PRER cn be viewed s grphicl representtion of the HSE. Exmple. The production rules for the D-element re: z r i l o z r i l o l i r i z z r i z l i r o z l i r o III. INVERSE SYNTHESIS This section outlines the proposed methods for inverting ll the steps in the synthesis of QDI circuits. We use the sme intermedite representtions s the synthesis procedure outlined in Section II. We lso discuss limittions of the proposed inverse synthesis steps. A. PRS PRER As PRER re similr to stndrd repetitive event-rule systems (RER) [8], lgorithms to construct RER cn lso construct PRER systems. An exmple of such n lgorithm is Lee s Index-Priority Simultion lgorithm [13]. These lgorithms need to be ugmented to lbel events s being either sets or wits, but cn otherwise be implemented s specified. This lbeling must be specified by the designer for the inversion of this rule. For systems without shred vribles, the wit event vribles will be exctly the chnnel input vribles, mking this strightforwrd step. As Index-Priority Simultion is only concerned with finding cycles, the lgorithm ws lso ugmented for finding the stright-line predecessors to cycles (pseudorepetitive PRER), nd identifying the entry points to cycles. This ws done by ensuring tht the PRER initil stte in mtched the circuit reset stte, nd tht there were s few PRER nodes possible between this stte nd the cycle entry. In the cse where the reset stte ws in the cycle, edges connecting to it were lbeled s bck edges. We utomticlly reconstructed the D-element PRER from its production rule set using ugmented index-priority simultion. Limittions. All QDI PRS without inherent disjunctions cn be trnsformed bck into PRER [13] though this procedure is computtionlly complex. This exposes nother limittion of the pproch outlined in this pper nmely, tht we pply the inverse synthesis process to individul control processes rther thn the full system. This is similr to n implicit limittion in Mrtin synthesis where hndshking expnsions re converted into PRS one process t time, thereby voiding the construction of the stte spce for the entire system. B. PRER HSE To trnsform from PRER to n HSE, we first trnsform ll of the PRER events into HSE events, wit events mpping to HSE wits, nd set events mpping to HSE sets. If the PRER is pseudorepetitive, we consider the two components independently. These re combined using the following three rules: If two wit nodes hve the sme set of successors, these two nodes re fused together, nd become single node with their elements combined with nd. If HSE hs only single predecessor, nd tht predecessor hs only single successor, the two HSE nodes cn be fused together, sequencing the predecessor before the successor. If two HSE nodes hve the sme set of successors nd predecessors, these two HSE nodes re fused together with prllel composition. This is sufficient to collpse ll properly nested PRER into single HSE node. If this node hs no successors or predecessors, it is stright line HSE. If it is its own successor nd predecessor, it is n infinitely looping HSE. Note tht if the PRER is cyclic, reverse edges must be either ignored or trnsformed with the lowest priority. If they re not, the HSE my be reconstructed incorrectly, s these re the only indictor for where loop begins. Repetedly pplying these trnsformtions to the PRER in Figure 1 re-cretes the hndshking expnsion for the D- element. Limittions. If the PRER is not properly nested [7], the trnsformtions given will not be ble to derive HSE. As the HSE only hs prllel nd sequentil composition opertors, the originl embedding must be properly nested. However,

4 the PRER system could correspond to circuits creted by other procedures tht do not use HSE. Finlly, the limittions outlined in Section II lso pply.. HSE Two-phse HP To reverse the trnsltion of chnnel ctions from Twophse HP, ech chnnel must be lbeled s ctive or pssive, nd then mtch the projection onto ech pir of chnnel ction vrible pirs ginst Tble I, duplicted from [7]. This gives prtil ordering on Two-phse chnnel ctions, which cn be used to reconstruct the Two-phse HP. We describe few extensions to this process below. First, if chnnel is communicted on more thn once in progrm, ech communiction nd nd its ssocited chnnel vribles cn be given fresh nmes for the ske of the trnsformtion. Second, if the vribles do not fit into the orderings shown in Tble I, they cn be reordered under certin circumstnces. Prllel composition of ctions on chnnel vribles cn be mpped to ny of the possible interlevings. This prllel composition should be reconstructed to lest restrictive Two-phse HP llowed, where the Two-phse compositions re ordered s: L R < L ; R = R ; L < L R Finlly, ny invisible trnsformtions, s defined in the Twophse HP to HSE section cn be mde. The trnsformtion tht ws found to be the most common ws loop peeling, where reconstructed HSE hd some chnnel vrible set in its reset stte, nd subsequent occurrences of this set were scheduled in the body of the loop. These trnsformtions must be mde such tht when reconstructing the Two-phse HP, the ordering on chnnel up nd down going ctions is for ny chnnel. If this is not true, it is not possible to trnslte bck into HP progrm. This ordering must exist for ny properly constructed HSE, but my not pper in reconstructed HSE if the reentry point of the infinite loop ws incorrectly determined. In these cses, loop peeling tht gives the proper chnnel ordering must exist if the decompiltion is to continue. Limittions. The methods presented here will not reconstruct ny of the trnsltions of dt opertions onto Boolen vribles. As there re mny possible origins for Boolen opertion, the specifiction cnnot be reconstructed through purely uninformed inversions. Additionlly, s ws stted in the originl pper on Two-phse HP, to recrete the Twophse HP, the HSE must be properly nested, however, ny HSE tht ws generted from the synthesis procedure will be properly nested [7]. It must lso be the cse tht the chnnel ctions in the HSE contin correct ordering for ll chnnels. D. Two-phse HP HP In the mjority of cses trnsforming from Two-phse HP to HP is done by replcing the up-going chnnel ction with the full chnnel ction, s its position in the computtion must not hve been modified. TABLE II EXAMPLE STAR OMPOSITION TO PROBES. IN THIS TABLE, IS BEING USED TO RANGE OVER ALL NON- OMPOSITION OPERATORS (E.G. ;) Pssive, D Active nd D pssive, E ctive pssive, D nd E ctive pssive, D nd E ctive D ; D [ ]; D; D E ; D E [ D]; E; ( D) (D E ); D E [ ]; (D E); (D ; E ); D E [ ]; (D; E); The one exceptionl cse is when two up-going chnnel ctions re composed with. If the down-going chnnel ctions re lso composed with, then the full chnnel ctions cn be consider to occur t the sme progrm point s the upgoing ctions, composed with. If the down-going ctions re not composed with, then the trnsltion used is the following steps in sequence: (i) wit for ll the probes on the pssive chnnels to be true; (ii) execute the opertions on the ctive chnnels (composed s in the originl up-going ctions); (iii) complete the communiction on the pssive chnnels in prllel. Exmples re shown in Tble II. Limittions. The procedure defined here does not preserve dedlocking behvior (since the second hlf of the synchroniztion is ersed). Any dedlock would hve to be identified t the Two-phse HP level of bstrction, through existing techniques [7]. IV. APPLIATIONS We hve creted tool which utomticlly pplies the reverse steps detiled in the previous section, nd hve successfully pplied it to the control circuits tht re used in two compiltion procedures in the literture: (i) Syntx Directed Trnsltion [14], nd (ii) the Tngrm synthesis pproch [15]. These two systems were chosen s the primitives re within the limits to the nlysis proposed, their synthesis ws not conducted by the uthors, nd their reverse engineerings re simple enough to present here. Beyond these exmples, we hve successfully pplied the decompiltion tool to dtless control buffers of the PHB, PFB, nd WHB fmilies [9], s well s lrger stright-line sequencing with severl hundred possible rechble stte ssignments. A. Syntx Directed Trnsltion l i l o Fig. 2. F The D-Element In the Syntx Directed Trnsltion process presented in [14] sub-processes re decomposed utomticlly into smller pro- r o r i

5 TABLE I HSE AND MAPPINGS TO RESHUFFLED TWO-PHASE OMMUNIATIONS L Pssive, R Pssive L Active, R Active L Active, R Pssive [l i ]; l o ; [r i ]; r o L ; R [l i r i ]; l o r o L R [r i ]; r o ; [l i ]; l o R ; L l o ; [l i ]; r o ; [r i ] L ; R l o r o ; [l i r i ] L R r o ; [r i ]; l o ; [l i ] R ; L l o ; [l i r i ]; r o L ; R l o ; [r i ]; r o ; [l i ] L R [r i ]; l o ; [l i ]; r o L R [r i ]; r o l o ; [l i ] R ; L In this tble, n up-going ction is being used s shorthnd for up nd down going ctions. The sme trnsforms pply. As nd commute, L Pssive, R Active is identicl to L Active, R Pssive with renming. cesses, nd then re-connected with D-element (see Figure 2). For sequentil composition, this corresponds to the trnsformtion: [S 0 ; S 1 ] [ 0 S 0 ; 0?] [ 1 S 1 ; 1?] D( 0, 1 ) where the D-element is shown in Figure 2. The F-element in Figure 2 is simply: l i r i z z This llows us to trnslte the D-element circuit into PRS. In this PRS, the pir of wires on the left is ddressed s l i nd l o, nd the ones on the right s r i nd r o, mking up the chnnels L nd R, respectively. We used this D-element s the working exmple when explining Mrtin Synthesis, s well s the proposed inverse synthesis pproch. When ugmented with n environment nd reset on z, our tool cn crete the PRER system shown in Figure 1. This in turn ws utomticlly inverted into the correct hndshking expnsion, which in turn ws converted into the correct Two-phse HP. Finlly, the Two-phse HP *[L ; L (R ; R )] cn be correctly converted into: *[L; R] As these re dtless chnnels, they cn be freely ssigned to sends by lbeling the outputs s dt, creting the HP: *[L!; R!] which mtches the originl HP used for the D-element. B. Tngrm ontrol ircuits The Tngrm compiltion method hs been successfully used to crete severl synchronous chips by mpping from SP-derived source lnguge down to circuit primitives [15]. The vlidity of this mpping ws rgued by giving specifictions for the primitives nd showing tht, if these specifictions re followed, the finl decomposition will be vlid implementtion of the originl progrm [16]. In this section, we use the decompiltion tools nd techniques we hve developed to show tht n interesting selection of the Tngrm primitives 0 0 S 1 1 ) ircuit Digrm b) Schemtic Icon Fig. 3. Tngrm S Element implement their specifictions. For the ske of compctness, we do not present the PRER for the Tngrm primitives. TABLE III MAPPING FROM TANGRAM SPEIFIATION TO TWO-PHASE HP Nme Tngrm Two-phse HP Specifiction Up-going Action b Down-going Action b A! B? A! B? Sequentil omposition T ; U P; Q Prllel omposition P Q Simultneous omposition : b A B Infinite Loops #[T ] *[P] Tngrm specifictions indicte if chnnel is ctive or pssive. Here, tht is indicted in Two-phse HP by lbeling s send or receive, respectively. This mpping is rbitrry. The primitives re specified in terms of circuit digrms, Tngrm digrms nd SP-like specifiction. The circuit digrms re directly trnsltble into PRS nd the Tngrm digrms give indictions for which chnnels should be considered pssive (indicted with bubble) nd ctive (indicted with filled-in circle). The written specifictions hve direct trnsltions into Two-phse HP, detiled in Tble III. All of these circuits re specified to be strongly initilizing mening they need no dditionl circuitry to reset to the correct stte given tht their inputs were reset to the correct stte. 1) S-Element: The S-Element is circuit element tht is used to build up other Tngrm primitives. The circuit digrm nd the symbol tht will be used to represent it re shown in Figure 3. It is described s being similr to the D-element [14], nd with Two-phse specifiction: *[A? (B!; B!); A?] When we pss the PRS for the S-element circuit through our tools, the HSE derived (where z indictes the output of the -element, nd with vribles renmed to indicte input nd

6 output) is: *[[ i ]; b o ; [b i ]; z ; b o ; [ b i ]; o ; [ i ]; z ; o ] This HSE cn be pssed through the next phse of decompiltion, creting the Two-phse HP: *[A? (B!; B!); A?] which is identicl to the Two-phse HP specified by the Tngrm flow. Using this description, we cn see tht it is subtly different thn the D-element. The S-element requires the entire ctive hndshke to be enclosed in the up-going ction of the pssive hndshke, while the D-element requires the ctive hndshke be enclosed by the down-going ction. These re symmetric, but represent distinct HP. The S-element HP follows: *[[A]; B!; A?] 2) Repeter: The repeter is source for ctive chnnel b, ctivted by pssive chnnel. The trnsltion of its specifiction into Two-phse HP follows: A? (*[B!; B!]) Given n ll-low reset, the circuit shown in Figure 4 cn be inverted to result in the HSE: [ 0 ]; *[ ; [ ]; ; [ ]]] This HSE cnnot be decompiled further by the procedures presented bove into pure chnnels. This is becuse the Twophse ction on A never completes. One wy to proceed is to simply convert the wit into probe on the chnnel. With this pproch, we cn obtin the Two-phse HP nd HP shown below: Two-phse [A]; *[B!; B!] HP [A]; *[B!] These re correctly infinite sources on B tht re predicted on A. However, they will never cknowledge the first Twophse ction on A, so the Two-phse HP does not precisely mtch the Tngrm specifiction. If we erse unrechble ctions from the Tngrm specifiction, then the Two-phse HP mtches exctly. 3) Sequencer: Two specifictions re given for the sequencer: b # 0 1 ) Tngrm Digrm b) ircuit Digrm Fig. 4. Tngrm Repeter b ; c S 0 1 ) Tngrm Digrm b) ircuit Digrm Fig. 5. b c Tngrm Sequentil Element 0 1 c 1 c 0 S S ) Tngrm Digrm b) ircuit Digrm Fig. 6. Tngrm Prllel Element *[A? (B!; B!;!); A?!] *[A? B!; A? (B!;!;!)] However, only the circuit shown in Figure 5 is given s n implementtion. We cn invert the production rules corresponding to the Tngrm circuit into the following HSE: *[[ 0 ]; ; [ ]; ; [ ]; c 0 ; [c 1 ]; 1 ; [ 0 ]; c 0 ; [ c 1 ]; 1 ] This ws utomticlly inverted to construct the following Two-phse HP: *[A? (B!; B!;!); A?!] Which represents the first specifiction, nd is thus correct implementtion. This trnsltes into the HP: *[[A]; B!;!; A?] 4) Pr: The Pr element, shown in Figure 6, is used to compose two ctions in prllel. No explicit Two-phse specifiction is given, but it is described s structure where hndshke on A encloses prllel hndshkes on B nd. We cn decompile this circuit using our flow, representing the outputs of the S-elements connected to B s z, nd to s y, we derive the HSE: *[[ 0 ]; (( ; [ ]; ; [ ]; z ) (c 0 ; [c 1 ]; c 0 ; [ c 1 ]; y )); 1 ; [ 0 ]; (z y ); 1 ] This decompiles to the Two-phse HP *[A? ((B!; B!) (!;!)); A?] nd finlly, to the HP: *[[A]; (B!!); A?] c 0 c 1

7 This HP corresponds to the textul description of the Pr opertion. 5) Non-Receptive Mixer: The Tngrm non-receptive mixer element depicted in Figure 7 is structure for joining two chnnels into single chnnel, it hs requirement on its usge tht the environment must gurntee tht the two input chnnels re ccessed strictly sequentilly. Given tht, it cn be considered s the superposition of two specifictions: *[A?!; A?!] *[B?!; B?!] Decompiling the circuit in conjunction with the prtil environments corresponding to these two scenrios llows the tool to derive: *[[ 0 ]; c 0 ; [c 1 ]; 1 ; [ 0 ]; c 0 ; [ c 1 ]; 1 ] *[[ ]; c 0 ; [c 1 ]; ; [ ]; c 0 ; [ c 1 ]; ] These cn be decompiled into the Two-phse HP processes: *[A?!; A?!] *[B?!; B?!] which correspond to the specifictions given. A more detiled reconstruction my recombine them to the HP *[[A B!; A? []B!; A? ]] However, this selection-sttement reconstruction is not performed by the current version of the decompiltion tool tht we hve developed. 6) Join: The Tngrm join element, shown in Figure 8, is the dul of the pr element, tking communictions on A nd B nd enclosing them in. We cn derive the HSE from the circuit to obtin: *[ [ 0 ]; c 0 ; [c 1 ]; ( 1 ); [ 0 ]; c 0 ; [ c 1 ]; ( 1 ) ] This decompiles to the Two-phse HP: *[ A? B?!; A? B?!] which corresponds to the HP: c b 1 0 c 0 c 1 ) Tngrm Digrm b) ircuit Digrm Fig. 7. Tngrm Non-Receptive Mixer Element b c 1 0 c 0 c 1 ) Tngrm Digrm b) ircuit Digrm Fig. 8. *[ A? B?! ] Tngrm Join Element One given requirement of the join element is tht when the B nd ports re connected to the B nd ports of the pr element, the communiction proceeds. This is the cse for this HP, nd so we sy tht this circuit implements the specifictions given. V. ONLUSIONS AND FUTURE WORK We hve discussed nd given inversions for ech stge of Mrtin Synthesis, dividing up stges when this ws found to give more nturl inverse trnsformtions. These inversions hve been composed together to produce decompiltion tool, which hs been successfully pplied to reconstruct specifictions of QDI circuits with only limited informtion bout the originl specifiction. We showed how the pproch could be pplied to construct HP-lnguge specifictions for number of different control circuits. The nlysis here is limited to non-inherently disjunctive systems, but could be extended using methods similr to the Extended Repetitive Event Rule extension of Repetitive Event Rule Systems [13]. Outside of the exmples presented in this pper, it hs been used to verify the sequencing of simple dt-crrying circuits, but currently cnnot reconstruct nontrivil dt-crrying elements or complex selection sttements. Future work will be focused on more generl reconstruction tht includes dt s well s selection sttements. AKNOWLEDGEMENTS This reserch is supported by by the NSF GRFP under grnt DGE , IARPA under wrd N , nd the NSF TRUST ST under F APPENDIX A Here we informlly present the nottion we use to describe QDI synchronous circuits. A forml trce-tree bsed semntics cn be found in [17]. A. HP As convention, vribles re rnged over by lowercse letters,, b, c..., chnnels re rnged over by uppercse letters from the beginning of the lphbet, A, B,..., nd progrms or progrm segments re rnged over by uppercse letters from the second hlf of the lphbet, P, Q, R... Skip: skip. This sttement does nothing.

8 Assignment: x := E. This sttement mens ssign the vlue of expression E to x. The sttements x nd x re shorthnd for x := true nd x := flse, respectively. ommuniction: A!e is sttement mening send the vlue of e over chnnel A, nd B?x mens receive vlue over chnnel B nd store it in vrible x. Both sending nd receiving re blocking. Selection: [G 1 P 1 []...[]G n P n ], where ech G i is boolen expression, nd ech P i is sttement. This sttement is executed by witing for one of the gurds to be true, nd then executing one sttement with true gurd. If the gurds re not mutully exclusive, we use the thin br ( ) insted of the thick br ([]). [G] is used s shorthnd for [G skip]. Repetition: *[G 1 P 1 []...[]G n P n ]. This sttement is executed by choosing one of the true gurds nd executing the corresponding sttement, repeting until ll gurds evlute to flse. If the gurds re not mutully exclusive, we use the thin br ( ) insted of the thick br ([]). *[P] is used s shorthnd for *[true P]. Probe: The boolen A is true if nd only if communiction on chnnel A cn complete without suspending. Probes re only llowed to occur in the gurds of selection sttements. Sequentil omposition: P; Q. This sttement mens execute sttement P, nd then execute sttement Q. Prllel omposition:p Q. This sttement mens execute sttement P, while simultneously executing sttement Q. Simultneous omposition: P Q. This sttement mens execute chnnel ctions P nd Q such tht they begin nd complete simultneously. This composition ws introduced in [7] nd replces composition of Mrtin [3]. Unlike the composition, it hs well-defined definition in Two-phse HP, nd will dedlock when composed in prllel with itself. binds more tightly thn ;, which in turn binds more tightly thn. Wek Firness oncurrent execution of HP processes is ssumed to be wekly fir, mening tht every continuously enbled ction will eventully be given chnce to execute. B. HSE Hndshking Expnsion (HSE) is subset of HP, where ll ctions on chnnels (communiction, probes) re trnslted into Boolen vribles, nd ll non-boolen dt representtions re given Boolen representtions.. PRS A Production Rule Set (PRS) is set of production rules, ech of the form: G t where t is simple boolen ssignment, nd G is boolen expression, known s the gurd of the production rule. We require few properties of vlid PRS: Non-Interference Production rules G + x nd G x re sid to be non-interfering in computtion if nd only if G + G is n invrint of the computtion. A vlid PRS must only contin non-interfering rules, s interfering rules correspond to short circuit. Stbility A production rule G t is sid to be stble in computtion if nd only if G cn chnge from true to flse only fter the ssignment on t hs completed. A vlid QDI PRS will only contin stble production rules. A PRS is executed s stte trnsformer, where ny of the rules whose gurds re stisfied by the current stte my execute, modifying the stte with their ssocited boolen ssignment. REFERENES [1] J. OLery, X. Zho, R. Gerth, nd.-j. Seger, Formlly verifying ieee complince of floting-point hrdwre, Intel Technology Jounl, Q1 99. [2]. Hore, ommunicting sequentil processes, in ommunictions of the AM, vol. 21, no. 8, August 1978, pp [3] A. J. Mrtin, ompiling communicting processes into delyinsensitive VLSI circuits, vol. 1, no. 4, pp , [4], Tomorrow s digitl hrdwre will be synchronous nd verified, in Informtion Processing 92, Vol. I: Algorithms, Softwre, Architecture, ser. IFIP Trnsctions, J. vn Leeuwen, Ed., vol. A-12. Elsevier Science Publishers, 1992, pp [5] S. F. Smith nd A. E. Zwrico, orrect compiltion of specifictions to deterministic synchronous circuits, in Forml Methods in System Design, 7: Kluver Acdemic Publishers, 1995, pp [6] I. D. Bxter nd M. Mehlich, Reverse engineering is reverse forwrd engineering, Working onference on Reverse Engineering, [7] R. Mnohr, An nlysis of reshuffled hndshking expnsions, in Asynchronous ircuits nd Systems, ASYN Seventh Interntionl Symposium on, 2001, pp [8] S. M. Burns, Performnce nlysis nd optimiztion of synchronous circuits, Ph.D. disserttion, liforni Institute of Technology, December [9] A. Lines, Pipelined synchronous circuits, Mster s thesis, liforni Institute of Technology, [10] M. Ercegovc nd T. Lng, Digitl Arithmetic. Morgn Kufmnn, [11] A. V. Aho, M. S. Lm, R. Sethi, nd J. D. Ullmn, ompilers: Principles, Techniques, nd Tools (2nd Edition). Addison Wesley, August [12] J. Tierno, R. Mnohr, nd A. Mrtin, The energy nd entropy of vlsi computtions, in Advnced Reserch in Asynchronous ircuits nd Systems, Proceedings., Second Interntionl Symposium on, mr 1996, pp [13] T. K. Lee, A generl pproch to performnce nlysis nd optimiztion of synchronous circuits, Ph.D. disserttion, liforni Institute of Technology, My [14] S. M. Burns, Automted compiltion of concurrent progrms into selftimed circuits, Mster s thesis, liforni Institute of Technology, [15] K. vn Berkel, J. Kessels, M. Roncken, R. Seijs, nd F. Schlij, The vlsi-progrmming lnguge tngrm nd its trnsltion into hndshke circuits, in Proceedings of the conference on Europen design utomtion, ser. EURO-DA 91. Los Almitos, A, USA: IEEE omputer Society Press, 1991, pp [16] K. Vn Berkel, Hndshke ircuits: An Asynchronous Architecture for Vlsi Progrmming, ser. mbridge Interntionl Series on Prllel omputtion : 5. mbridge University Press, [17] M. vn der Goot, Semntics of vlsi synthesis, Ph.D. disserttion, liforni Institute of Technology, My 1995.