Address Register Assignment for Reducing Code Size

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1 Address Register Assignment for Reducing Code Size M. Kndemir 1, M.J. Irwin 1, G. Chen 1, nd J. Rmnujm 2 1 CSE Deprtment Pennsylvni Stte University University Prk, PA {kndemir,mji,guilchen}@cse.psu.edu 2 ECE Deprtment Louisin Stte University Bton Rouge, LA jxr@ee.lsu.edu Abstrct. In DSP processors, minimizing the mount of ddress clcultions is criticl for reducing code size nd improving performnce since studies of progrms hve shown tht instructions tht mnipulte ddress registers constitute significnt portion of the overll instruction count (up to 55%). This work presents compiler-bsed optimiztion strtegy to reduce the code size in embedded systems. Our strtegy mximizes the use of indirect ddressing modes with post-increment nd post-decrement cpbilities vilble in DSP processors. These modes cn be exploited by ensuring tht successive references to vribles ccess consecutive memory loctions. To chieve this sptil loclity, our pproch uses both ccess pttern modifiction (progrm code restructuring) nd memory storge reordering (dt lyout restructuring). 1 Introduction Address clcultions ply key role in determining code qulity in DSP processors since instructions tht mnipulte ddress registers constitute significnt portion of overll instruction count. For exmple, it ws found tht for set of codes from MediBench suite ( populr benchmrk suite for embedded systems) running on Motorol s DSP56000 processor, nerly 55% of the instructions re used to mnipulte ddress registers through explicit lods nd stores [15]. Consequently, optimizing ddress code genertion by eliminting s mny explicit ddress register lods s possible cn result in significnt improvements in code size nd performnce. Note tht code size improvements re very importnt not only becuse code size directly determines the cpcity of the customized instruction memory (hence, its cost) in n embedded system, but lso becuse smller instruction memory mens lower power consumption. Address clcultions in modern DSPs such s NEC 7701, Motorol DSP56000, Anlog Devices ADSP21xx, nd Texs Instruments TMS320C5x re done in ddress genertion units (AGUs). An AGU contins number of G. Hedin (Ed.): CC 2003, LNCS 2622, pp , c Springer-Verlg Berlin Heidelberg 2003

2 274 M. Kndemir et l. ddress registers, the contents of which cn be incremented or decremented in prllel with the ongoing ctivity in the min dtpth. The instruction formt for such processors llows one to encode CPU ctivity nd postincrement/decrement of n ddress register in single instruction. Thus, using post-increment/decrement opertions insted of explicit ddress register lods enhnces on-chip prllelism (performnce) nd reduces code size (s no seprte instruction is necessry to updte the ddress register). Cintr nd Arujo [3] report tht lthough some of the register increment/decrement opertions cn be ccommodted in VLIW instruction slots, modern VLIW DSP rchitectures lso hve uto-increment nd uto-decrement modes; this is becuse exploiting these modes effectively sves one instruction slot which might be used for some other opertion. An optimizing compiler cn exploit these post-increment/decrement opertions by performing computtion nd dt trnsformtions s well s by ssigning vribles to ddress registers optimlly. Consider the following scenrio where three sclr vribles c,, nd b re to be ccessed in the order c,,b in given DSP code. Also ssume tht the AGU in question hs single ddress register tht cn be post-incremented/decremented by 1 nd tht these three vribles re stored in memory in the order, b, c. The code for implementing this sequence of ccesses uses three steps. The first step lods the ddress register with the ddress of c (the first vrible in the ccess sequence). To ccess the vrible next, the second step lods the ddress of into the ddress register. In ccessing the vrible, post-increment opertion cn be used to modify the content of the ddress register so tht it points to b which will be ccessed next. In the finl step, the vrible b is ccessed. Overll, we need to perform two explicit ddress register lods. In ddition to being wste of mchine cycles, this increses code size nd thereby the instruction memory size, which is t premium in mny embedded designs. We cn reduce this overhed of explicitly updting the ddress register by using better choice of the order in which the vribles re stored in dt memory. Insted of the storge order, b, c in the previous scenrio, we cn eliminte one of the two ddress register lods if we use the storge order c,, b. In this cse, first, we lod the ddress register with the ddress of c nd post-increment the ddress register to mke sure tht, fter the execution of the sttement tht ccesses c, it will point to the next loction (which contins ). Next, we ccess the vrible, nd use gin post-increment to mke the ddress register point to the vrible b. Finlly, we ccess the vrible b. This problem of determining the most suitble storge order of vribles is clled the offset ssignment problem nd hs been prtilly ddressed by Brtley [1], Lio et l. [10,11], nd others (e.g., [9,15]). Bsiclly, these solutions first determine suitble storge order for vribles nd then ssign ddress registers to these vribles to minimize the number of ddress register lods. In essence, since we re determining the contents of the ddress register(s) before ech vrible ccess, this problem cn lso be defined s the ddress register ssignment problem.

3 Address Register Assignment for Reducing Code Size 275 A mjor limittion of the techniques proposed so fr for the ddress register ssignment problem is tht they either focus only on modifying the storge order of vribles (e.g., [10,11]) or only on modifying the intr-sttement ccess pttern using commuttivity nd ssocitivity trnsformtions (e.g., [13]). In this work, we present frmework tht considers both computtion-bsed (intrsttement nd inter-sttement) trnsformtions nd storge-bsed optimiztions in unified setting for reducing the code size of given ppliction; tht is, our min objective is to sve the code spce. More specificlly, this work mkes the following contributions. (1) It presents n lgorithm bsed on ccess pttern modifiction tht mkes efficient use of post-increment/decrement ddressing modes in DSPs. This lgorithm ssumes fixed storge order for vribles nd restructures the code to exploit these ddressing modes. This lgorithm is more generl thn the one proposed in [13] s it considers both intr-sttement nd inter-sttement trnsformtions. (2) It gives n lgorithm tht modifies n ccess pttern (ccess sequences), given prtilly-fixed storge order. A prtilly-fixed storge order is storge order in which the memory loctions of only subset of the vribles re fixed. (3) It combines these two lgorithms with the storge order-bsed optimiztion strtegy (i.e., offset ssignment) developed by Lio et l. [11], nd presents unified pproch (which is demonstrted to be superior) to hndle the offset ssignment problem for given control flow grph. 2 Review of Offset Assignment The offset ssignment problem [10] is one of ssigning frme-reltive offset (i.e., storge loction) to ech vrible in the code in order to minimize the number of ddress rithmetic instructions (tht is, the instructions tht lod new vlue to the ddress register) required to execute the code. The cost of n offset ssignment is defined s the number of such instructions. Given code sequence, we cn define unique ccess sequence for it. In n opertion = b op c, where op is some binry opertor, the ccess sequence is given by b, c,. The ccess sequence for n ordered set of opertions is simply the conctented ccess sequences for ech opertion tken in order. For exmple, for the code frgment = c + d d = d + c + b + c + the ccess sequence is c, d,, d, c, b, c,, d, ssuming tht ddition is left-ssocitive. Let us ssume tht the vribles in this code frgment re stored in memory in the following order:, b, c, d. The cost of given storge sequence (offset ssignment) is the number of consecutive ccesses (in the ccess sequence) for which the ccessed vribles re not ssigned to djcent loctions in memory. Therefore, the cost of the offset ssignment given bove is four s there re four trnsitions in the ccess sequence between non-djcent vribles.

4 276 M. Kndemir et l. The objective of the offset ssignment problem is to determine storge order for vribles such tht the cost will be minimum. Lio [10] showed tht the offset ssignment problem is equivlent to the Mximum Weighted Pth Cover (MWPC) problem nd proved tht it is NP-complete. His heuristic solution ws lter improved by Leupers nd Mrwedel [9] who presented tie-breking strtegy for chieving better storge ssignments. 3 Computtion Restructuring for Fully Fixed Storge Sequence Code size reduction using ddress register ssignment is chieved by mking the ccess sequence (i.e., the order in which the vribles re ccessed) nd the storge sequence (i.e., the storge order of the vribles in memory) comptible. In prctice, it is possible to do either of the following: modify the ccess sequence for fixed storge sequence, or modify the storge sequence for given fixed ccess sequence. In this section, we discuss strtegy tht dopts the former pproch s opposed to Lio s scheme [10] which tkes the ltter pproch. In this work, we pply code trnsformtions to high-level intermedite representtion (IR) of the code where optimiztions such s conventionl (e.g., grph coloring-bsed) register lloction nd common subexpression elimintion hve lredy been performed. This IR hs sttements very similr to high-level source sttements. In the reminder of this presenttion, when we mention sttement, we ctully refer to this IR-level sttement. However, to mke the presenttion cler, we use source-level (C-like) sttements. Consider, sttement of the following form = b + c Let us ssume tht the mchine hs single ddress register nd tht the storge sequence is c, b,. The ccess sequence in this exmple is b, c,, which is different from the storge sequence. As result of this, going from vrible c to vrible incurs n explicit ddress register lod (since c nd re not consecutive in the storge sequence, so we cnnot use post-increment/decrement mode). Lio s pproch [10] fixes this problem by modifying the storge sequence from c, b, to b, c,. Chnging the storge sequence is vible option provided tht the vribles hve not yet been ssigned to storge loctions, or (if they hve lredy been ssigned to loctions) the cost of trnsforming the storge sequence from one form to nother (which my require copying resulting in dditionl memory requirements) does not outweigh its benefits. An ccess pttern-oriented pproch, on the other hnd, cn optimize this code by trnsforming this sttement into = c + b The new ccess sequence is c, b, which is the sme s the storge sequence. Note tht, for this exmple, just pplying commuttivity trnsformtion (n intr-sttement trnsformtion) ws sufficient to obtin the desired result. Let us consider the following code frgment with two sttements.

5 Address Register Assignment for Reducing Code Size 277 = c + e b = c + f We ssume single ddress register nd storge sequence of, b, c, d, e, f. It should be noted tht ech vrible ccess in this code frgment (under the ssumed storge sequence) will require lod to the ddress register. A storge lyout-oriented scheme would chnge the storge sequence of the vribles, but this my be too costly if the vribles hve lredy been ssigned to storge loctions (for exmple, during the optimiztion of different set of sttements tht mnipulte the sme vribles.) On the other hnd, commuttivity trnsformtion would led to = c + e b = f + c Note tht this code frgment (which is obtined from the previous one by pplying commuttivity trnsformtion to the right-hnd side of the second ssignment sttement) elimintes one of the explicit lods to the ddress register. Tht is, in going from c to b in the second ssignment sttement, we cn mke use of the post-decrement mode (s these two vribles re consecutive in memory). An inter-sttement trnsformtion, on the other hnd, cn generte the following progrm frgment b = f + c = c + e Note tht this code frgment is obtined from the originl one by interchnging the order of two sttements nd by pplying commuttivity trnsformtion to one of the sttements. In this cse, two vrible ccesses (i.e., going from c to b in the first sttement, nd going from b in the first sttement to c in the second sttement) cn be stisfied using post-increment/decrement modes. This is simple exmple tht illustrtes the benefit of inter-sttement optimiztion. However, there re some cses where it is not possible to interchnge the order of sttements due to dt dependency constrints. For exmple, in the code frgment = + c c = c + 1 interchnging two sttements would give wrong result s the vlue used for c in = + c would be different thn the one in the originl cse. Here, storge-oriented pproch (e.g., [10]), on the other hnd, could store nd c in consecutive loctions in memory, thereby leding to the effective use of postincrement nd decrement ddressing modes. The preceding exmples show tht neither storge bsed techniques nor ccess sequence (computtion) bsed techniques (intr nd inter sttement trnsformtions) dominte the other, nd unified frmework tht uses both the techniques my be needed for better results. In the rest of this section, we formulte the computtion oriented trnsformtions using grph-bsed representtion.

6 278 M. Kndemir et l. 3.1 Terminology We represent progrm using control flow grph (CFG) which is directed grph in which ech node denotes bsic block nd n edge between two bsic blocks indictes tht there is possibility tht the flow of control (during execution) my be trnsfered from one of these bsic blocks to the other. A bsic block cn be defined informlly s stright-line sequence of sttements tht cn be entered only t the beginning nd exited only t the end [16]. Consider grph G =(V,E) where V is the set of nodes (vertices) nd E is the set of edges. A pth cover (or cover) C of given grph G(V,E) is set of pths such tht every node in V is incident t some edge belonging to the chosen set of pths. In other words, we cn think of cover C(V,E ) s subgrph of G(V,E) where V = V nd E E. The length of pth is the number of edges in the pth, nd the length of cover is the sum of the number of edges of ech constituent pth. A pth tht hs the mximum length (mong ll pths in the cover) is referred to s the longest pth. 3.2 Lyout Trnsition Grph Given bsic block, we use lyout trnsition grph (LTG) to show the connections between elements tht re stored consecutively in memory. The lyout trnsition grph of bsic block is directed grph LT G(V,E), where ech node v i represents vrible tht occurs in the bsic block; nd directed edge e =(v i,v j )fromnodev i tonodev j indictes tht the vrible represented by v i is stored (in memory) next to the vrible represented by v j. Whether v i comes before v j in the storge order or fter v j is not importnt for the purposes of this work (s long s they re consecutive in memory). An LTG lso contins n edge from v i to v j if these two nodes represent the occurrences of the sme vrible. Note tht the vrible ccess pttern of progrm touches ll the nodes of the corresponding LTG. For ese of exposition, we divide given LTG into lyers, ech lyer corresponding to sttement in the bsic block. If the bsic block contins K sttements, ech vrible v i in the jth sttement from top (denoted s j where 1 j K) is ssumed to belong to the vrible set of s j ; we express this s v i s j. We will use s j to denote both the sttement nd its vrible set, where there is no confusion. A given vrible set s i cn lso be divided into two logicl subsets: one tht contins the vrible on the left hnd side (LHS), nd one tht contins the vribles on the right hnd side (RHS). For vrible set s i, the first subset is denoted by s il nd the second subset is denoted by s ir. To illustrte these concepts, consider the LTG shown in Figure 1(i) for the sttement = b + c, ssuming tht the storge sequence is c, b,. There is bi-directionl edge between c nd b (i.e., we hve directed edge from c to b nd one from b to c), nd nother bi-directionl edge between b nd. Lbeling this sttement by s 1,wehves 1L = {} nd s 1R = {b, c}. Note tht the ccess sequence for this sttement is b, c, s shown in Figure 1(iii)

7 Address Register Assignment for Reducing Code Size 279 using dshed rrows. It should lso be noted tht new ccess sequence cn be obtined by trversing the edges in the LTG in different mnner. If we strt from the vrible c, we cn first trverse the edge (c,b) nd then the edge (b,), s depicted in Figure 1(iv). Note tht this new trversl corresponds to trnsforming the sttement from = b + cto = c + b(i.e., commuttivity trnsformtion). We need to emphsize tht it my not lwys be possible to trnsform sttement bsed on its LTG. Further, not every trversl of the edges in the LTG is legl. For exmple, going from to b using the edge (,b) is not cceptble (see Figure 1(v)) s ll the right-hnd side references should be ccessed before the left hnd side reference. We cn prevent some of the trnsitions such s this by eliminting edges from the LTG tht would led to uncceptble or infesible trnsformtions. For exmple, in order to prevent trnsformtion from to b, we eliminte the directed edge from to b s shown in Figure 1(ii). Obviously, given the two legl trversls in Figures 1(iii) nd (iv), we prefer the one in Figure 1(iv) s ll trnsitions between vribles in this figure re between consecutive memory loctions, mening tht we cn use post-increment/decrement mode for these trnsitions. Another wy of expressing this is tht both the edges visited during the trversl in Figure 1(iv) belong to the LTG given in Figure 1(ii). On the other hnd, one of the trnsitions tken during the trversl in Figure 1(iii) (the trnsition from c to ) does not hve ny corresponding edge in the LTG. Therefore, the objective of trversl must be minimizing the number of trnsitions tht do not correspond to n edge in the LTG. We will formlize this concept lter. Now, let us consider the LTG given in Figure 1(vi) for the following progrm frgment. = c + e b = c + f It is ssumed here tht the storge sequence is, b, c, d, e, f. As before, trversl of the nodes of this LTG corresponds to specific ccess sequence. The defult ccess sequence is c, e,, c, f, b s shown in Figure 1(viii). Note tht different trversl of the nodes corresponds to trnsformtion of the code sequence. Here, n importnt point should be noted. In trversing the nodes (or edges), we hve restriction in the sense tht once we re in sttement we need to finish ll the nodes in the sttement before moving to node in nother sttement. Tht is, we re not llowed to go from node in s kr tonodeins k R if k k, ssuming tht ech sttement hs left hnd side vrible. The preceding discussion indictes tht we need some restrictions on the trversl order of the nodes in the LTG. For this purpose, we use modified form of the LTG clled constrined lyout trnsition grph (CLTG), nd perform our trversl on this grph. Simply, in those cses where the compiler cn detect tht vrible v i in sttement s k cnnot be ccessed immeditely fter the vrible v j in sttement s k (s k nd s k re not necessrily distinct here), the corresponding edge (if ny) from v j to v i in the LTG should be removed when constructing

8 280 M. Kndemir et l. the CLTG (Insted of deleting edges from the LTG to construct the CLTG, it is possible to directly construct the CLTG using the necessry edges, lbeit using somewht more complicted rules. The correctness of the lgorithms is not ffected by the choice of either method to construct the CLTG). A constrined lyout trnsition grph, written CLTG(V,E ), is subgrph of the LT G(V,E) such tht V = V nd E contins ll the edges in E except those tht cn led to n incorrect or infesible code trnsformtion. The construction of the CLTG subsumes both the intr-sttement constrints (i.e., evlution rules tht need to be obeyed when processing n RHS expression) nd the inter-sttement constrints (i.e., dependence nd other constrints between sttements). For exmple, CLTG cnnot contin n edge between the vrible occurrences of the right hnd sides of two different ssignment sttements. In mthemticl terms, n edge e =(v i,v j ) E does not belong to E if v i s kr nd v i s k R, where k k. Figure 1(vii) depicts the CLTG for the LTG in Figure 1(vi). Note tht the defult trversl (ccess sequence) given in Figure 1(viii) does not use ny of the edges in the underlying CLTG. Consequently, n explicit ddress register lod is necessry prior to ech vrible ccess. Now consider the trversl given in Figure 1(ix). In this cse, the new ccess sequence corresponds to trnsformtion in which the right hnd side of the second sttement is trnsformed using commuttivity. Note tht one of the trnsitions in this trversl (i.e., the one from c to b) hs corresponding edge in the CLTG given in Figure 1(vii). Finlly, let us focus on the trversl given in Figure 1(x). The trnsformtion corresponding to this trversl is one of interchnging the order of the two sttements nd pplying the commuttivity trnsformtion to one of the sttements. In this trversl, two trnsitions, one going from c to b nd the other going from b to c hve corresponding edges in the CLTG. These two exmples in Figure 1 show tht the preferred trversl must mximize the number of trnsitions tht hve corresponding edges in the underlying CLTG. In other words, it should minimize the number of trnsitions tht do not hve corresponding edges in the CLTG. It should be noted, however, tht lthough given CLTG shows possible legl trnsitions between nodes, it is still possible to generte n illegl trversl (ccess sequence) on the CLTG. For exmple, by itself, ccessing two nodes v i nd v j consecutively my not brek ny dependence; however, fter this modified ccess sequence, it my not be possible to generte legl code due to new restriction (in the ccess order) resulting from the sid trnsition between v i nd v j. 3.3 Trversing the CLTG We formulte the problem of modifying given bsic block code for effective use of the ddress register(s) s one of determining pth cover nd trversl order in the CLTG. We ssume for now tht the AGU hs only single ddress register.

9 Address Register Assignment for Reducing Code Size 281 (i) b c b c (ii) (iii) b c (iv) b c (v) b c (vi) c e b c f (vii) c e b c f (viii) c e b c f (ix) b c c e f (x) c e b c f Fig. 1. (i-v) LTG, CLTG, nd different trversls for n ssignment sttement under the storge sequence c, b,. (vi-x) LTG, CLTG, nd different trversls for progrm frgment under the storge sequence, b, c, d, e, f. Leglity. In order to generte correct code (tht is, to preserve the originl semntics of the bsic block), we impose the following conditions on the trversl order: (1) Ech node in the LTG (i.e., vrible occurrence in the bsic block) should be visited. (2) For given lyer in the LTG corresponding to the sttement s k, ll nodes in s kr should be visited before ny node in s kl. (3) Once the trversl reches the lyer corresponding to the sttement s k,it should finish ll the vribles in tht lyer (i.e., the set s kl s kr ) before moving to nother lyer. (4) All the dt dependences nd other restrictions such s ltency constrints or expression evlution constrints should be observed. Condition (1) indictes tht ech vrible should be touched (by ny legl execution of the code). We enforce Condition (4) by ensuring tht we do not mke trnsition from v i s k to v j s k (even if v i nd v j re consecutive in memory) when there is dt dependence from s k to s k. To enforce Condition (2), we do not llow trnsition from the node v i s kl tonodev j s kr.to enforce Condition (3), we disllow trnsitions between node v i s kr nd ny node v j s k R for k k. A trnsition from node v i s kl tonodev j s k L (where k k ) is llowed only if s k hs no vribles on the right hnd side (i.e., s k R = ). Also, there cnnot be trnsition from node v i s kr tonode

10 282 M. Kndemir et l. v j s k L (where k k ) unless s k hs no vrible on the right hnd side (i.e., s k R = ) nd s k hs no LHS vrible, which cnnot occur in our frmework. (i) (ii) c b c b f d e f d e d d c f c f d d f d d f (iii) c b f d e * * d * * c f * d d * f * * (iv) c b f d e * c * f 4th pth (v) 1st pth c b f d e d d 5th pth c f 3rd pth d d * f * d d f 2nd pth Fig. 2. (i) LTG nd (ii) CLTG for given bsic block. (iii) Defult ccess sequence. (iv) Optimized ccess sequence. (v) Exmple pths in the CLTG. Profitbility. The objective of the trversl of the nodes in the CLTG is to minimize the cost of the trversl, which is defined s the number of trnsitions from node v i tonodev j such tht v i nd v j re not consecutive in the storge sequence (i.e., there is no edge (v i,v j ) in the CLTG) for ll i nd j. It should be noted tht storge sequence imposes constrints on the CLTG. If trnsition from v i to v j does not use n edge in the CLTG, this mens tht post-increment or post-decrement cnnot be used for this trnsition; thus, new vlue should be loded in the ddress register (using n explicit lod instruction), thereby incresing the code size. As result, the cost of trversl cn be viewed s

11 Address Register Assignment for Reducing Code Size 283 the number of trnsitions in the ccess sequence tht do not use n edge in the CLTG. Thus, the ddress register ssignment problem cn be re-expressed s determining trversl of the nodes in the CLTG subject to the four leglity conditions listed bove tht minimizes the number of trnsitions tht do not correspond to n edge in the CLTG. It cn be shown tht this problem is NP-complete; but, we omit the proof due to lck of spce. Let us now concentrte on the lrger bsic block given below ssuming storge sequence of, b, c, d, e, f. c = + b f = d - e - 2 = + 3d c = 2f + 4 d = d + f + Figures 2(i) nd (ii) show the LTG nd CLTG, respectively, for this code frgment under the ssumed storge sequence. Note tht, in going from the LTG to the CLTG, mny edges re dropped s they re not possible for ny legl trversl. Figure 2(iii) shows the defult ccess sequence (i.e., without ny optimiztion). This ccess sequence hs cost of eight, nd the trnsitions tht contribute to this cost re mrked using the symbol *. Our pproch, on the other hnd, results in the ccess sequence (trversl) given in Figure 2(iv). We see tht the cost of this ccess sequence is four (gin, the trnsitions tht contribute to the cost re mrked using the symbol * ). In other words, we re ble to eliminte four ddress register lods in the code. This trversl corresponds to the following trnsformed progrm: c = + b f = d - e - 2 c = 2f + 4 = 3d + d = + f + d Note tht this optimized code is obtined from the originl one through one sttement reordering (inter-sttement trnsformtion) nd number of intrsttement trnsformtions. The Algorithm nd Trnsformtions. We now present n lgorithm tht tkes s input CLTG nd genertes s output trversl (n ccess sequence) nd ll the necessry (inter-sttement nd intr-sttement) trnsformtions to obtin this ccess sequence. Given CLTG, the lgorithm first detects the longest directed pth (i.e., the pth tht contins the mximum number of edges in the sme direction). 1 It then trnsforms the portion of the CLTG (which contins subset of the sttements in the originl bsic block) in ccordnce with 1 Note tht the longest pth detection problem is hrd problem in generl. Here, we re employing heuristic.

12 284 M. Kndemir et l. this longest pth. Finding the longest pth in given directed grph is strightforwrd, nd tkes O(N 3 ) time, where N is the number of nodes in the grph [5]. Trnsforming the progrm code in ccordnce with the longest pth is more chllenging. Consider the bstrct CLTG in Figure 3 nd the longest pth shown. Note tht ech lyer in the CLTG is lbeled with different sttement id. The desired ccess sequence here is, c, h, d, f, g, b, e. To chieve this ccess sequence, the following trnsformtions need to be performed: (1) The vrible should be mde the lst vrible ccessed on the RHS of the sttement s 1 ; (2) In sttement s 2 : (i) the vrible h should be mde the first vrible ccessed on the RHS; (ii) the vrible h should be mde to immeditely precede the vrible d; (3) Sttement s 4 should be mde to immeditely follow the sttement s 2 ; nd (4) In Sttement s 4 : (i) the ccess of vrible b should be mde to immeditely follow the vrible g; (ii) the vrible e should be mde to immeditely follow the vrible b. In ddition to these trnsformtions, the trnsformed progrm should not modify the following properties of the input code (CLTG): (1 ) Sttement s 2 immeditely follows sttement s 1. (2 ) d is the lst vrible ccessed on the RHS of Sttement s 2. (3 ) g is the first vrible ccessed on the RHS in Sttement s 4. If the compiler cn find series of trnsformtions to stisfy ll these constrints, we chieve the best possible ccess sequence (for this pth). In mny cses, however, this my not be possible due to inconsistencies between the requirements given bove, or due to sitution tht does not involve the vribles on the longest pth. An exmple of the former is the inconsistency between conditions (2.i), (2 ), nd (2.ii) bove. Tht is, if we mke the vrible h the first vrible on the RHS of the sttement s 2 nd insist on keeping the vrible d s the lst vrible on the RHS, it is not possible to ccess h nd d successively s there re two more vribles on the RHS. We ssume tht these other vribles re different from those lbeled in the figure. An exmple of the second type of difficulty is the possibility tht it my not be legl to ccess the sttement s 4 immeditely fter the sttement s 2 (s required by the condition(3)). This my occur for exmple if the sttement s 3 writes vrible x (ssumed to be different vrible from the ones shown in the figure) tht is subsequently red by the sttement s 4. Although it my not lwys be possible to chieve ll of the desired trnsformtions, our pproch ttempts to chieve s mny of the desired trnsformtions s possible. Note tht this strtegy helps to use s mny edges in the CLTG s possible. After the longest pth hs been determined nd the portion of the CLTG tht contins the longest pth (tht is, subset of the sttements in the originl bsic block) hs been trnsformed, our pproch continues by selecting the second longest pth nd trnsforming the relevnt prts of the CLTG. A specil ttention is pid to ensure tht we do not modify ny prts of the bsic block

13 Address Register Assignment for Reducing Code Size 285 s 1 c s 2 f h d s 3 s 4 g e b Fig. 3. An bstrct CLTG nd the longest pth. tht hve lredy been trnsformed in ccordnce with longer pth considered erlier. In this wy, our pproch selects the next longest pth in ech step nd trnsforms the relevnt portions of the bsic block. The process stops when it is not possible to trnsform the bsic block ny further (without distorting the previous trnsformtions). In cse we hve two pths of the sme length, the current implementtion fvors the one tht leds to miniml modifiction to the originl code. In the exmple in Figure 2, following the construction of the CLTG shown in Figure 2(ii), our pproch determines the longest pth mrked s the 1 st pth in Figure 2(v). Bsed on this pth, it builds n ccess sub-sequence, b, c, d, e, f, f. This sub-sequence completely specifies the trnsformtions required for three of the five sttements in the code (i.e., the first, second, nd fourth sttements in the originl code). Note lso tht the trnsformtions performed long this pth include n inter-sttement trnsformtion. Next, it finds the pth,, (mrked s the 2 nd pth). Note tht this pth fixes the ccess sequence for the third sttement in the originl code completely s d,,. It lso specifies tht the vrible should be the first vrible ccessed in fifth sttement. After tht, the pproch selects the pth c, d, d. The (c,d) prt of this pth sys tht the fifth sttement should follow the fourth sttement in the trnsformed progrm, but this is not possible s the fourth sttement hs lredy been trnsformed, nd it now (in the trnsformed code) comes before the third sttement (in the originl progrm). The (d,d) prt of the pth, on the other hnd, is fesible, nd indictes tht d should be the lst vrible ccessed in the fifth sttement. The next pth is c, d; but, the trnsformtion implied by this is not possible. The lst pth is the one between c nd d (mrked s the 5 th pth in the figure). It implies tht d should be the first vrible ccessed in the third sttement, nd the third nd fourth sttement should be interchnged. At this point, the lgorithm hs trversed ll the pths. It next visits ech sttement, nd fixes the ccess order for the vrible whose order hs not been fixed yet. It visits the fifth sttement (in the originl code) nd mkes f the second vrible ccessed on the RHS. The finl ccess sequence is shown in Figure 2(iv).

14 286 M. Kndemir et l. 4 Computtion Restructuring: Prtilly Fixed Storge Sequence Cse So fr, we hve ssumed tht the storge sequence (storge pttern) of vribles is fixed completely. Tht is, storge loction is ssigned to ech progrm vrible. In this section, we describe how to optimize n ccess sequence when only subset of the vribles hve fixed memory loctions. This is clled the prtilly fixed storge. Specificlly, given prtilly fixed storge pttern of bsic block, we ddress two subproblems: (1) Determining the best ccess sequence for ll vribles in the bsic block, nd (2) Determining the storge sequence for the vribles in the bsic block whose memory loctions re yet to be determined. This problem is importnt becuse the compiler employs it during procedurewide optimiztion (s will be discussed in the next section). Our pproch to the problem involves the following three steps: (1) Determine the best ccess (possibly prtil) pttern for the prtil storge order given, (2) Determine the storge sequence for the vribles whose memory loctions re yet to be determined, nd (3) If there is further flexibility, then determine the best ccess pttern for the portions of the bsic block tht involves the vribles whose storge sequence ws determined in Step (2). Consider the following progrm frgment ssuming single ddress register nd prtilly fixed storge sequence of e, b, d. e = e + d = d + c f = 3c + b = ( * c) + ( * g) Figure 4(i) shows the CLTG for this bsic block, under the given prtil storge sequence. Clerly, there is just one pth in this cse. Trnsforming the code in ccordnce with this pth gives us: e = d + e f = b + 3c = d + c = ( * c) + ( * g) Note tht this trnsformtion (which corresponds to Step (1) bove) involves one sttement interchnge nd one commuttivity trnsformtion. In the next step (which is Step (2) bove), the compiler ttempts to determine storge sequence for the vribles whose storge loctions re yet to be determined. We chieve this using modified version of Lio s heuristic [10]. Lio summrizes the ccess sequence using grph clled the ccess grph. In this grph, ech vrible is represented by node nd weighted edge between two vribles corresponds to the number of trnsitions between them. Lio then runs n lgorithm on this

15 Address Register Assignment for Reducing Code Size 287 grph to select pth cover, with no node hving more thn two selected edges incident on it. The vribles represented by the nodes connected by selected edge re ssigned to consecutive memory loctions. The objective is to mximize the totl weight of the edges selected (which corresponds to cpturing the most frequent trnsitions). We modify this heuristic s follows. Let L = {v i } be the set of ll vribles v i tht hve lredy been ssigned to consecutive storge loctions. Let us ssume for now tht there is only single such set. We use b L to denote the first (strt) node of L, nd t L to denote the lst (terminl) node. Ech node in the modified ccess grph corresponds to either single node v j such tht v j / Lor block node v L tht represents L. There exists n edge between v j (/ L) nd v L if nd only if there is n edge between v j nd b L or n edge between v j nd t L. We lso keep trck of whether the edge between v j nd v L is due to (incident on) b L or t L. Figure 4(ii) shows this modified ccess grph for our exmple. Note tht this ccess grph is constructed by tking into ccount the trnsformtions (both inter-sttement nd intr-sttement) done in the previous step. Next, we run Lio s heuristic [10] on this ccess grph. Figure 4(iii) show the mximum weight cover detected by the heuristic. Afterwrds, we determine the complete storge order (sequence) for the vribles. In our exmple, this sequence is e, b, d, f, c,, g. Although it does not occur in this exmple, in some cses, the compiler my hve dditionl scope, nd my pply Step (3) bove to further modify the ccess pttern to ccommodte the needs of the vribles whose storge loctions hve been determined in Step (2). Note tht lthough we explin this strtegy ssuming tht there is single block node (L), it is strightforwrd to extend the pproch to multiple block nodes. Note lso tht since our pproch is essentilly bsic block oriented, we cn expect its effectiveness to increse when it is used in conjunction with techniques tht increse bsic block sizes (e.g., superblocks/hyperblocks). (i) e e d (ii) (iii) d c f c b c ebd c 1 f 2 g ebd c f g Fig. 4. (i) An exmple CLTG. (ii) An ccess grph for prtilly fixed storge sequence. (iii) Selected mximum weight cover. 5 Intr-procedurl Optimiztion Strtegy We now present unified strtegy tht employs both ccess sequence nd storge sequence trnsformtions to mke effective use of ddress registers. The pproch

16 288 M. Kndemir et l. works on representtion clled weighted control flow grph (WCFG), which is CFG with weighted nodes (bsic blocks). A node weight specifies the number of times the corresponding bsic block is entered (dynmic execution frequency). This is typiclly clculted by considering the execution frequencies of edges nd brnch probbilities. Our pproch to this globl (procedure-wide) optimiztion problem is s follows. After determining the execution frequencies of bsic blocks nd lbeling them, we visit bsic blocks one-by-one, nd optimize bsic block completely before moving to the next one. The optimiztion order is determined by the weights (i.e., bsic block lbels). The first (most frequently executed) bsic block is optimized using Lio s heuristic (explined in Section 2). After optimizing this bsic block, we determine storge sequence for ll the vribles ccessed by this bsic block. Note tht this step determines only prtil storge sequence (clled the storge subsequence) s the vribles ccessed by this block form, in generl, subset of ll the vribles declred in the progrm. Then, we move to the next most frequently executed bsic block, nd optimize it using the pproch explined in Section 3 or Section 4 depending on whether ll the vribles mnipulted by this bsic block hs lredy fixed memory (storge) loctions or not. After optimizing this bsic block, new storge subsequences (for the vribles ccessed by this second most frequently executed bsic block, but not ccessed by the most frequently executed bsic block) re determined. Afterwrds, we move to the third most frequently executed bsic block nd, in optimizing it (using the techniques given in Section 3 nd Section 4), we tke into ccount ll the storge sequences determined so fr. In this wy, our pproch hndles the bsic blocks one-byone, nd in optimizing ech of them, it considers the storge sequences found so fr. If t given point, the storge loction for ech vrible in the code is fixed (i.e., complete storge sequence is determined), the remining bsic blocks re optimized using the technique discussed in Section 3. At the end of the process, if the storge sequences found do not form single connected component, they re mde so using post-processing pss. 6 Summry In this work, we hve presented compiltion frmework tht employs both progrm restructuring nd storge order optimiztions to reduce the size of the generted code for embedded processors by eliminting s mny explicit ddress register lods s possible. Reducing code size is extremely importnt s in mny embedded systems reduction in code size mens reduction in memory size. Work in progress includes the investigtion of different wys of combining storge lyout nd code restructuring trnsformtions, incorporting prtitioning of vribles mong different ddress registers, nd studying the impct of SSA trnsformtion on code size. We lso pln to mke experiments with different rchitectures s different instruction set rchitectures (ISA) cn led to different code sizes [6].

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