On Computation and Resource Management in Networked Embedded Systems

Transcription

1 On Computtion nd Resource Mngement in Networed Embedded Systems Soheil Ghisi Krlene Nguyen Elheh Bozorgzdeh Mjid Srrfzdeh Computer Science Deprtment University of Cliforni, Los Angeles, CA soheil, rlene, elib, Abstrct This pper presents the ide of mnging the comprising computtions of n ppliction performed by n embedded networed system. An efficient lgorithm for exploiting the timing slc of building blocs of the ppliction is proposed. The slc of blocs cn be utilized by replcing them with slower but cheper, i.e. better, modules nd by ssigning the computtions to the proper resources. Thus, our pproch mnges the comprising computtions nd system resources nd cn indirectly ssist the reltime scheduling of computtions on system resources. This is performed without compromising the timing constrints of the ppliction nd cn led to significnt improvements in power dissiption, computtion ccurcy or other metrics of the ppliction domin. Our lgorithm is well-suited for rbitrry tree computtions. Moreover, it delivers solutions tht re desirbly close to the optiml solution. Experimentl results for number of object trcing pplictions implemented in n networed system with embedded computtion resources, exhibit significnt mount of slc utiliztion.. Introduction Tody s dvnces in technology hs enbled the integrtion of processing resources, memory blocs nd sophisticted I/O interfces into dt cquisition devices. Furthermore, these devices re often cpble of communicting with other system devices through wired or wireless networs, nd therefore form networ of embedded sensors nd computtion resources. Such networed embedded systems provide the opportunity of processing the perceived informtion loclly t the sensor nodes s opposed to trnsferring the dt to remote processing sttion, hving the sttion perform the computtion nd reding the result bc. These two pproches to dt processing, nmely loclly embedded t the sensor nodes nd trditionl centrlized processor-bsed computing schemes, introduce mny trde offs into the design spce. Sclbility, energy dissiption nd performnce of the system cn be gretly impcted by the choice of computtion scheme deployed in the system. Usully, embedded locl computing improves system sclbility nd energy dissiption. It cn lso improve system performnce for some pplictions. On the other hnd, computtion nd resource mngement becomes criticl issue in such scenrios. This pper discusses this problem in networ of embedded devices trcing moving object. Techniques to utomte the computtion nd resource mngement in such environments hve been proposed. An instnce of such system consisting of number of cmers nd controller is depicted in Figure. The figure demonstrtes n intruder detection nd object trcing system tht hs been built s prt of this wor. The system consists of multiple IQeye3 cmers [7]. The cmers communicte with the control unit in order to collborte nd distribute their informtion. Figure 2 demonstrtes the bstrct model of the resources existing in the system. A generl-purpose processor (IBM PowerPC) nd Xilinx VirtexE FPGA re embedded in ech of the cmers. Any of these embedded resources cn be used to relize the comprising bsic blocs of n ppliction. The control unit is lso cpble of performing vrious computtions nd hs more powerful resources compred to the cmers. It is lso responsible for reltime scheduling of the ppliction processes on the system resources. An ppliction, such s the forementioned object trcing ppliction, is composed of vrious bsic blocs tht perform different functionlities. To relize n ppliction, ech bsic bloc hs to be executed Fig. : The implemented trget trcing system. on one of system resources. Design librries, voltge scling, ccurcytiming trde offs nd other design choices led to different implementtions for ny of the comprising blocs of the ppliction. Ech of the implementtions hs its own specifictions in terms of timing chrcteristics, power dissiption, computtion ccurcy, etc. These specifictions, provide discrete rnge of choices for implementing bsic bloc. As highlighted in Figure 2, ny of the ppliction processes cn be executed loclly on the resources embedded in the cmers or it cn be shipped to the controller nd performed in the trditionl mnner. In prticulr, the object trcing ppliction is comprised of two bsic computtions, nmely feture selection nd feture trcing. Different versions of these two computtions hve been implemented for cmer nd controller processors. Ech implementtion offers prticulr ccurcy-ltency trdeoff. This is used to study the involved trde offs of embedded vs. trditionl processing. The qulity of n implemented ppliction is usully evluted using one of the stndrd design metrics such s power dissiption, ccurcy or timing. Optimiztion techniques for improving one of these metrics will usully hrm other chrcteristics of the design. In prticulr, intensive timing optimiztion of design usully imposes dditionl costs on its implementtion. Bsed on the ppliction domin the system power dissiption, ccurcy or response time cn be interpreted s the cost. In the conventionl implementtion process, one of the performnce metrics is usully fixed s constrint nd ny implementtion tht does not meet the constrint hs no vlue. Optimiztion procedures re then used to select the chepest design mong ll the implementtions tht meet the constrint. For design to meet the timing constrints, it is not lwys required tht ll of the comprising bsic blocs (or computtions) run with the lowest possible dely. In fct, some bsic blocs cn be slowed down which in turn might led to significnt svings in other design metrics while the design still meets the timing constrints. The process of determining the dely (ltency) vlues for comprising bsic blocs of design is clled dely budgeting. The objective of this wor is to propose provbly effective dely budgeting scheme for mnging the computtion ltencies nd resource utiliztion such tht the design timing

2 {,2} {,3} 2 3 {,5} 5 {,6} () {,4} Fig. 2: The bstrct model of the system resources. The controller hs to schedule the tss either on the cmer s embedded resources or its computtionl units. Ech cmer hs n FPGA nd processor embedded in it. constrints re met while using the slower implementtions of computtions. The proposed technique determines the dely vlues for bsic blocs of specific clss of pplictions, nmely the pplictions tht cn be modeled using rooted tree. Ech computtion ltency corresponds to specific implementtion of tht bsic bloc on prticulr resource. Therefore determining the ltency vlue for computtions ssigns the bsic blocs to different system resources, hence mnges the resources nd computtions t the sme time. The problem, s formulted in this pper, is NP-hrd. Therefore, n optiml polynomil time lgorithm to solve it does not exist unless P=NP. Given sufficient mount of time, the proposed pproximtion lgorithm cn find solutions s close to the optiml solution s desired. Section 2 summrizes the previous wors on slc mngement nd dely budgeting. Section 3 presents some bsic definitions nd nottions tht re used throughout the pper. The problem ddressed in this pper is formlly described in section 4. Section 5 describes the proposed pproximtion lgorithm nd discusses some interesting extensions. Section 6 explins clss of vision pplictions tht cn be modeled using rooted tree. A set of experimentl results supporting our lgorithm nd its solution qulity re lso reported nd finlly section 7 concludes the pper.. An Exmple Figure 3. shows n exmple of dt flow grph representing n ppliction with four bsic blocs. There re two different implementtions with different ltencies vilble for relizing ech of the blocs. The possible dely vlues for ech node re indicted in Figure 3.. The figure lso illustrtes three different implementtions of the sme ppliction. Assuming tht the entire computtion should not te more thn 8 dely units, Figure 3.b shows n implementtion tht violtes the timing constrint, becuse it tes 9 dely units to complete. Sections c nd d of the figure depict two vlid implementtions of the sme ppliction with different totl dely of the ppliction blocs. Since implementtion of bloc with relxed timing constrints cn led to significnt svings in other design metrics, one would lie to mximize the totl dely of the implemented blocs. Intuitively, the implementtion in Figure 3.c is more liely to be cheper thn the implementtion in Figure 3.d, becuse the ltter hs totl dely of units while this quntity for the former design is 4 units. This exmple shows tht n effective dely budgeting scheme cn improve the qulity of the finl design. This improvement is done through constrint relxtion s much s it does not violte the timing constrints of the design. In this pper, we present n ε-pproximtion lgorithm tht cn find solutions s close s desired to the optiml solution. 2. Relted Wor The concept of slc in more generl context hs been ddressed in the synthesis community. Slc hs been used to prioritize the scheduling of opertions [3, ]. Mobility is lso used in force directed scheduling [8, 9] iming to blnce the number of opertions in ech control step. Opertion mobility hs been guide for these lgorithms to obtin (c) Fig. 3: () A smple design with different dely choices for ech bloc. An invlid implementtion violting the timing constrint of 8 units. (c, d) Vlid designs with different timing budgets for bsic blocs homogeneous distribution of opertions to control steps while pursuing this objective. They re not prticulrly concerned with the possible wys to exploit the finl slc distribution within the schedule for improving other spects of the design. In domins other thn high-level synthesis, techniques to exploit slc to chieve certin objectives hve been proposed. For exmple, Shin nd Choi proposed scheduling lgorithm for hrd rel-time systems trgeting reduced power solution [5]. Zhu et. l. [5] describe scheduling technique to reclim the time unused by ts to reduce the execution speed of future tss. Fields et l. propose slc prediction scheme to schedule opertion in different pipelines with different speeds for energy optimiztion [2]. Zhng et l. [4] propose compiler optimiztion techniques for exploiting slc in VLIW processor with decresing the energy consumption s the objective. Chen et l. proposed slc distribution lgorithm for logic circuits [4]. Given networ of logic gtes represented with Directed Acyclic Grph (DAG), this lgorithm utilizes the vilble slc in the networ s dely budgets to logic gtes. The uthors report improvements over the Zero Slc Algorithm [0], however they hve the ssumption of continuous possible ltency vlues for different implementtions of ech gte. Hence, their pproch cnnot be directly pplied to the cses where the possible ltencies of ech module re discrete vlues. A similr problem hs been studied by Li et l. [2, 3], however they present pseudo polynomil lgorithm. Therefore, their lgorithm s running time exponentilly grows with the increse in vlues of the problem prmeters. This wor presents strongly polynomil technique for utilizing mobility of components in discrete ltency scenrio. Our lgorithm improves other metrics of the design (such s power dissiption) through slc mngement without ffecting the timing constrints. 3. Preliminries An ppliction cn be viewed s set of bsic tss tht re to be performed on the input dt in some specific order. Ech bsic ts could be complex opertion tht is invoed by the ppliction in order to ccomplish its functionlity. The dt dependency mong the comprising tss is usully modeled s directed cyclic grph (DAG). However for some clsses of pplictions, the corresponding DAG does not hve ny reconvergent fnouts. In this cse, the dt dependency mong the bsic tss cn be represented using rooted tree. Some instnces of such pplictions re mentioned in section 6. Figure 4 illustrtes n exmple of such pplictions. Ech node of the tree corresponds to module performing one of the comprising bsic tss. Throughout this pper we del with the pplictions tht cn be modeled using rooted tree. For the sme reson, we use the terms comprising ts of n ppliction nd node of the tree interchngebly. A fnin of node n is node whose output is used s n input by n. Similrly fnout of node n is node tht receives s input, the output of node n. We ssume tht ech node hs its own propgtion dely, i.e. it needs specific mount of time to generte its output fter ll its inputs become vilble. Given the rrivl times t primry inputs (PI) nd the (d) 4

3 () utilized to improve the totl power dissiption, re or ny other design metric tht contributes to the cost. Intuitively, this problem tries to relx the timing constrints of the nodes tht re not criticl to the ppliction runtime. The extr dely of such nodes cn be exploited to implement them in cheper fshion. Note tht regrdless of the user cost function, less timing-constrined module is lwys cheper to implement. Fig. 4: ()An rbitrry ppliction. A smple ppliction modeled using rooted tree required times t primry output (PO), the rrivl nd required times t the internl nodes of the tree cn be computed s follows. r n min r x d x () x FO n n mx x d n (2) x FI n where r n = Required time t the output of node n, FO n = Fnout set of node n, d x d n = Dely in node x,n, n = Arrivl time t the output of node n, FI n = Fnin set of node n. In order to compute the rrivl times, the nodes re visited in topologiclly sorted order (from PI to PO). The rrivl time for ech node is computed using Eqution 2. For required times, the nodes re still visited in topologiclly sorted order, but from PO to PI. Eqution is used to set the required time t node. We lso define the slc ssocited with node n s the difference between the required nd rrivl time t the node. The rrivl time t the PIs re ssumed to be 0. The required time t the PO depends on the timing constrints of the ppliction nd hs to be greter thn or equl to the slowest chin of tss. So ll the slcs in the networ re non-negtive. A criticl node is node whose slc is the minimum slc mong ll nodes. A criticl pth is pth from PI to PO which is mde of only criticl nodes. Any dely budgeting strtegy should be creful with existing nd newly born criticl pths s they re the slowest pths in the circuit nd hence they determine the ppliction ltency. 4. Problem Formultion The tree dely budgeting problem cn be formulted s below: Given n ppliction modeled s rooted tree with n nodes, mximum ffordble dely D mx (lso clled dely budget) for the entire ppliction nd t most m possible ltency vlues for different implementtions of ech node. The objective is to select dely vlue for ech node nd mximize the totl dely of the nodes, i.e. we would lie to me O F n i s lrge s possible, where d i is the selected dely vlue for node i. Such tht the propgtion dely from ech primry input to the primry output is not greter thn D mx. In other words, the entire ppliction cn be performed within the dely budget. This constrint gurntees n upper bound for the ppliction execution time. The ide is tht the extr dely on ech node cn led to cheper implementtion for tht prticulr node. Therefore, mximizing the totl dely of the nodes seems resonble in order to decrese the implementtion cost. The extr dely on nodes tht re slowed down cn be d i 5. An Approximtion Algorithm for Dely Budgeting Problem It is not hrd to see tht the subset problem [6, ] cn be reduced to specil cse of the formulted problem, nmely when the ppliction tree is pth of bsic blocs. Therefore the formulted dely budgeting problem is NP-hrd nd polynomil time optiml lgorithm for solving it does not exist unless P=NP [6]. In this section we present n lgorithm tht cn find solution tht is rbitrrily close to the optiml solution of the problem. Given n ppliction tree T with n nodes nd ε s the desired pproximtion ccurcy, ssume the tree nodes re scheduled using the ASAP lgorithm. Therefore ech node is ssigned to level (figure 5). Furthermore, ssume tht node i is implemented with its smllest possible dely vlue, i.e. d mini. Also, Let B D mx D cp be the extr dely budget, where D cp is the criticl pth dely of the ppliction. level 0 level L = {(d,g ),...,(d,g )} n n level 2 level 3 Fig. 5: ASAP scheduling of the tree nodes to determine their levels. For ll nodes, let cp i be the criticl pth dely of the subtree rooted t node i. We lso ssocite list L i of dely-gin pirs to node i of the tree. Figure 5 demonstrtes n instnce of this list for node n. Ech pir hs the form D G nd implies tht G is the mximum chievble gin by ssigning the extr dely D to the subtree rooted t tht prticulr node. Given prticulr node in the tree clled i, L i nd the extr dely budget B for the subtree rooted t i, let OPT i L i B denote the mximum chievble gin by ssigning B to tht subtree. By definition, for two pirs d g nd d 2 g 2 in L i, if d d 2 then g g 2. Therefore, it is pprent tht OPT i L i B cn be esily determined by conducting binry serch on dely vlues of elements in L i nd compring them with B. It follows tht once this list is generted for the primry output, OPT PO L PO B will be the best possible solution for the problem. We initilize L i with ll pirs of the form d i d mini d i d mini, where d i s re possible dely vlues for node i. d mini is the minimum of ll d i s. Note tht by definition L i contins 0 0. The initiliztion process shows the chievble gin by ssigning ll the extr dely budget to the root node nd hence forms lower bound for the potentil gin. Note tht ssigning the extr dely to the subtree root does not violte the timing constrints. For updting the lists, we trverse the nodes in the order of their levels. At ech level the dely-gin list for the nodes in tht level is updted nd this process is continued until this list is updted for the primry output. Interestingly, s the subtrees rooted t level 0 nodes contin only those nodes, the initiliztion step forms the exct lists for them. Now, we describe n lgorithm for updting the lists t ech level, ssuming tht dely-gin lists for nodes in the previous levels re lredy updted. We define two opertions for ccomplishing this ts nd prove their ccurcy. First opertion clled P T T 2 T n is pplicble to cses where the root node in tree T hs one possible dely choice equl to 0. Figure 6. shows n exmple of this cse. Clerly, Note tht ASAP is used becuse it is esy to implement. Any other topologicl ordering would be fine for our purpose.

4 The extr budget of T hs to be pplied to the fnins of node r since r hs no other option for its implementtion other thn 0. T () T 2 b r Fig. 6: () Opertion P pplies the extr dely budget to ll fnins. Opertion S divides the extr dely budget between r nd the subtree T Since subtrees T T 2 T n hve different criticl pth delys, we might be ble to slow down some of the subtrees even more thn the extr dely budget. Clerly, the mount of the extr dely for the subtree i is cp mx cp i, where cp mx is the mximum criticl pth dely mong fnins of r. It follows tht the dely-gin lists of the fnin nodes cn be optimlly merged to updte this list t node r. This process is outlined by Algorithm. Algorithm Merging fnin dely-gin lists in opertion P Input: L L b L p nd cp cp b cp p, Output: L r Let cp mx be the mximum of cp cp b cp p ; Cler L r ; for ll fnin of r do for ll pir p d g L i do Let p d g p d cp mx cp i g ; for ll extr dely budget d L i s do Add pir d g g 2 g p to L r where g i is OPT i L i d ; Return L r ; The second opertion, S T r is pplicble when the root node r hs only one fnin, nmely T (figure 6.b). In this cse, the extr budget hs to be divided mong r nd T. We combine L nd the initil vlue of L r to updte L r. The combintion process, shown in lgorithm 2, enumertes ll possible cses. Since the number of possible cses cn potentilly grow exponentilly, trimming procedure is pplied to remove some of the pirs from L r. Section 5. proves tht the trimming procedure bounds the runtime of the lgorithm by polynomil in n nd m while the solutions ept in the list re t most ε times smller thn the optiml solution. Algorithm 2 Updting nd trimming the gin-dely list in opertion S Input: L L r ε n, Output: L r Let L temp /0; for ll pir p d g L do Let L temp L temp L r d g ; /*where L r d g is the list of ll pirs in L r with dely vlues incresed by d nd gins incresed by g. */ Trim L temp by the fctor ε n; /*if there re two pirs with gins nd b in L temp such tht ε n b then remove the pir with gin b from the list. */ Let L r L temp ; Return L r ; T p p T r In order to clculte the dely-gin list t the primry output of tree, it is necessry to trnsform generl rooted tree to tree tht cn be mnipulted by two S nd P opertions. This cn be chieved by replcing ech node of the tree by two nodes nd 2. We put n edge from to 2. All fnins of become the fnins of nd ll fnouts of become the fnouts of 2. Furthermore, we ssume tht hs no dely nd tht is the only possible dely vlue for. It follows tht ll possible dely vlues for re possible for 2. Figure 7 shows the trnsformtion for smple tree. () L ={(d,g )... (d,g )} L ={(0,0)} 2 L ={(d,g )... (d,g ) Fig. 7: () Replcing node with two to enble S nd P opertions. Trnsformtion on the entire tree. Blc nodes re initilized to hve zero dely s the only possible option. As discussed erlier, level by level trversing of nodes nd pplying S nd P opertions to nodes will updte the dely-gin for ll nodes. Once this list is updted for the primry output, OPT PO L PO B reflects the mximum chievble gin. A minor modifiction of the described lgorithm cn monitor the intermedite pirs tht contribute to the gin of ech pir of L PO. These pirs will provide the proper implementtion choice for ech node. The detils of this implementtion should be strightforwrd nd re not explined in this pper. 5. Performnce Gurntee Since the trimming step introduces some error into the process, the clculted solution might not be equl to the optiml solution. In this section, we prove some upper bounds for this error nd gurntee the solution qulity within some limits. We lso prove tht the lgorithm runs in polynomil time. Theorem. The solution given by the lgorithm described in section 5, is t most ε times smller thn the optiml solution. Proof : Opertion P does not introduce ny error in the dely-gin list since it does not remove ny pir from its result. Therefore S is the only opertion tht might introduce error in the result. There re n nodes in the tree, therefore the number of performed S opertions cnnot be more thn n. For ech pir D G L r tht is removed fter the opertion S (figure 6.b), there is nother pir D! G!" # L r such tht ε n G!$ G. This implies tht D! D nd hence G! cn be utilized in cse the deleted pir ws to be chosen. Now, suppose D% G% denotes the optiml dely-gin pir t the primry output for given problem instnce. By induction on the number of consecutive S opertions, it cn be esily shown tht there is pir D! G! L PO such tht ε n n G! G% nd D! D%. It follows tht: ε & ε n n G! G% OPT PO L PO B G% This completes the proof of the pproximtion bound ' 2

5 Note tht the P opertions tht might hppen between two S opertions will lwys eep the pirs within the desired bound nd hence, will not hurt the solution qulity. Theorem 2. The forementioned lgorithm runs in polynomil time in terms of n. Proof : To prove tht the lgorithm runs in polynomil time, we bound the number of elements in L PO (nd hence other intermedite lists). Since the trimming step removes the close-enough gin elements from the lists, ech two pirs d g nd d 2 g 2 remining in list must stisfy the eqution g 2 g ( ) ε n ssuming tht g 2 ( g. Therefore the number of distinct gin vlues is t most: log *+, ε* n nd MAX ln nd MAX ln ε n nln nd MAX ε n lnn ln D MAX ε which is polynomil in terms of the lgorithm inputs nd ε. Thereby the proposed lgorithm is fully polynomil time pproximtion scheme (FPTAS) ' new fetures visible by prticulr cmer. Therefore, the trcing system needs to re-execute the feture selection lgorithm t some points of time during the ppliction lifetime. This will refresh the feture points provided to trcing lgorithm nd improves the trcing ccurcy. The pproprite time to reselect the fetures in scene depends on mny prcticl prmeters such s the required ccurcy, cmer resolution nd object s shpe nd motion. Therefore, ny instnce of the trcing ppliction would switch from feture trcing to feture selection t prticulr moment of time nd hence hs different dt flow grph (DFG). All of the DFGs representing such pplictions hve the rooted tree form. Figure 8 depicts few itertions of smple ppliction. The ctul pth tht the ppliction tes t runtime is not nown in dvnce nd depends on the events hppening in the scene. However, it is nown tht the ppliction will te one of the pths from the tree root to one of the leves...-./ Feture Selection. Feture Trcing 5.2 Extensions to Other Objective Functions The chieved gin by slowing down node might not be linerly proportionl to its dely. For instnce specific implementtion of module which runs two times fster thn nother implementtion, might not be two times more costly. In such cses, mximizing the totl dely of the nodes will not necessrily led to the mximum gin. However, in mny cses the mount of potentil gin cn still be modeled using function of dely. If gin cn be modeled using polynomil function of the module dely, the bove pproch nd lgorithm cn be directly pplied to pproximte the solution to the desired degree. In other words, the bove mentioned technique lso wors for the following objective function: O F n P d i i where P is polynomil function of dely vlues. 6. Experimentl Results In this section, we present the result of pplying our time budgeting lgorithm on severl pplictions. The lgorithm hs been implemented in C nd pplied to number of trget trcing pplictions. First, we explin the frmewor of the performed experiments nd then we report the simultion results. 6. Experiment Frmewor We hve implemented system consisting of multiple cmers with embedded computtionl resources to trc the objects moving in prticulr re (figure ). As discussed in section, the cmers hve multiple resources to relize the bsic blocs of the ppliction. Furthermore, the controller resources cn be used for executing the computtions. The prticulr ppliction of interest is object trcing which is composed of two bsic vision lgorithms, nmely feture selection nd feture trcing. The feture selection lgorithm is used to select the proper points in n imge to trc. Shrp corners with significnt color or intensity vritions re usully considered s good fetures. Given two consecutive imges ten from scene, The feture trcing lgorithm tries to find the loction of the fetures in the first imge, in the second one. This will provide informtion for following the object in the scene. Hence, the norml procedure for trcing n object is to run feture selection on the first imge nd then switch to feture trcing for the next upcoming imges. On the other hnd, the trcing lgorithm might not be ble to trc ll of the specified fetures in the second imge nd hence might lose some of the fetures for trcing in the upcoming imges. For exmple, smple run of the implemented trcing scheme on 0 consecutive imges missed 44 out of the initil 00 fetures. Moreover, the motion of the objects in the scene cn hide some of their fetures or even crete Fig. 8: A trcing ppliction modeled s rooted tree. Blc nd white nodes represent feture selection nd trcing, respecitvely. For mny prcticl pplictions the system s worst cse response time should be gurnteed. Our lgorithm mnges the computtion delys such tht the timing constrint is met nd the sum of the computtion delys re mximized. Ech dely vlue for computtion, corresponds to prticulr implementtion of tht computtion on prticulr resource. Therefore, the output mnges system computtions nd resources nd cn ssist the ts scheduling. 6.2 Dely Budgeting Results We hve implemented severl vritions of the feture selection nd trcing lgorithms. These lgorithms re executed either on the IQeye3 cmer PowerPC processor or on the controller. These implementtions perform the feture selection nd trcing tss with different ccurcy levels, hence they exhibit different ltencies. Tble summrizes the dely vlues for different implementtions of fetures selection nd trcing. The delys re mesured for single run of the lgorithm on smple imge. All other ffecting prmeters re fixed, hence we expect tht these numbers scle by porting the lgorithm to other pltforms. All numbers re reported for executing the computtions on cmer s embedded processor, except for the first line of ech section, which corresponds to running processes on the controller s processor (tble ). While controller s processor is more powerful thn processor embedded in the cmer, the communiction dely for sending the dt to the controller nd reding the result bc slows down this scheme. The significnt difference in computtion ltencies run on cmer nd the controller highlights this fct. Also, number of trcing ppliction trees hve been creted. These trees correspond to object trcing pplictions with different ccurcy requirements nd they differ in the frequency of feture selection execution. Ech tree hs bout 30 to 40 nodes. Ech node is to be implemented with the tss listed in tble. Therefore, mnul enumertion of ll of the cses is not possible nd prcticl. Figure 8 demonstrtes one smll smple trcing tree. Ech ppliction hs prticulr worst cse dely, i.e. it hs to finish within gurnteed mount of time. We ssume tht ech ppliction hs t most 0% extr dely budget. In other words, it hs to finish its computtion within 0% dely of its fstest possible implementtion. The choice of 0% extr dely budget hs been mde for experimentl purposes only. Our pproch would be effective for ny other choice of

6 Minimum Additionl Inserted Additionl Inserted Additionl Inserted Additionl Inserted Additionl Inserted Appliction possible ltency0 ms ltency0 ms ltency0 ms ltency0 ms ltency0 ms ltency0 ms ε 0 7 ε 0 5 ε 0 3 ε 0 Optiml solution pp pp pp pp pp pp pp pp pp pp Tble 2: The result of pplying the proposed lgorithm on 0 different trcing pplictions. The extr computtion dely injected into the ppliction (which cn be utilized to improve the trcing ccurcy) is mentioned. Lst column shows the mximum chievble gin for ech ppliction. All simultions were performed ssuming tht the ppliction cn be slowed down t most 0% of its mximum ltency. Algorithm Feture Selection Execution Dely 0 ms Executed on controller s cpu 3300 Bsic Implementtion 340 Modified grdient clcultion 30 Removed multi-resolution pyrmid 295 Feture Trcing Executed on controller s cpu 3345 Bsic Implementtion 360 Removed multi-resolution pyrmid 230 Removed smoothing code 80 Modified grdient clcultion 0 On demnd grdient clcultion 95 Trcing 60% of fetures 80 Trcing 30% of fetures 60 Simplified trcing for 30% of fetures 32 Tble : The implemented lgorithms nd their corresponding dely vlues in milliseconds. Ech ltency is clculted for one itertion of the lgorithm under similr conditions. Fster implementtions hve lower ccurcy levels. dely budget. The proposed lgorithm hs been implemented in C nd pplied to the forementioned pplictions. The result of the simultion is reported in Tble 2, which summrizes the result of pplying our lgorithm on 0 different object trcing pplictions. For ech ppliction, the dely of its fstest possible implementtion is mentioned. The dely of the implemented pplictions re t most 0% more thn the minimum possible dely. Severl simultions hve been performed with different pproximtion fctors(ε vlues) nd ll of them support the fct tht the dditionl inserted computtion dely into the ppliction is within the required bound from the optiml solution. 7. Conclusion We presented the ide of dely budgeting t the ppliction level by using fully polynomil ε-pproximtion lgorithm. The proposed lgorithm wors for prticulr clss of pplictions tht cn be modeled using rooted tree. It is ssumed tht ech bloc cn be implemented in number of wys nd ech implementtion hs different ltency. The proposed lgorithm ttempts to exploit the timing slc of ech bsic bloc nd replces the bsic blocs with slower implementtions without violting the timing constrints of the design. The slower implementtions of ech bloc re usully less costly in terms of conventionl design metrics such s power dissiption, re nd ccurcy. Thus, the entire procedure leds to svings in the ppliction implementtion cost or improvements in its qulity. Experimentl results to dvocte our lgorithm nd its solution qulity hve been reported. The experiments re performed on some object trcing pplictions. The result for multiple pproximtion fctors nd dely budgets support our lgorithm performnce nd solution qulity. Future wors include extension of the experiments to verify the simultion results in ction. Moreover, the clss of considered pplictions should be generlized to less restricted pplictions. 8. References [] A. Prer, J. Pizrro nd M. Mlinr. MAHA: A Progrm for Dtpth Synthesis. In Design Automtion Conference, 986. [2] B. Fields, R. Bodi nd M.D. Hill. Slc: Mximizing Performnce Under Technologicl Constrints. In Interntionl Symposium on Computer Architecture, [3] B. Pngrle nd D. Gjsi. Design Tools for Intelligent Silicon Compiltion. In IEEE Trnsctions on CAD, volume 6, pges 098 2, November 987. [4] C. Chen, X. Yng nd M. Srrfzdeh. An Effective Algorithm for Gte-Level Power-Dely Trdeoff Using Two Voltges. In Interntionl Conference on Computer Aided Design, [5] D. Zhu, R. Melhem nd B. Childers. Scheduling with Dynmic Voltge/Speed Adjustment using Slc Reclmtion in Multi-Processor Rel-Time Systems. In IEEE Rel Time Systems Symposium, 200. [6] M.R. Grey nd D.S. Johnson. Computers nd Intrctbility, A guide to the theory of NP-Completeness. W.H. Freemn nd Compny, New Yor, 979. [7] IQinVision Inc. Iqeye3 Cmer Documenttion. In [8] P. Pulin nd J. Knight. Force Directed Scheduling for Behviorl Synthesis of ASICs. In IEEE Trnsctions on CAD, volume 8, pges , 989. [9] R. Cloutier nd D. Thoms. The Combintion of Scheduling, Alloction nd Mpping in Single Algorithm. In Design Automtion Conference, 990. [0] R. Nir, C. Bermn, P. Huge nd E. Yoff. Genertion of Performnce Constrints for Lyout. In IEEE Trnsctions on CAD, volume 8, pges , 989. [] R. Rivest T. Cormen, C. Leiserson. An introduction to lgorithms. MIT Press, 990. [2] P. Agrwl W. Li, A. Lim nd S. Shni. On the circuit implementtion problem. In Design utomtion conference, pges , 992. [3] P. Agrwl W. Li, A. Lim nd S. Shni. On the circuit implementtion problem. In IEEE Trnsctions on CAD, volume 2, pges 47 56, August 993. [4] W. Zhng, N. Vijyrishnn, M. Kndemir, M. J. Irwin, D. Durte nd Y.Tsi. Exploiting VLIW Schedule Slcs for Dynmic nd Lege Energy Reduction. In Interntionl Symposium on Microrchitecture, 200. [5] Y. Shin nd K. Choi. Power Conscious Fixed Priority Scheduling for Hrd Rel-Time Systems. In Design Automtion Conference, 999.