Improved Clock-Gating through Transparent Pipelining

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1 2. Improved Clock-Gting through Trnsprent Pipelining Hns M. Jcobson IM T.J. Wtson Reserch Center, Yorktown, NY. STRCT This pper re-exmines the well estblished clocking principles of pipelines. It is observed tht clock gting techniques tht hve long been ssumed optiml in relity produce significnt mount of redundnt clock pulses. The pper presents new theory for optiml clocking of synchronous pipelines, presents prcticl implementtions nd evlutes the clock power benefits on multiply/dd-ccumulte unit design. Trnsistor level simultions show tht dynmic clock power dissiption cn be reduced by 4-6% t pipeline utiliztion fctors between 2-6%, on top of trditionl stge-level clock gting, without ffecting pipeline ltency or throughput. Ctegories nd Subject Descriptors C..3 [Processor rchitectures]: Other rchitecture Styles - Pipeline processors. Generl Terms Design, Performnce. Keywords Optiml pipeline clocking, Trnsprent pipeline, Pipeline stge unifiction, dptive pipeline depth, Dynmic pipeline scling, Clock gting, Low power, High performnce, Microrchitecture, Circuits.. INTRODUCTION Clock power is key design constrint in modern VLSI design. Despite increses in lekge power, clock power remins significnt prt of the totl power dissiption in modern microprocessors []. Clock gting hs shown to be n efficient technique to significntly reduce dynmic power dissiption [3, 5, 8, 2]. However, despite fine grined clock gting, power consumed by the clock remins mjor contributor to overll chip power dissiption. The work presented in this pper re-exmines the fundmentl clocking principles of pipelines. Our work shows tht trditionl clock gting techniques tht hve long been thought to gte the clock optimlly produce significnt mount of clock pulses tht re redundnt to the correct opertion of the pipeline. Our observtions of requirements for correct pipeline opertion rrive t novel nd prcticl clocking solution tht cn significntly reduce clock power by relxing the clocking requirements of pipelines. Permission to mke digitl or hrd copies of ll or prt of this work for personl or clssroom use is grnted without fee provided tht copies re not mde or distributed for profit or commercil dvntge nd tht copies ber this notice nd the full cittion on the first pge. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission nd/or fee. ISLPED 4, ugust 9, 24, Newport ech, Cliforni, US. Copyright 24 CM /4/8...$5.. Relted work The gol of the clocking technique presented in this pper is to reduce the clock power in trditionl synchronous pipelines. This is chieved by reducing the number of clock pulses required to propgte dt item through the pipeline. In relted work, severl techniques hve trgeted clock power reduction by reducing the number of clock pulses generted to the ltch stges in the pipeline. Clock gting [3, 5, 8, 2] hs been used to reduce dynmic clock power through ll levels of the design hierrchy from the top-most chip level down to the individul ltch level. While these techniques reduce the number of clock pulses generted in the pipeline, they ll hve one thing in common: To void dt rces through the ltches of djcent pipeline stges, ech ltch stge is clocked t lest once for ech dt item propgting through the pipeline. Collpsible pipelining techniques hve been presented to reduce clock power in pipelines [6, 7, 4]. During runtime, dt ltches in collpsed pipeline stges re mde permnently trnsprent for durtion of time. The collpsing technique subsequently reduces the number of ltches tht hve to be clocked. These novel techniques cn significntly reduce clock power, but re lso limited in two wys. First, when collpsing pipeline stges, the logic depth of ech collpsed pipeline stge is doubled (or more depending on how mny stges in sequence re collpsed). This cuses the pipeline opertion frequency to be cut in hlf (or more). Pipeline collpsing techniques subsequently trde frequency for power which my cuse significnt drop in performnce. Second, while the pipeline cn be collpsed for durtion of time during runtime, this collpsing is sttic in nture nd ffects throughput for the whole pipeline. ecuse of fundmentl limittions of these collpsing techniques, they cnnot be pplied dynmiclly on cycle-by-cycle bsis to sve clock power. F E D C ) Collpsible pipeline operting in deep mode frequency = F, throughput = T, clock power = C C ) Collpsible pipeline operting in shllow mode frequency = F/2, throughput = T/2, clock power = C/2 Figure : Prior work: sttic collpsible pipeline. Figure illustrtes the concept of sttic collpsible pipeline. In deep mode ll ltches operte in opque mode nd the pipeline cn run t full frequency. In shllow mode, every other ltch stge is mde trnsprent, collpsing two pipeline stges into one. In shllow mode, the pipeline runs t hlf frequency nd only every other ltch stge is clocked. 26

2 Contributions To summrize, the common limittion of previous work in the re of clock gting is tht, for given opertion frequency (tht my chnge during runtime), ll ltch stges required to be ctive in order to run t tht frequency hve to be clocked t lest once for ech dt item pssing through the pipeline. In contrst, the work presented in this pper cn void clocking ctive ltch stges by dynmiclly dpting to the current stte of the pipeline, on cycle-by-cycle bsis, without reducing the opertion frequency or throughput of the pipeline. Our technique is bsed on the observtion tht ltch stge only needs to go opque in order to seprte closely spced dt items in pipeline. y keeping ltches trnsprent by defult, our technique llows dt items tht re sufficiently seprted in time (clock cycles) to propgte through the pipeline without generting ny clock pulses. Such seprtion occur frequently in, for exmple, microprocessors due to pipeline stlls cused by dt dependencies. The reminder of this pper first discusses the theoreticl clocking requirements of pipelines in Section 2. Section 3 presents trnsprent pipelines t conceptul level. Prcticl reliztions for control logic nd clock blocks re presented in Section 4. Results re presented in Section 5 nd conclusions re given in Section 6. ssumptions Throughout this pper we ssume timing constrints tht re stndrd for sttic trnsprent ltch bsed pipelines. The long pth nd short pth delys through pipeline re llowed to be rbitrry nd stndrd ltch setup nd hold times pply. No new timing constrints re introduced by our technique nd the technique works with ny type of trnsprent ltches. The correct opertion of trnsprent pipeline, s presented in this pper, plces two behviorl constrints on its input nd output environment. First, trnsprent pipeline requires tht the vlue of dt item is held stble t the environment input until next subsequent vlid dt item rrives. Second, trnsprent pipeline requires tht the output environment only ltches dt indicted vlid by the trnsprent pipeline. Simply put, the environment input nd output stges need to be clock gted t the stge level in trditionl opque fshion. 2. PIPELINE CLOCKING RE-EXMINED In trditionl pipeline implementtions, fundmentl ssumption hs been tht ltch stges of pipeline must be held opque by defult in order to void dt rces between the ltch stges. Such dt rces my cuse dt residing in n upstrem stge to ccidentlly overwrite the dt in downstrem stge due to differences in the depth of logic pths between ltches. y keeping ltches opque by defult, dt rces through ltches re voided. However, this invribly results in pessimistic clocking model tht produces clock pulses tht re redundnt to the functionlity of the pipeline. The following sections propose new technique for clocking synchronous pipelines. To eliminte redundnt clocking of pipeline, we first introduce the notion of trnsprent pipeline in which ll ltches re trnsprent by defult. Second, we develop new clocking model in which ltches re mde opque (clocked) only when true dt rce is present in the pipeline. The proposed technique cn significntly reduce the number of clock pulses required to propgte dt item through pipeline. Pipeline correctness criteri true dt rce exists only if two dt items propgte through pipeline without ny opque ltch stge to seprte them. ssuming rbitrry min/mx dely of logic pths through combintionl logic nd ltches, the following criteri must be met to ensure correct opertion of trnsprent pipeline. Requirements to void dt rces: For ech pir of distinct djcent dt items (,) propgting through pipeline, where is downstrem of, t lest one opque ltch stge must seprte from (nd from in cse of circulr pipeline). For ech dt item propgting through circulr pipeline, t lest one opque ltch stge must seprte from the til of. Given these requirements to void dt rces, the criteri required to implement optimum clocking of trnsprent pipeline cn be derived. In this context the concept of stte holder is introduced. stte holder for dt item is the opque ltch stge holding the most recent vlue of stble. This is typiclly the opque ltch stge closest upstrem of the current position of. Criteri for optimum clocking of pipeline: For ech pir of djcent dt items (,) propgting through pipeline, where is downstrem of, the ltch stge for is clocked only when overwrites the current stte holder for, nd For ech dt item propgting through circulr pipeline, only one stge for is clocked, nd only once ech itertion. In non-liner pipelines, such s forks nd joins, cn hve multiple stte holders ech holding prt of the vlue of. If ny of these stte holders re overwritten, new stte holder must be provided for t its current loction in the pipeline. The consequence of the stted clocking criteri for trnsprent pipeline is tht ltch stge only needs to be clocked in order to seprte pir of dt items moving concurrently through the pipeline. This is in contrst to the trditionl clocking criteri of n opque pipeline tht sttes tht ltch stge needs to be clocked in order to propgte dt item moving through the pipeline. The first criteri is the significntly more relxed of the two nd llows for tngible reduction in required clock pulses. 3. TRNSPRENT PIPELINE: CONCEPT trnsprent pipeline keeps its ltch stges trnsprent by defult. This defult stte represents the trnsprent clock gted mode of the ltch stge (trnsprent mode). Dt rces between ltches re voided by physiclly seprting ech pir of dt items concurrently propgting through the trnsprent pipeline. pir of dt items re seprted by forcing ltch stge residing between the pir to enter n opque stte. This opque stte cn be either the opquely clock gted mode of the ltch stge (opque mode), or the norml clocking of the ltch stge (clocked mode). ltch stge in generlized trnsprent pipeline cn thus operte in three different modes. Figure 2 illustrte the behvior of five stge liner pipeline. The three middle ltch stges, 2, 3, nd 4 form trnsprent pipeline segment. These ltch stges operte in trnsprent mode by defult. Ltch stges nd 5 form the input nd output environment of the trnsprent pipeline. These ltch stges operte in trditionl opque mode by defult. vlid ltch is ssocited with ech stge to keep trck of the loction of vlid dt in the pipeline. The vlid ltches re clocked ech clock cycle. In the figure, dotted lines indicte tht the ltch is clock gted in trnsprent mode. Solid lines 27

3 stge: clock cycle: glb.clk lcl.clk lcl.clk 2 clock cycle lcl.clk 3 clock cycle lcl.clk 4 lcl.clk 5 () Trnsprent clock gting time clock cycle 2 glb.clk lcl.clk lcl.clk 2 lcl.clk 3 b lcl.clk 4 lcl.clk 5 clock cycle 3 (b) Trditionl opque clock gting Figure 3: Clock wveforms corresponding to Figure 2. clock cycle 4 clock cycle 5 clock cycle 6 clock cycle 7 b Figure 2: liner three-stge Trnsprent Pipeline indicte tht ltch is clock gted in opque mode (or is clocked the current cycle). Thick lines indicte tht the ltch is the current stte holder for the dt item mrked inside it, i.e., the ltch is responsible for holding the vlue for tht dt item stble. drk shdow indictes tht the ltch in question cptures dt item, nd lso represents the completion of one cycle of its locl clock. Consider strem of dt items entering the pipeline, where represents the bsence of vlid dt ( bubble). ssume the pipeline is initilly empty. Stges nd 5 re then clock gted in opque mode, nd stges 2, 3, nd 4 re clock gted in trnsprent mode. Clock cycle : s dt item enters stge, t clock cycle, it is cptured nd held stble in the dt ltches. Stge is now the stte holder for. Since the dt ltches for stges 2, 3, nd 4 re clock gted in trnsprent mode cn now propgte freely through this trnsprent segment of the pipeline. In the figure, the short pth propgtion of is indicted in lower cse. The long pth propgtion of is indicted in upper cse. ssuming rbitrry dely on short pths through the logic the dt inputs to the ltches of stge 5 cn chnge t ny time. Since stge 5 is clock gted in opque mode, these unstble vlues re not ltched. Subsequently, there is no risk for metstbility to occur. t the end of clock cycle, the longest pth through the logic in stge hs completed nd the output of the stge is now vlid. Clock cycle 2: t the strt of clock cycle 2, the ssocited vlid bit is cptured by the vlid ltch in stge 2 to indicte the new position of (note tht the vlid ltch is lwys clocked). Note, however, tht since no vlid dt item immeditely follows in the pipeline, stge continues to hold stble. There is subsequently no need to clock the dt ltches of stge 2. The dt ltches of stge 2 therefore remin clock gted in trnsprent mode. Clock cycle 3: In clock cycle 3, stge ltches dt item. Since stge no longer holds dt item stble, stge 3, where currently resides, must cpture nd hold stble. The dt ltches for stge 3 re therefore clocked this cycle nd re therefter held in opque gted mode. Stge is now the stte holder for, while cn stge 3 is the stte holder for. s stge 2 is trnsprent, propgte freely through stges nd 2 during this clock cycle. The short pth propgtion of is indicted with lower cse. Since the dt ltches for stge 3 re opque, cnnot propgte further thn stge 2, nd there is subsequently no risk for dt rces between dt items nd. The vlid ltches re updted to indicte tht resides in stge nd resides in stge 3. Clock cycle 4: During clock cycle 4, no dt ltches hve to be clocked s stge continues to hold stble nd stge 3 continues to hold stble. The vlid ltches re updted to indicte tht now resides in stge 2 nd resides in stge 4. Clock cycle 5: In clock cycle 5, the dt ltches for stge 3 re forced trnsprent to let propgte through nd therefter remin 28

4 E T T2 E3 go C gt C gt C go C vlid[e] vlid[e] vlid[t] vlid[t2] vlid[e3] Figure 4: Control logic implementtion for two-stge trnsprent pipeline. in trnsprent mode. t the sme time, the vlid bit ssocited with indictes to stge 5 of the output environment tht the output of the trnsprent pipeline is now vlid. Stge 5 is subsequently clocked nd cptures. The vlid ltches re updted to indicte tht resides in stge 3 nd resides in stge 5. Clock cycle 6: During clock cycle 6, no dt ltches need to be clocked s stge continues to hold stble. The vlid ltches re updted to indicte tht now resides in stge 4. Clock cycle 7: t the strt of clock cycle 7, the vlid bit ssocited with indictes to stge 5 of the output environment tht the output of the trnsprent pipeline is gin vlid. Stge 5 is subsequently clocked nd cptures. The vlid ltches re updted to indicte tht now resides in stge 5. Figure 3 illustrtes the clock wveforms generted for the exmple illustrted in Figure 2. Figure 3() illustrtes the clock wveforms when stges 2, 3, nd 4 mke use of trnsprent mode clock gting. Figure 3(b) illustrtes the clock wveforms when stges 2, 3, nd 4 mke use of trditionl opque mode clock gting. s cn be redily observed from Figure 3(), the three-stge trnsprent segment of the pipeline genertes the equivlent of only one clock pulse in order to let dt items nd propgte through it. In comprison, the trditionlly opque clock gted pipeline in Figure 3(b) hs to generte totl of six clock pulses to propgte nd through it. The exmple clerly illustrtes the potentil benefit of trnsprent mode clock gting in pipelines with moderte utiliztion fctors. 4. TRNSPRENT PIPELINE: IMPLEMEN- TTION There re mny wys to implement trnsprent pipeline. To better focus the presenttion on the min concepts of trnsprent pipelining, simple nd efficient specil cse implementtion for two-stge non-stllble trnsprent pipeline is given in this pper. The presented technique cn be redily extended to cover generl N-stge stllble pipelines s well. The specil cse implementtion covered in this section is possible when the trnsprent pipeline segment hs two stges or less. In this cse, the behvior of the opque clock gted mode equls the behvior of the clocked mode. The number of opertion modes tht ltch stge hs to support cn thus be reduced from three down to two, providing solution very similr to trditionlly clock gted pipelines. The two opertion modes tht need to be supported re () normlly clocked mode, nd (2) trnsprent mode clock gting. 4. Control logic pipeline stge tht is clock gted in trnsprent mode hs to be ble to detect whether it should switch to clocked mode or sty trnsprent. Clocked mode only hs to be entered in order to seprte two dt items propgting concurrently through the trnsprent segment of the pipeline. For given clock cycle, ny trnsprent pipeline stge should enter clocked opertion mode only under the following conditions: trnsprent pipeline stge should be clocked only if:. vlid dt is present t the input of, nd 2. vlid dt is present t the input of ny trnsprent stge upstrem of, or vlid dt is present t the input of the environment input stge. Whenever the stted conditions do not hold, the trnsprent pipeline stge should operte in trnsprent clock gted mode. Given this simple condition, it is possible to provide strightforwrd implementtion. The first condition cn be implemented by observing the vlid bit feeding into stge. From the second condition, it is cler tht look-behind function is needed to detect whether there is nother dt item upstrem of stge. This lookbehind function cn be implemented by observing the vlid bits of the upstrem pipeline stges. The clock gting conditions for the two trnsprent stges nd, with the input environment nd output environment, then become:! #"%$'&( )+*-,/ (6 3 "7$'&8)+*9,:.; 243=<4>@? *-,/.! 5 6( "7$'&8)+*9,:.; 6 3<!>C? )+*-,/.-243ED!FG*-,/.-!55!H "%$'&( )+*-,/.I6(J5 Figure 4 illustrtes the necessry control logic for n implementtion of synchronous pipeline with two trnsprent stges. 4.2 Clock block clock block (C) supporting trnsprent mode clock gting in two stge trnsprent pipeline is strightforwrd to implement. Figure 5 illustrtes trnsprent nd n opque mode clock block for two-phse clocked mster/slve pipeline. The trnsprent mode clock block contins one mster nd one slve ltch internlly. These ltches re used to ltch the clock gting signl to prevent glitches on the clock. Since both the mster nd slve dt ltches (not shown) re gted in trnsprent mode, the mster nd slve clock signls both need to be gted in their high stte (logic ). In trditionl opque clock gting the gting signl for the mster nd slve clocks cn both be tken from the internl mster ltch. However, when clock gting in trnsprent mode, the clock polrity t the input to the clock gting point for the slve clock, gte 9K in Figure 5, mkes gte 9K sensitive to glitches on the clock gting input while the internl mster ltch is trnsprent. The gting 29

5 gm mster_clk XY US CTL US glb_clk gs slve_clk OOTH gte_trns glb_clk M S ) Clock block supporting proposed trnsprent mode clock gting gm gs mster_clk slve_clk Q DDER YPSS PRTIL PRODUCTS 3/2 COMPRESS x2 3/2 COMPRESS x2 3/2 COMPRESS x2 RESULT FORWRDING Q muxsel gte_opq M y s c x z b) Clock block supporting trditionl opque mode clock gting DDER Figure 5: Two-phse clock block implementtions. DDER or signl for the slve clock must therefore be tken from the internl slve ltch insted. 5. RESULTS 5. Power contributors The power svings chievble in trnsprent pipeline depend on two fctors. First, power is sved by reducing the number of clock pulses tht re generted in the pipeline. This is due to keeping ltches trnsprent so tht dt items tht re sufficiently seprted in time cn propgte through the pipeline without requiring the ltch stges to be clocked. Second, however, dditionl power is consumed s n effect of incresed glitching on dt signls. Opque ltches ct s brriers nd prevent glitches on dt signls to propgte down the pipeline. In trnsprent segments of the pipeline, ltches re held trnsprent. Glitches cn therefore propgte down the pipeline nd cuse extr switching of wires nd trnsistors. The power svings chievble in trnsprent pipelines is subsequently trdeoff between how much power is sved by reducing the number of clock pulses tht hve to be generted versus how much dditionl power is consumed by dditionl glitching on dt signls. 5.2 Evlution results For technique tht dpts dynmiclly to the current utiliztion of the pipeline, it is importnt to evlute the mount of sved clock power over rnge of pipeline utiliztion fctors. Introduced glitch power depends on both pipeline utiliztion nd dt switching fctors. Glitch power therefore hs to be evluted over rnge of both these fctors. It is importnt to estimte worst cse bounds for the introduced glitch power in order to determine the prcticl pplicbility of trnsprent pipelines. The design chosen for evlution purposes is therefore bsed on logic with high glitch tendency. The trnsprent pipeline techniques were evluted on high frequency Multiply/dd-ccumulte (MC) unit illustrted in Figure 6. This type of design ws chosen since dd nd multiply functions re bsed hevily on XOR-type logic tht hs high glitch tendency. The unit implements 32x32 fix-point ooth encoded multiplier with finl dder. The unit fetures bypss pth to llow RESULT US Figure 6: Trnsprently pipelined MC unit. dd instructions to enter the finl dder directly without hving to pss through the multiply stges. forwrding pth is provided to the multiplier to llow multiply-ccumulte instructions. The unit ws implemented s seven stge pipeline in.3 micron technology with trget frequency of 3 GHz. Two implementtions of the unit re evluted. The first design implements trditionl opque stge level clock gting of ll pipeline stges. The second design implements stges 2, 3, 5, nd 6 in trnsprent clock gted mode (shdowed ltch stges in Figure 6). The unit ws simulted t the trnsistor level under rnge of pseudo rndomly generted input vectors for the dt inputs nd vlid inputs. The vlid signls indicte the utiliztion of the pipeline. The simultion includes ll dtpth logic, control logic, ltches, clock gting logic, clock blocks, nd clock buffers. The grph in Figure 7 illustrtes the clock power of the trnsprently clock gted pipeline stges s compred to the sme pipeline stges clock gted in trditionl opque mode over pipeline utiliztion (vlid switch fctor) rnge of -5%. The verge clock power sving over the given utiliztion rnge is 52%. The reltive clock power sving peks t 6% t pipeline utiliztion of 2%. The grph in Figure 8 illustrtes the bsolute clock power svings of the trnsprently clock gted pipeline stges over pipeline utiliztion rnge of -%. The two curves in Figure 8 illustrte the trnsprent clock power svings when the dt input switching fctor is t % nd t % respectively. The difference between the curves illustrtes the rnge between best nd worst cse glitching power introduced s result of keeping ltches trnsprent. From this grph it cn be observed tht the introduced glitch power is never more thn % of the clock power svings. This is n importnt result s it shows tht trnsprent pipelining techniques cn be pplied dvntgeously even in situtions where the dt logic hs high glitch tendency. Figure 8 lso clerly illustrtes the rnge of pipeline utiliztion for which trnsprent pipelining is most effective. The trnsprent pipeline opertes most efficiently in the utiliztion rnge between 2-6% where the clock power dissip- 3

6 2 5 Clock power (mw) (*) Totl power sving (mw) opque trnsprent (*) lso includes introduced glitch power Vlid switch fctor (%) Figure 7: Clock power dissiption for MC unit over pipeline utiliztion rnge of -5% (opque = trditionl opque stge-level clock gting, trnsprent = proposed trnsprent stge-level clock gting). Vlid switch fctor (%) Dt switch fctor % Dt switch fctor % Figure 8: bsolute clock power svings for trnsprently clock gted MC unit, on top of trditionl stge-level clock gting, over pipeline utiliztion rnge of -%. The two curves illustrte best/worst cse bounds for introduced dt glitch power. tion is reduced by 4-6%. The bsolute power sving peks t pipeline utiliztion of 5%. nother importnt thing to note in Figure 8 is tht s the pipeline utiliztion fctor increses, the introduced dt glitch power decreses s more ltch stges re opque nd therefore ct s glitch brriers. s cn be observed in the figure, the trnsprent pipeline therefore lwys performs s good s, or better, thn the opque clock gted pipeline in terms of power. Lstly, it is importnt to keep in mind tht since the presented trnsprent pipelining technique dpts dynmiclly to the current utiliztion stte of the pipeline, on cycle-by-cycle bsis, ltency, throughput, nd IPC of the pipeline re not ffected. The power sving benefits of trnsprent pipelining re chieved without ny performnce degrdtion. The only limittion in the ppliction of trnsprent pipelining techniques is in keeping the dely on the clock gting signls within the trget cycle time. This limits the prcticl length of trnsprent pipeline segment. In high frequency pipelines this limit is typiclly between three to five pipeline stges nd depends gretly on signl rrivl times, ltch count, nd wire distribution. 6. CONCLUSIONS This pper hs re-exmined the clocking principles of trditionl synchronous pipelines. It hs been shown tht clock ctivity cn be significntly reduced, on top of trditionl stge level clock gting, through use of trnsprent pipelining techniques. The pper presents new theory for optiml clocking of synchronous pipelines nd outlines the conceptul opertion of such optimlly clocked pipelines. Prcticl circuit implementtions for control logic nd clock blocks re presented nd the clock power benefits re evluted on high frequency multiply/dd-ccumulte unit design. Trnsistor level simultions of dtpth, control logic, nd clock blocks show tht dynmic clock power cn be reduced by 4-6% t pipeline utiliztion fctors between 2-6% on top of trditionl stge level clock gting. This power benefit is chieved without negtively ffecting pipeline ltency or throughput. It is lso shown tht dt glitch power introduced s result of keep- ing ltch stges trnsprent is limited to below % of the chieved clock power svings, mking trnsprent pipelining techniques pplicble even for logic with high glitch tendencies. cknowledgements. The uthors wish to thnk Peter Cook for providing the combintionl dtflow for the MC unit. 7. REFERENCES [] ROOKS, D. M., OSE, P., SCHUSTER, S. E., JCOSON, H., KUDV, P. N., UYUKTOSUNOGLU,., WELLMN, J., ZYUN, V., GUPT, M., ND COOK, P. W. Power-wre Microrchitecture: Design nd Modeling Chllenges for Next-Genertion Microprocessors. IEEE Micro 2, 6 (November/December 2), [2] CHNDRKSN,., ND RODERSEN, R. Low Power CMOS Design. IEEE Press., 998. [3] CORRELE JR.,. Overview of the power minimiztion techniques employed in the IM PowerPC 4xx embedded controllers. In Proc. Interntionl Symposium on Low Power Electronics nd Design (ISLPED) (995), pp [4] EFTHYMIOU,., ND GRSIDE, J. dptive Pipeline Depth Control for Processor Power-Mngement. In ICCD (22). [5] GOWN, M., IRO, L., ND JCKSON, D. Power Considertions in the Design of the lph 2264 Microprocessor. In DC (June 998), pp [6] KOPPNLIL, J., RMRKHYNI, P., DESI, S., VIDYNTHN,., ND ROTENERG, E. Cse for Dynmic Pipeline Scling. In CSES (October 22). [7] SHIMD, H., NDO, H., ND SHIMD, T. Pipeline Stge Unifiction: Low-Energy Consumption Technique for Future Mobile Processors. In ISLPED (ugust 23), pp [8] TIWRI, V., SINGH, D., RJGOPL, S., MEHT, G., PTEL, R., ND EZ, F. Reducing Power in High-Performnce Microprocessors. In DC (June 998), pp