Simultaneous Gate Sizing and Fanout Optimization

Size: px

Start display at page:

Download "Simultaneous Gate Sizing and Fanout Optimization"

Calvin Barnett
5 years ago
Views:

1 Smultaneous Gate Szng and Fanout Optmzaton We Cen *, Ceng-Ta Hse +, Massoud Pedram * * Unversty of Soutern Calforna + VerplexSystems,Inc. Los Angeles, CA Mlptas, CA Abstract Ts paper descrbes an algortm for smultaneous gate szng and fanout optmzaton along te tmng-crtcal pats n a crcut. Frst, a contnuous-varable delay model tat captures bot szng and bufferng effects s presented. Next, te optmzaton problem s formulated as a non-convex matematcal program. To manage te problem sze, only a small number of crtcal pats are consdered smultaneously. Te matematcal program s solved by a non-lnear programmng package. Fnally, a desgn flow based on teratve selecton and optmzaton of te k most crtcal pats n te crcut s proposed. Expermental results sow tat te proposed flow reduces te crcut delay by an average of 10% compared to conventonal flows tat separate gate szng from fanout optmzaton. 1 Introducton Tmng constrants n modern VLSI crcuts are becomng ncreasngly tgter. Gate szng and fanout optmzaton tecnques are wdely used to meet tese constrants. Gate szng reduces te crcut delay by adustng te gate szes and ence ter drve strengts and nput capactances. Fanout optmzaton aceves crcut delay reducton by speedng up te tmngcrtcal sgnals troug nserton of szed buffers. Gate szng metods can be classfed nto two categores: dscrete and contnuous. Dscrete szng metods only allow a set of dscrete szes for eac gate. Tey use combnatoral algortms or stocastc searc to determne te best sze for eac gate [1]. Contnuous szng metods on te oter and assume tat gate szes are contnuous varables and ten use matematcal programmng to formulate and solve te optmzaton problem [2]. Contnuous szng metods ave a more global vew of te soluton space and ence tend to aceve better ntal results. Te fnal qualty may owever degrade after te round off step, wc s requred because n realty tere are only dscrete szes allowed for eac gate n te ASIC lbrary. In today s ASIC desgn process owever, te number of avalable gate szes n standard gate lbrares s ncreasng, so te roundng error s becomng smaller. Furtermore, te advent of on-te-flysynteszed gate lbrares s elpng allevate ts problem furter. Fanout optmzaton metods are usually appled n a crcut one net at a tme. Tey can agan be dvded nto dscrete buffer szng and contnuous buffer szng. Te dscrete buffer szebased fanout optmzaton problem as been proven to be NP- Te Semconductor Researc Corporaton under contract no. 98-DJ-606 sponsored ts researc. complete [3]. Most of te prevous work n ts category ence assumes a fxed template for te buffer tree [4]. Usng a buffer lbrary wt contnuous szes greatly smplfes te fanout optmzaton problem [5]. Tradtonally, gate szng and fanout optmzaton are done ndvdually and at dfferent stages n te desgn process. Ts sequental flow can adversely affect te crcut performance as llustrated n te example below. (a (b Fgure 1. Motvaton for smultaneous gate szng and buffer nserton. In Fgure 1 (a, assume tat, le on a tmng-crtcal pat. (Obect szes n te scematc represent te actual gate szes n te crcut. Furtermore, assume tat te requred tmes for to are n ncreasng order. Startng from ts confguraton, a gate szng tool wll lkely sze down te non-crtcal snks, to to mprove te crtcal pat s tmng as sown n Fgure 1(b. On te oter and, startng from te confguraton n Fgure 1 (a, a fanout optmzaton tool wll lkely buld te buffer tree sown n Fgure 1 (c to solate te non-crtcal gates from. It s possble tat n Fgure 1 (b even toug, are szed down to ter mnmum allowed szes n te lbrary, ter output arrval tmes are stll earler tan ter requred tmes. So n fact, as n Fgure 1 (c, buffer b 1 can be nserted to mprove te arrval tmeatoutputof. Smlarly, n Fgure 1 (c, f, are szed down, buffer can be removed wtout volatng te tmng requrement at output of. Te gate-szng tool cannot owever add b 1 n te same way tat te fanout optmzaton tool cannot sze down,. From ts example, we can see te sortcomngs of separatng te gate szng and fanout optmzaton steps. Because eac step tres to make use of all te freedom n te optmzaton space, t does not leave muc optmzaton opportunty for te oter. At te same tme, eac step s lmted n te knd of optmzaton tat t can perform. By combnng tese two steps nto one ntegrated step, we enlarge te soluton space and aceve more optmzed results. An nterleaved buffer nserton and transstor-szng algortm s proposed n [6]. Te algortm evaluates te effect of buffer nserton and gate szng separately and mplements te one tat mproves crcut delay best. Expermental results demonstrate b1 (c

2 tat even ts greedy approac outperforms tose tat only do gate szng. Ts paper presents an algortm for contnuous-varable smultaneous gate and buffer szng. Te resultng problem formulaton become a non-convex matematcal program, ence te sze of te matematcal program must be controlled carefully to avod excessve runtmes. Ts s aceved by restrctng te number of tmng-crtcal pats tat are consdered at one tme. Te wole crcut s n turn optmzed teratvely by a sequence of tmng recalculaton and smultaneous szng and bufferng. Te rest of ts paper s as follows. model s descrbed n Secton 2. Precse problem formulaton s gven n Secton 3. Detaled algortm and flow are presented n Secton 4. Expermental results and conclusons are gven n Sectons 5 and 6, respectvely. 2 Model 2.1 Notaton Te followng notaton s used n ts paper: gate a arrval tme of s output r requred tme of s output z sze of buf, buffer can nserted from to ts snk g, gan of te buffer can buf, x, number of levels of buf, cbuf, nput capactance of te frst gate n buf, dnt, ntrnsc delay of g for a sgnal transton from te output of rdr, drvng strengt of g for a sgnal transton from te output of cload sum of nput capactances of g s fanout gates cn nput capactance of d, delay from te output of to te output of g dgate, delay from te output of buf, to te output of g dbuf, delay of te buffer can buf, C(k set of gates on te k most-crtcal pats Ne(k, set of gates tat are drect fanout gates of C(k 2.2 Tmng Analyss Let drected grap G(V, A represent te net lst of a crcut. Te vertex set V represents te set of gates n te crcut wereas te edge set A represents te source-to-snk connectons among gates. Assocated wt eac gate n te crcut, tere exst an actual output arrval tme a and a requred output arrval tme r. Te crcut desgner specfes arrval tmes for crcut nputs and requred tmes for crcut outputs from cp level consderatons. Te arrval tme a s gven by: a = max{(a + d (v v A},, Te requred tme r s gven by: r = mn{(r d (v v A},, were d, s te delay from te output of to te output of g. 's slack tme s s defned s = r a. A (tmng crtcal pat s a pat n wc te sequence of vertces (v,,v o tat comprse te pat (v prmary nputs and v o prmary outputs, all ave slack values less tan or equal to zero. 2.3 Gate Szng Model Te contnuous-varable pn-dependent gate delay model of [7] s adopted. 1 d, g dnt. Fgure 2. Gate delay model. rdr. cload d, = dnt, + rdr, cload (1 dnt, represents te ntrnsc delay of g for a sgnal transton from te output pn of.. For gates wt te same logc functon, dnt, s nearly a fxed value, ndependent of te gate sze. rdr, stands for te drve strengt of g for a sgnal transton from te output pn of. cload s te nput capactance of te gate load of g. cload = cnk. rdr, and cn k are functons of te gk= fanout( g gate sze and gate functon. Usng lnear regresson, we emprcally obtan te followng equatons: rdr, = α1+ β 1 /z cn = α2 + β2 z Equaton (1 can ten be rewrtten as: d, = dnt, + rdr,( z cn k( z k gk= fanout( g 2.4 Buffer Inserton Model Te global fanout optmzaton problem n conventonal logc syntess flow s solved net by net by applyng a local fanout optmzaton algortm. Te latter problem can be expressed as: Gven a source wt arrval tme a and a set of snk g wt capactance load cn, polarty P and requred tme r, fnd te optmum topology of buffer tree and te approprate sze for eac nserted buffer to mnmze te load seen by te source, suc tat te arrval tme of g s less tan r Buffer Can Model b x, Fgure 3. Sngle snk buffer can. AssownnFgure3,buffersbuf, nserted on te lnk from te output of to ts sngle snk g, consst of b 1,,,b x,,werex,. denotes te number of nserted buffers between and g.to calculate te delay of buf,, denoted as dbuf,, te logcal effort based delay model [8] s used. Ts model s a reformulaton of te conventonal RC model of CMOS gate delay. Te delay of buffer b, d=τ(p+g. 2 p s te parastc delay of te gate. s called te logcal effort of te gate and depends only on te topology of te gate and ts ablty to produce output current. s 1 For smplcty, te nterconnect delay as been gnored n ts formula. It s owever easy to extend ts formula to use a statstcal wre load model based on te pn-count of te net and sze of te crcut. 2 τ s a scalng parameter tat caracterzes te semconductor process beng used. It converts te unt-less quantty (p+g to d, wc as tme unts. For smplcty and wtout loss of generalty, we wll drop τ n te dscusson tat follows. b x, x, g

3 called electrcal effort (or gan, wc s defned as load/c n. p and g are ndependent of te buffer szes wle c n s te nput pn capactance of te buffer. In Fgure 3, 1, 2, x, are gans of te buffer b 1,,,b x,, respectvely. Suppose te nput capactance of g s cn. Te nput capactance of te frst buffer x, b 1 s c = cn /. 1 l l Teorem [9] Under te requred tme constrant a + ( p+ g < r for te snk, c 1 s mnmzed wen 1 = 2 = = x, =,. In ts paper, we take advantage of ts teorem, snce by mnmzng te load of, te arrval tme of s sortened, and ts drver gates are sped up. Notce tat te delay from te output of to te output of te last level buffer b x, s: dbuf, = x,( p + g, ( Buffer Tree Model Wtout nformaton about te topology of te buffer tree, te delay from te net source to eac net snk cannot be calculated correctly. Assume tat all buffer szes are avalable n te cell lbrary, te buffer tree can be manpulated by te merge and splt operatons wtout affectng te optmalty of te buffer tree [9]. Tese operatons are llustrated n Fgure 4. b 1 b 3 splt merge Fgure 4. Buffer tree merge and splt transformatons. Teorem [9] If gans of b 1,b 11,b 12 are te same, ten te tmng and nput capactance propertes are preserved by te merge/splt transformatons (cf. Fgure 4. As a result, te optmal fanout tree wt approprate buffer szes may be splt nto a fanout-free tree, wc s composed of a set of buffer cans connected at te source of te net. Te reverse s obvously true too. Hence, we can buld te buffer cans separately and ten merge tem to obtan te optmal fanout tree. Equaton (2 can be extended to multple snk buffer trees as sown n Fgure 5. Recall tat for eac snk g of,, s te gan of every buffer n buf,.,3 x,3,4 x,4 b 11 b 12 Fgure 5. Multple snk buffer tree. 2.5 Smultaneous Gate Szng and Buffer Inserton Model To express smultaneous gate szng and fanout optmzaton problem n a matematcal form, te delay model must reflect te effect of sze cange and possble nserton of a buffer can. b 3 AssownnFgure6,wecombnetegateszngandtebuffer can delay models. d, s dvded nto two parts: dbuf,, wc s te delay from s output to te buffer can s output and dgate,, wc s te delay from te buffer can s output to g s output. As before, dbuf, s calculated by Equaton (2. Notce owever tat prevously output load of te buffer can cn was a known value wereas now cn canges wt g s sze. Te load of g s not determned from ts drect fanout gates, nstead t s determned from te nput capactance of te very frst buffer n cnk te buffer can: cbuf,k : cbuf,k = x,k ( Te complete set of delay equatons s tus summarzed as: dbuf, = x, ( p + g, cn k( z k dgate, = dnt, + rdr, ( z x (3,k k (,k d = dbuf + dgate,,, were k denotes te ndex of te fanout branc of g. d,, g gk,k x,k,k x. (p+g, dnt. rdr. dbuf, dgate, Fgure 6. Gate delay model wt buffer cans. Teorem Te delay model d, of Equaton (3 s non-convex. Proof Hessan matrx F of functon f s te matrx of te 2 nd partal dervatves of f. Functon f s convex over a convex set Ω contanng an nteror pont f and only f te Hessan matrx F of f s postve sem-defnte trougout Ω [11]. Readers can easly verfy tat d, gven n equaton (3 s not postve sem-defnte. Terefore, te delay mode s non-convex.! Equaton (3 descrbes te tmng relatons n te matematcal formulaton of te smultaneous gate szng and fanout optmzaton problem (secton 3. Note wen x. s equal to 0, t means no buffer s nserted between and g,andd, becomes exactly te same as Equaton (1. Ts model consstency s of course mportant, because we do not assume any buffer tree template before te soluton s attempted, and we do not know weter or not an nserted buffer can buf, exsts. We let te matematcal programmng package determne te value of x,, and,, tat s te best topology and sze of te buffers trees. If Equatons (1 and (3 were not consstent at x. =0, for te edges wt a zero-value buffer level, te real delay calculated by equaton (1 would be dfferent from te tmng estmaton of constrants formulated based on (3. Te convergence of problem soluton would terefore not be guaranteed. Oter mportant propertes of Equaton (3 are ts contnuty and dfferentablty, wc are ndspensable to most matematcal programmng packages. 3 Problem Formulaton 3.1 Global Formulaton We would lke to capture te tmng relatons n te wole crcut n one formulaton, because suc formulaton would result n a globally optmzed soluton. Te problem s stated as:

4 mnmze s.t. cycle a Tstart v PI a cycle v PO a a + dbuf + dgate ( v,v A,, were T start s te latest arrval tme of all te prmary nputs. In ts formulaton, for eac gate tere are two varables correspondng to ts arrval tme and gate sze; for eac edge, tere are two varables correspondng to te number of nserted buffers and te buffer gan (recall tat all buffers n te same buffer can ave dentcal electrcal effort,.e. dentcal gan. Suppose te number of gates s n and te number of edges s e. Tere are (2n+2e varables. Te number of constrants s also e. Observaton: Equaton (4 s a non-convex problem because dgate, s a non-convex functon. Eac constrant of Equaton (4 s related to qute a small number of varables: a,a,x,,z,z k,x,k and,k. So te problem formulaton s very sparse. LANCELOT [12] s especally effectve n solvng ts knd of large-scale, non-lnear, sparse problem. It as been adopted n many VLSI CAD tools and sows robustness and g effcency. We use LANCELOT to solve Equaton (4 drectly on several bencmark crcuts. Altoug LANCELOT sows good performance on ts knd of problem, Equaton (3 as, n worst case, O(n 2 varables and constrants. Furtermore, te delay model s non-convex. Tese consderatons make te global optmzaton formulaton nfeasble n practce for large crcuts. 3.2 Crtcal Secton Formulaton Instead of optmzng te wole crcut n one sot, we can teratvely optmze te k most-crtcal pats of te crcut [7]. C(k s defned as te set of gates on te k most-crtcal pats n te crcut. Ne(k s defned as te set of gates wc are te mmedate fanouts of C(k. In eac teraton, C(k and Ne(k are dentfed. We only focus on optmzng tem. Te operatons performed nclude gate szng C(k, fanout optmzaton of C(k and gate szng of Ne(k. Compared to only gate szng, te topology of te crtcal pats s not fxed. Compared to local fanout optmzaton, te snks of te crtcal pats are szable, and te buffer trees are generated on te bass of wole pat delay, not for a sngle net. By carefully controllng te boundary condtons, tat s te arrval tmes of Ne(k, soluton convergence s guaranteed [7]. Note tat only te gates n C(k and Ne(k are canged, all oters are fxed, terefore te load of gates n Ne(k are not cangng. So f we guarantee tat te arrval tme of Ne(k after optmzaton s no larger tan te specfed requred tme, te arrval tme of te gates outsde of C(k and Ne(k wll not ncrease. Ts analyss gnores te reconvergent fanout ssues, and ence olds only approxmately. In practce owever, enforcng boundary constrants for Ne(k s qute effectve. Te new formulaton s gven as: mnmze cycle s.t. a Tstart v PI,v C(k a cycle v PO,v C( k (5 a a + dbuf, + dgate, ( v,v A, v C( k a r v Ne(k (4 were dbuf, and dgate, were gven n Equaton (3. δ s a parameter to control te strctness of te arrval tme requrement on Ne(k. Its value s set to less tan or equal to 1. We defne crtcal edge as an edge n grap G(V, A tat s drven by a gate n C(k. Suppose tere are n gates n C(k, wc ntroduce e crtcal edges and m gates n Ne(k. Tere are 2(n +e +m varables (arrval tme and sze for eac gate n C(k and Ne(k, buffer can level and gan for eac crtcal edge n Equaton (5. In ts way te problem sze decreases. If te crcut s small, we can ncrease k to put more gates n C(k. 4 Algortm Intal mapped crcut Tmng analyss C(k & Ne(k marked Formulate & Solve Problem (5 No Buld Buffer Trees Gate/Buffer Szng New Crcut Tmng OK? Yes End Fgure 7 Algortm flow. Te algortm flow s depcted n Fgure 7. Frst, tmng analyss s performed on te crcut network. Te k most-crtcal pats are marked. Te buffer trees, wc are drven by C(k and bult n prevous teraton, are removed suc tat te new buffer trees can be constructed from Equaton (5. Te ratonale for removng prevously constructed buffer trees s tat n ts way we allow deletng redundant or non-optmal buffer trees. Next, problem formulaton (5 s generated and passed on to te LANCELOT package. LANCELOT produces gate szes, buffer can lengts and ndvdual buffer gans. Te buffer tree for eac gate n C(k s formed by recursve mergng of te buffer cans on tat net (c.f. secton 4.2. After te fanout tree topology s decded, te algortm determnes te buffer and gate szes. In te end, a new crcut net lst s generated. Te above steps are repeated untl te tmng constrants are met. 4.1 Buffer Tree Generaton After Equaton (5 s solved, x, s usually a non-ntegral value. In realty, a feasble soluton sould be an nteger. Suppose µ 1 and µ 2 are te two nearest feasble ntegers consderng polarty requrement of x,. We round x, to te number tat satsfes te requred tmng constrant of g. If bot values meet (or volate te requred tme demand, we pck up te value tat makes cbuf,, te nput capactance of te frst gate n te tapered buffers buf,, smaller. Ts eurstc keeps te load of te crtcal gate smaller, tus reducng te arrval tme of crtcal gate. After te number of levels for eac buffer can s determned, te sze of buffers are calculated from ts level and gan. Te sze of tese buffers s agan n general a non-ntegral value, and ndeed some szes may be less tan one. Te merge operaton s done recursvely from te frst level to reduce te number of buffers and ncrease ter szes to make tem wole buffers. Te advantage of merge s tat t can mnmze te round up error due to non-ntegral buffer szes and at te same tme reduce te buffer areas. Snce te gan of eac can s calculated for

5 dfferent snks separately, ter values may not be same. Te merge transform keeps te delay uncanged only wen two brances ave te same gan. Terefore, we defne a constant ε and merge two buffers as long as te dfference of ter gans s less tan or equal to ε. 5 Expermental Results Our algortm was mplemented and run on Pentum-III 733MHz macne. Table 2 sows our expermental results for performng global optmzaton on some bencmark crcuts. Tese results correspond to te soluton to Equaton (4. Te ntal cell count and delays for all crcuts are gven n Table 1. Intally, eac logc gate s mapped to te correspondng mnmum sze cell n te lbrary. To make te comparson far, we teratvely perform bot buffer + szng (B+S and szng + buffer (S+B. Notce tat buffers nserted n teraton are kept durng sznn teraton +1, but tey are removed before buffernn teraton +1. Te delays of te frst four teratons are compared wt te delay of (one-step smultaneous buffer/szng (B/S. Te gate szng and fanout optmzaton tecnques are descrbed n [7] and [10], respectvely. Te B+S and S+B teratons converge to te fnal crcut delay only after two teratons. Te percentage mprovement of B/S over B+S or S+B s calculated as te delay of B/S dvded by te smaller of te two delays obtaned by B+S and S+B. Te mprovement of B/S over te sequental metods s an average of 5.1%. Te global formulaton s too expensve (and ndeed mpractcal to apply to large crcuts. Table 3 presents results of te teratve optmzaton metod based on Equaton (5. In eac teraton, we coose a k value suc tat te k most crtcal pats consst of about 150 gates. For te sequental metods, we perform two local teratons of B+S or S+B on te gates n te crtcal secton wereas for te B/S tecnque, we solve Equaton (5 n one sot. Crcut tmns updatng from one teraton to next. Examnng te results for te frst four crcuts n Tables 2 and 3, we note tat te delay of te crtcal secton formulaton B/S s only a lttle bt larger tan tat of te global formulaton B/S. Sequental metods owever perform worse usng te crtcal secton formulaton flow. Percentage mprovement of te B/S tecnque over sequental tecnques becomes more pronounced. Te average delay mprovement s 9.8%. Crcut Cell Crcut Cell (Intal (Intal C C C k C C C C dalu Table 1. Bencmarks nformaton. Crcut Iteratons (B/S (sec C499 D (B+S D (S+B C1908 D (B+S D (S+B C880 D (B+S D (S+B C3540 D (B+S D (S+B Table 2. Global formulaton results. Crcut (B+S (B+S (S+B (S+B (B/S (B/S Improve (% C C C C dalu C k C C Table 3. Crtcal secton formulaton results. 6 Conclusons In ts paper, we ntroduced a new delay model for descrbng gate szng wt nserted buffers. Te smultaneous gate szng and fanout optmzaton problem was formulated as a non-lnear programmng problem and solved by LANCELOT. To control te problem sze, we used an teratve flow to optmze te k most-crtcal pats. Merge and splt operatons were adopted to transform te fanout free tree to a general buffer tree. Expermental results sowed tat our smultaneous gate szng and fanout optmzaton algortm as an average delay mprovement of 9.8% compared to conventonal metods based on sequental fanout optmzaton and gate szng flow. Reference [1] O. Coudert, R. Haddad, "New Algortms for Gate Szng: a Comparatve Study", Proc. of 33rd DAC, pp , Jun [2] M. Berkelaar, J. Jess, "Gate Sznn MOS Dgtal Crcuts wt Lnear Programmng", Proc. of European DAC, pp , [3] C. L. Berman, J. L. Carter, K. F. Day, Te Fanout Problem: From Teory to Practce, Advanced Researc n VLSI: Proc. of te 1989 Decennal Caltec Conference, pp , [4] H. Touat, Performance-orented Tecnology Mappng, P.D. tess, Unversty of Calforna, Berkeley, Tecncal Report UCB.ERL M90/109, November [5] K. Kodandapan, J. Grodsten, A. Domnc, H. Touat, A Smple Algortm for Fanout Optmzaton usng Hg-Performance Buffer Lbrares, Proc. of ICCAD, pp , November [6] Y. Jang, S. Sapatnekar, C. Bam, J. Km, Interleavng Buffer Inserton and Transstor Sznnto a Sngle Optmzaton, IEEE Transactons on VLSI Systems, vol.6, No.4, pp , December [7] W. Cen, C. T. Hse, M. Pedram, Smultaneous Gate Szng and Placement, IEEE Transactons on CAD, Vol.19, No.2, pp , February [8] I. Suterland, R. Sproul, Te Teory of Logcal Effort: Desgnng for Speed on te Back of an Envelope, Advanced Researc n VLSI, Santa Cruz, [9] D. Kung, A Fast Fanout Optmzaton Algortm for Near- Contnuous Buffer Lbrares, Proc. of 35t DAC, pp , June [10] P. Rezvan, A. Aam, M. Pedram, H. Savo, Leopard: A Logcal Effort-based fanout OPtmzaton for Area and, Proc. of ICCAD, pp , November [11] D. Luenberger, Lnear and Nonlnear Programmng, Addson- Wesley, pp.180, [12] A. R. Conn, N. I. M. Gould, P. Tont, LANCELOT: A Fortran Package for Large-Scale Nonlnear Optmzaton, Sprnger- Verlag, 1992.

Priority queues and heaps Professors Clark F. Olson and Carol Zander

Priority queues and heaps Professors Clark F. Olson and Carol Zander Prorty queues and eaps Professors Clark F. Olson and Carol Zander Prorty queues A common abstract data type (ADT) n computer scence s te prorty queue. As you mgt expect from te name, eac tem n te prorty