A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network

Transcription

1 A Fst Dely Anlysis Algorithm for The Hyrid Strutured Clok Network Yi Zou 1, Yii Ci 1,Qing Zhou 1,Xinlong Hong 1, Sheldon X.-D. Tn 2 1 Deprtment of Computer Siene nd Tehnology, Tsinghu University, Beijing, , P..Chin 2 Deprtment of Eletril Engineering, University of Cliforni t iverside, iverside CA, USA stn@ee.ur.edu Astrt This pper presents novel pproh to reduing the omplexity of the trnsient liner iruit nlysis for hyrid strutured lok network. Topology redution is first used to redue the omplexity of the iruits nd preonditioned Krylov-suspe itertive method is then used to perform the nodl nlysis on the redued iruits. By proper hoie of the simultion time step sed on Elmore dely model, the dely of the lok signl etween the lok soure nd the sink node nd the skews etween the sink nodes n e otined effiiently nd urtely. Our experimentl results show tht the proposed lgorithm is two orders of mgnitude fster thn HSPCE without loss of ury nd stility nd the mximum error is within 0.4% of the ext dely time. 1. ntrodution Clok network distriutes the lok signl from the lok soure to the lol sink nodes on hip. The design of the lok network determines the lok frequeny nd the ehvior of the synhronized iruits on hip. n deep su-miron VLS tehnology, lok distriution hs eome n inresingly hllenging prolem for VLS designs,nd reful design of lok networks is essentil in high-performne VLS iruits. As the proess vrition eomes n importnt ftor in the design of lok distriution networks in deep su-miron tehnology, the portion of the lok skew introdued y the proess vritions on the wire width nd the lok uffer size n no longer e ignored. Hyrid strutures tht onsists of oth tree nd mesh strutures re more tolernt of proess vritions. Another mjor dvntge of hyrid strutured topologies is tht even very non-uniform lod distriutions hve very smll impts on the lol skew so tht hnges in lok lods or lotions use little hnge on lok timing. As result, retuning of the grid wires is rrely neessry [9]. Grid sed hyrid strutured lok networks re eoming more widely used in the topology design of lok networks. However, ompred with tree strutured lok networks, hyrid strutured lok network tht onsists of oth tree nd mesh is more diffiult for timing nlysis nd optimiztion. The root of the omplexity stems from the more omplited topology s more interonnets re present t ross nodes nd lrge numer of loops exist, whih mkes trditionl nlysis method ineffiient. As the lok frequeny lims to GHz rnge, the indutne effet n no longer e ignored espeilly when the hip hs fster on-hip rise times nd long trnsmission wire length. High order LCM iruits re typilly used y nlysis tools to otin etter ury. With VLS integrtion towrd system on hip nd shrinking feture size, the omplexities of lok networks due to extrted prsitis eome too lrge to e nlyzed effiiently y urrent trnsistor-level SPCE-like simultion tools. A fst yet urte nlysis method using high order model for the hyrid strutured topology is urgently needed for the design, nlysis nd optimiztion of high-performne lok networks. Grid sed or hyrid strutured lok network design [1] [11] use the Elmore dely model for meshes to lulte dely nd skew. Elmore dely model is widely used for fst dely pproximtion. One shortoming of this model is tht it does not inlude the indutive effets nd is first order moment pproximtion. Higher order propgtion delys n e otined through moment mthing methods suh s AWE [3], PMA [4], Multi-node Moment Mthing [5]. But they re effiient only when used to hndle the tree nd tree-like topologies. The pth tring lgorithm, whih is liner nd is the ore of the pid nteronnet Evlutor [6], is responsile for effiieny of methods in [3] [4] [5]. Those methods, however, eome less effiient s iruit mtries with oupling loops require more (t lest super-liner) CPU time to solve. Therefore, fst yet urte lgorithm for the timing nlysis of the hyrid strutured lok networks is still urgently needed for topology design nd post-design verifition. n this pper, we propose n effiient method to nlyze the mesh-tree (hyrid) strutured lok networks. Clok networks modeled s LC iruits re used in our method for high ury. Sine the prolem size is very lrge for rel designs, we use divide-nd-onquer sheme to perform the omplexity redution. The resulting lgorithm n give fster yet more urte results for hyrid strutured lok network over existing methods. There re mny underlying tree strutured wires driven y the overlying mesh, eh tree rnh struture n e redued into trnsient iruit soure with n equivlent ondutor. Also, the nodes on the mesh struture just

2 onneting to resistors nd indutors n lso e simplified. The use of lumped trnsmission LC models inreses the prolem omplexity. But the LC hins originte from the lumped trnsmission model n lso e simplified vi topology redution. After the order redution sed on topology is finished, the system equtions formulted y Nodl Anlysis (NA) re solved y preonditioned Krylov-suspe itertive method [7], whih shows n lmost liner performne in prtie. With the simultion results, the dely time etween the soure nd sink nodes n e otined y interpoltion. Sine the dely times of the sink nodes spn smll period in the trnsient wveforms, we n further derese the steps to get etter simultion results sed on Elmore dely estimtion for simultion intervls. Experiments show tht our method is two orders of mgnitude fster thn Hspie without introduing ny signifint error. We orgnize this pper s follows: Setion 2 provides our simultion model nd the formultion of Nodl Anlysis in the time domin. Setion 3 presents the detiled nlysis of the struture redution vi equivlent iruit model. Setion 4 desries the dely nlysis through hierrhil simultion step tuning. The overll lgorithm is lso given in this setion. At the end of this pper, experimentl results nd onlusion re proposed. We use the LC model to desrie the eletromgneti ehvior of lok networks. The distriuted trnsmission wire etween ny two nodes re modeled s hin of onneted resistors nd indutors with pitors etween the wire nd ground s shown in Figure 2 where the mesh struture onsists of oth nd L, C prmeters of metl wires. Also, the wires in the tree strutures re lso modeled s LC iruits just like the wires in the mesh strutures whih is shown in Figure 3 elow: 2. Desription of the Simultion Model 2.1 Hyrid Strutured Clok Network Our topology is tree-mesh-tree hyrid struture tht is very suitle in SOC tehnology [8]. n our simplified topology for timing nlysis, lok soure, whih is treted s voltge soure in trnsient simultion, drives glol H or X tree tht in turn diretly drives the mesh struture. And the lol trees try to get the lok signl from the mesh struture nd trnsmit the signl to the sink nodes. Figure 1 shows the hyrid lok struture tht we use in our nlysis nd simultion [8]. n order to effiiently simulte the timing hrteristi of eh wire, we further divide eh wire into severl LC setions to get lumped trnsmission line model. Figure 4 shows the lumped trnsmission line model [10]. We inorporte the lumped trnsmission line modeling in our test se genertions. Fig 4 Trnsmission Line interonnet model n our model, the ottom lol tree strutures n exist t ny inner nodes of the mesh networks nd the trnsmission line inner nodes. The positions of tree roots, the depths of trees nd the rnh numers re rndomly generted. Similr to models proposed efore, we only onsider the lod pitne in the sink node sine the lod resistne of the lok pin of MOSFETs is very lrge. The whole model for the lok networks is dequte nd urte. Figure 1 Tree-Mesh-Tree Hyrid Clok Network 2.2 LC Simultion Model 2.3 Nodl Anlysis for Generl LC iruits Modified Nodl Anlysis provides good solution for

3 generl iruits. However, it my led to iruit mtries tht re non-symmetri positive definite, whih my use the itertive method to onverge slowly. As result, we use the nodl nlysis to void the prolem. The voltge soure t the lok soures n lso e modeled s urrent soures to void the introdution of extr urrent vriles. We first trnsform the differentil equtions into lgeri equtions y using trpezoidl differene method: Suppose h e the nlysis time step. For pitors, this finite differene eqution will hve 2C 2C k 1 = V k 1 ( V k + k ), (1), + h, + h,, where V, k,, k, V, k + 1, denote the rnh voltge nd, k + 1 rnh urrent of the pitor on step k nd step k+1 respetively nd C is the vlue of the pitor. Similrly the urrent through n indutor L t step k+1 is: h h L k 1 = VL k 1 + ( VL k + L k ), (2), + 2L, + 2L,, The ompnion models of L nd C omponent is shown in Figure 5 where G,G L stnd for 2 C h, respetively; S, h 2 L S L stnd for G V,i +,i nd G L V L,i + L,i in (1) nd (2) respetively. After repling ll the pitnes nd indutnes in the network with their ompnion models, we otin pure resistor equivlent network. One the topology of the lok network nd prmeters of its omponents re given, resistors in the equivlent network remin the sme t ny nlysis time point under the fixed time step, only the equivlent urrent soures in the network hnge from time to time. The equivlent resistor network n e desried y the Nodl Anlysis eqution elow: n t t Gnxn Vn = Sn (3) gii = - gij (4) j= 1, j i Here G nxn is n x n symmetril mtrix with element g ij (i j) stnds for the ondutne etween node i nd j, V n t is the vetor of node voltge t time point t, S n t is the urrent vetor t time point t with eh element stnding for the equivlent urrent tht flows from node to the ground. 3. Struture Complexity edution The iggest diffiulty in performing nodl nlysis of LC modeled lok network is its huge iruit mtrix size. edued order trnsfer funtion methods n signifintly redue the order of the prolem ut itself is lso time intensive lgorithm. We wnt to demonstrte tht through struture or topology omplexity redution, we n lso redue iruit omplexity while suh redution is simple nd esy for implementtion. 3.1 edutions of Series or Prllel Conneted Elements Ciruits tht hve prllel or series onneted elements nmed type 1 nd 2 in Figure 6 n e simplified to equivlent one vi simple lgeri opertions (5) (6), nd type 1 nd type 2 iruits n lso hnge k nd forth y (7). GE = G1+ G2, E = 1+ 2 (5) G1 G2 GE =, VE = V 1 + V 2 (6) G1+ G2 E VE = G 3.2 Simplifition of Tree Strutures (7) n order to simplify the tree strutures t the ottom of the whole topology, equivlent ondutne nd urrent soure of the tree must e omputed first. Beuse rnhes would hve the sme prent node (the numer of hildren it hs is lled its degree), we must strt t the ottom of the tree. We redue lef rnhes first (node with degree 0). One rnh hs een redued, we sutrt its prent node s degree y 1, nd dd ddress informtion of its prent node into root hin while oeffiients informtion of this rnh is dded into rnh hin. Then we serh the new root hin mde to find whether new lef nodes exist. f they do, we repet this proess until no new lef nodes n e found. When the tree is redued ompletely, we otin the equivlent ondutne of the tree. Figure 7 shows how to simplify rnh. n Eq. (8) G * is used in sueeding simplifition proess s G 1, G 2 G k s pperne in Figure 7. k GL G G * top G ottom middle Gottom = Gi + G, Gmiddle =, G = (8) i= 1 GL + Gottom Gtop + Gmiddle f we store oeffiients in (9) during the redution proess, the totl urrent of tree n e expressed y

4 liner omintion of urrents on pitnes nd indutnes: 1 1 = GL d, = 1, = Gtop e, d=, e= (9) G + G G + G L ottom top middle Now we hve rnh hins we hve mde during the redution proess tht hve reorded ll the informtion of rnhes from the ottom of the tree to the root. We use them to ompute the liner omintion like this: first, the equivlent urrent of eh rnh is omputed, then we dd them to their prent nodes. When we reh the end of the rnh hin, the totl urrent of the tree is otined. Equtions elow n e proved using equivlent iruits in Figure 7, p t t t t ottom = j S + node (10) j= 1 t t t middle = ottom + SL (11) t t top = middle (12) Here t ottom, t middle, t top stnd for the equivlent urrent of the ottom, middle, nd top nodes in rnh, t node is the urrent sored y ell lok t time point t,,, re defined in (7), S t L, S t re the urrents of indutne nd pitne. Detils of these formuls re shown in Figure 7. Here we store t ottom, t middle of eh rnh in order to reover the voltge of the tree node. t top will e dded into urrent of the top node lter. After reduing ll the tree nodes in the network, the size of liner eqution set is redued. By solving the new eqution set, the root node s voltge is known. Then we n ompute voltges of internl nodes in the tree from the root down to the tree ottom long the rnh hin inversely. Suppose we get the voltge vlue of the top node in rnh, then the voltge of the middle nd the ottom node n e omputed using (13) nd (14) t t t V m id d le = V to p e m id d le (1 3 ) t t t t o tto m m id d le L o tto m V = V + d ( ) (1 4 ) 3.3 edution of -L Nodes The node just onneting to ondutor nd n indutor is lled L node. All the L nodes lso n e redued to further redue the size of eqution set. Current of these rnhes n e treted s soure flowing from G node to L node diretly s shown in Figure 8. Beuse the numer of the L nodes n e up to the hlf of the totl numer of mesh nodes, even if the overll topology ontins no tree strutures, the dimension of equtions n e redued y hlf y the struture redution. When king solve the voltge of the L node, we n use formul (15): t t t t VLnode = m VGnode + n VLnode o SL (15) where m, n, o in (15) re omputed nd stored using (16) during the redution proess. 1 m = o G, n = 1 m, o = (16) G + G 3.4 edution of Trnsmission LC Chins The presene of lumped LC hins in our topology for lok network is oming from the trnsmission line model s hs een used in [10]. Eh wire of trees or meshes is divided into severl LC setions modeled s LC hin iruit. n this susetion, we show how LC hin iruit n e further redued y n equivlent iruit onsisting of only the ross nodes. This is done y repetedly trnsforming Y model iruit to π model iruit s shown in Fig. 9: V E V E V E L V E Fig.9. Y model iruit to π model iruit n Fig. 9, E nd E re the urrents inflowing into node nd node respetively, nd the orresponding rrowheds show the urrent diretions. To ompute the equivlent urrents nd resistnes shown in the right-hnd side of Fig. 9, we first look t node nd we hve: V V = ( E ) + ( E ) = ( ) V + ( E ) + + E V. We define the following equivlent resistors: + + =, (17) + + =, (18)

5 + + =. (19) As result, we hve V V V E = + Similr result n e otined for node : V V V E = We further define the following equivlent urrents: =, (20) =, (21) =. (22) Finlly we n represent E nd E in terms of those equivlent urrents nd resistnes s follows: V V V E = +, (23) V V V E =. (24) Equtions (23) nd (24) essentilly give us the π model representtion of the sme iruit s shown in the right-hnd side of Fig Topology edution nd eonstrution First, we suppress ll the tree strutures s in Setion 3.2; then we redue ll the L nodes s in Setion 3.3; then we repetedly pply the Y model toπ model trnsformtion s in Setion 3.4 strting from the node t one end of the hin until we reh the node t nother end of the hin. After the topology redution of the hyrid network, we proeed to further solve the liner equtions (3) of the redued system y preonditioned onjugte grdients methods. [7] Topology reonstrution does the inverse steps. After the voltges t the nodes of the redued system re omputed, E nd E n then e omputed vi (23) (24), the voltges t the intermedite nodes of the hin n e otined itertively y the voltge t one end of the reonstruted hin plus the voltge drop on the equivlent resistor. Then the voltges t the L nodes nd node inside tree strutures n e simply omputed vi eqution (15) nd (13) (14). 4. Simultion Time-Step Tuning After we finished the struture redution, hierrhil simultion time-step tuning sheme is used to get the dely time etween sink nodes. By ui spine interpoltion, the rmp response or the step response is plotted. Dely time n e otined y one-dimensionl root finding method suh s Brent method or Stephenson method vi the evlution of the spine fter the interpoltion. n order to etter tune the simultion step, the mximum dely of the mesured nodes, whih n e tken s the end time for simultion, must e pproximtely estimted. This n e rhived y using Elmore dely model s Elmore model gives the upper ound on the worst-se propgtion dely for interonnets [11]. As result, we split the mximum Elmore dely into severl hundreds or thousnds simultion steps depending on the ury needed. The overll lgorithm n e desried s follows: Solver ( ) { pture the mximum Elmore dely determine the simultion step from mximum dely uild node hin from the net-list file ; uild pitne nd indutne hin ; uild rnh nd L node hin ; simplify tree struture ; simplify L nodes ; simplify trnsmission LC hins uild G nxn mtrix ; while timepoint < simultetime { refresh urrent on lol trees; refresh urrent on L rnh ; refresh urrent on Trnsmission LC hins refresh S t n vetor ; solve (3) using PCG ; reonstrut volge of Trnsmission LC hins reonstrut voltge of L nodes ; reonstrut voltge of tree nodes ; if ll the voltges of sink nodes overpss the threshold print the dely time vi interpoltion refresh urrent of indutnes ; refresh urrent of pitnes ; timepoint+=timestep; } } 5. Simultion esult Our lgorithm is implemented in C lnguge. The numer of nodes in our test ses rnges from 1 thousnd to 0.2 million. Sttistis informtion is shown in Tle 1. All the experimentl results re otined on Sun Ultr Spr worksttion with MHz CPUs, 8 GB memory. Simultion steps re ontrolled for the desired ury. We nlyze the iruit till the dely times of ll the sink nodes re otined. From the results, we n lerly see tht, three types of topology redution ll ontriute to the speedup. When no lol trees re present, the speedup is not s lrge s ses with mny lol trees. However, the redution of L-nodes

6 nd LC hin still led to deent speedup. Note tht in order to mke fir omprison, the CPU times listed in Tle 1 inlude the uild-up time suh s the topology redution nd mtrix uilding. The mximum reltive error of the 50% dely mesured is within 0.4% of the given y HSPCE. Note the ury n e further improved y deresing the simultion steps. t is ler tht the proposed method is fst while lso urte for hyrid strutured lok networks. Totl Nodes Mesh Size Tle 1 Experiment results of the speed nd ury Numer HSPCE Solver Speedup of Tree time (se.) time (se.) over Brnhes HSPCE Step time Mx reltive error * ns 0.37% * ns 0.22% * ns 0.27% * ns 0.37% * ns 0.29% * ns 0.35% * NA NA 5ns NA 6. Conlusion nd Future work This pper hs proposed n effiient tehnique for nlysis of hyrid strutured lok networks modeled s generl LC networks with tree nd meshes in time-domin. At eh time step, fter integrtion pproximtion y Norton-form ompnion models, we first perform the topology/struture redution for mny LC trees, L nodes nd trnsmission LC hin iruits to redue omplexities of the originl network. Then preondition onjugte grdient (PCG) sed itertive method is used to solve the redued resistor-only networks using nodl nlysis formultion. Experimentl results hve demonstrted tht the node redution tehnique ontriutes t lest one order of mgnitude speedup over methods without node redution. The resulting new lgorithm is two orders of mgnitude fster thn HSPCE t lmost no ury loss. The topology redution is first step towrd effiient extrtion of the timing hrteristi of lok networks. We re working on topology redution vi hierrhilly prtitioning the mesh network to further inrese the speedup nd ury of the whole lgorithm. 7. Aknowledgments This work is supported y NSFC No nd eferenes [1] H. Su, S.S. Sptnekr, Hyrid strutured lok network onstrution, CCAD 2001, pp [2] P.J. estle, et l, A lok distriution network for miroproessors, EEE Journl of Solid-Stte Ciruits, Vol.36, No. 5, My 2001 pp [3] L.T. Pillge nd.a. ohrer, Asymptoti wveform evlution for timing nlysis,eee Trns. on Computer-Aided Design, vol.9, No.4, April 1990, pp [4] A. Odsioglu, M. Celik nd L.T. Pilleggi, PMA: Pssive redued-order interonnet mromodeling lgorithm,eee Trns. on Computer-Aided Design, vol.17,aug.1998, pp [5] Y.. smil,; mproved model-order redution y using sptil informtion in moments, EEE Trnstions on VLS Systems, vol.11, Ot pp [6] C.L. tzlff nd L.T. Pillge, CE: pid interonnet iruit evlution using AWE, EEE Trns. on Computer-Aided Design,vol.13,no.6,Jun.1994, pp [7] T. Chen nd C.C. Chen, Effiient lrge-sle power grid nlysis sed on preonditioned Krylov-suspe itertive method, Pro. EEE/ACM Design Automtion Conf., pp , June, 2001 [8] C-C. P. Chen, nd E. Cheng, Future SOC design hllenges nd solutions ; Pro. nterntionl Symposium on Qulity Eletroni Design, Mrh 2002, pp [9] P.J. estle, nd A. Deutsh, Design the est Clok network ; Pro EEE VLS Ciruit Symposium 1998 pp2~5 [10] D. Kur,. nd A. Vnnelli, nteronnetion modeling using distriuted LC models, Pro EEE interntionl workshop on System-on-Chip for el-time Applitions,July 2003,pp32~35 [11] M.P. Desi,. Cvijeti, J. Jensen, Sizing of lok distriution networks for high performne CPU hips, Proeedings of Design Automtion Conferene, June 03-07, 1996 pp