UTMC APPLICATION NOTE UT1553B BCRT TO INTERFACE PSEUDO-DUAL-PORT RAM ARCHITECTURE INTRODUCTION ARBITRATION DETAILS DESIGN SELECTIONS

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1 UTMC APPLICATION NOTE UT1553B BCRT TO INTERFACE INTRODUCTION The UTMC UT1553B BCRT is monolithi CMOS integrte iruit tht provies omprehensive Bus Controller n Remote Terminl funtions for MIL-STD- 1553B. The BCRT esign reues the overhe ple on the host omputer y utomtilly exeuting messge trnsfers, proviing interrupts, n generting sttus informtion. The BCRT offlos the host proessor with uilt-in memory mngement funtions esigne speifilly for MIL-STD-1553B pplitions. Thus the host nee only estlish the neessry t n/or ontrol prmeters in memory so tht the BCRT n ess the informtion s require n therefore provie the requisite us funtions. This pplition note outlines simple pseuo-ul-port RAM memory interfe for the BCRT to e use in onjuntion with miroproessor. A DMA interfe will lso e isusse. The informtion supplie in this note is entirely pplile to other memers of the UTMC BCRT fmily. This fmily inlues the BCRTM ( BCRT with Monitor funtions) n the BCRTMP ( BCRT whih opertes with wie vriety of vionis seril us protools). DESIGN SELECTIONS The proessor provies the esigner with numer of onvenient signls for seleting memory n I/O ports. In this pplition note, the BCRT s registers re in peripherl spe. 8K x 16 of stti RAM is in the s softwre progrmmle mi-rnge memory spe. 8K of memory is suffiient for most 1553 pplitions, ut ny mount of memory n e use without ffeting this esign. PSEUDO-DUAL-PORT RAM ARCHITECTURE The BCRT is equippe with signls for implementing pseuo-ul-port esign with ese. The input signls re: RD, WR, n MEMCSI. The output signls re RRD, RWR, n MEMCSO. When the BCRT is not essing memory, inite y high, the inputs re psse through to the outputs. When is low, the inputs re loke. To generte wit sttes, n ritrtion evie ontrols the s signl. The sme evie ontrols ess to the BCRT y the 80186, n to the memory y the BCRT. Figure 1 shows the input n output signls to this evie. ARBITRATION DETAILS The ritrtion lgorithm n e omplishe in smll progrmmle logi evie suh s 22V10. Figure 2 shows esription of the stte mhine neessry through the use of stte igrm n stte tle. The stte mhine is esigne to hnge sttes on the rising eges of. A request y the is efine s the ssertion of either MCS0 in the se of memory ess or PCS0 in the se of BCRT ess. Sine either ess requires use of the shre ress n t uses, they re trete ientilly. A request y the BCRT is efine s the ssertion of its signl. Upon reset, the ritrtion stte mhine (ASM) goes to stte. It remins in this stte until one of three possile onitions: 1. the BCRT requests 2. the requests 3. oth 1 & 2 In se 1, the ASM goes to stte. Here, is sserte. Upon reeiving, the BCRT sserts. The ASM remins in stte until one of three events our: 1.1. the BCRT esserts 1.2. the requests 1.3. oth 1 & 2 1

2 CLK Proessor PCS0 MCS0 Aritrtion PLD BCRT Series Figure 1. Aritrtion PLD Inputs n Outputs * CS CS 000 * CS CS 100 * CS * CS * CS 010 * CS * CS * CS 011 e 001 Notes: 1. CS = MCS0 + PCS0. 2. All signls in this igrm hve een onverte to positive logi; thus inites the sserte (low) stte n inites the esserte (high) stte of the tul signl. 3. must e syhronize to. Figure 2. Aritrtion PLD Desription 2

3 CURRENT S 0 S 1 S 2 INPUTS CS NEXT S 0 S 1 S 2 OUTPUTS e 0 X 1 X 0 X X 1 X 1 X 1 X 0 X 0 X 0 X 0 X X X X X X 1 1 X X X e In se 1.1, the BCRT returns to ile stte. In se 1.2, the ASM vnes to stte, where is esserte using the to wit until the BCRT is finishe. The ASM stys in stte until is esserte, t whih time it vnes to stte e. In this stte, the ress uffers swith k to ontrol. The t the proessor is trying to re or write is psse. The ASM then returns to stte, where the is sserte n the ompletes its yle. In se 1.3, the requests ess in the sme yle tht the BCRT hs omplete. In this se, stte is entere n the proessor performs yle s if the ASM h strte from n ile stte. In se 2 from ove, the requests from n ASM ile stte. In this se, the ASM goes to stte. Stte prevents the BCRT from reeiving. On the next yle, the yle is omplete n the ASM returns to ile stte. For slower memories, wit sttes my e e (with esserte) etween n. However, re must e tken not to exee the mximum to times given in the BCRT t sheet. In se 3 from ove, the BCRT n request t the sme time. In this se, the BCRT wins n the must wit (entering stte ). Figures 4 n 5 show timing igrms for eh of the possile ritrtion senrios. These igrms show the trnsitions on yle-y-yle sis of. For ext timing elys for the or BCRT, onsult the pproprite t sheet. MEMORY CONTROL/ACCESS LOGIC Figure 3 shows the onnetion of the remining ontrol signls require in this interfe. Note the use of us trnseivers n lthes to emultiplex the ress/ t us. Also note the use of the RD, WR, MEMCSI, RRD, RWR, n MEMCSO signls. If itionl memory evies or other peripherls re to e ple in the system, they shoul hve seprte us trnseivers n lthes. DMA CONFIGURATION If itionl memory evies n other peripherls re put on the shre ress/t us shown in the igrm, the pseuo-ul-port esign is essentilly onverte to DMA onfigurtion. The ritrtion lgorithm must now e use for ll esses. In this onfigurtion, the BCRT lks lol t us, eliminting severl us uffers n lthes. The isvntge to this pproh is tht the BCRT t trnsfers now ompete with non-1553-relte tivity on the host us. In systems with low us throughput, this lterntive my e n eptle. SUMMARY This note hs shown simple pseuo-ul-port RAM implementtion for BCRT to interfe. A seprte pplition note is ville isussing true ul-port onfigurtion. For further informtion on UTMC prouts n literture, plese ontt UTMC pplitions support. 3

4 RD RD Proessor WR PCS0 MCS0 WR CS MEMCSI BCRT/ BCRTM/ BCRTMP AD(15-0) ALE Threestte ADDR lth OE ADDRESS BUS TSCTL ADDR(15-0) DEN Bus XCVR DATA BUS DATA(15-0) DT / R DIR OE RRD RWR MEMCSO BCRT is in peripherl spe. Memory is in mirnge memory spe 0. ADDR DATA 8K x 16 RAM Figure 3. System-Level Control Signls 4

5 80186 Aess with no Aritrtion Write T 1 T 2 T 3 T 4 Re T 1 T 2 T 3 T 4 AD 16-1 ADDR DATA DEN WR RD DT/R Note: If the BCRTM sserts while the stte mhine is in stte, it will hve to wit until the stte mhine returns to stte efore its request will e proesse. (Proessing then ontinues s shown elow.) BCRTM Aess with no Aritrtion Write T 1 T 2 T 3 T 4 Re T 1 T 2 T 3 T 4 Figure 4. Aritrtion Timing Digrm 5

6 80186/BCRTM Request t Sme Time T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 e Requests While BCRTM is using the Bus (BCRTM is on Lst Cyle) Figure 5. Aritrtion Timing Digrm 6

7 80186 Requests While BCRT is using the Bus (BCRTM is not on Lst Cyle) T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 e Figure 5. Aritrtion Timing Digrm (ont.) 7