Incremental Design Debugging in a Logic Synthesis Environment

Transcription

1 Inrementl Design Deugging in Logi Synthesis Environment Andres Veneris Jing Brndon Liu University of Toronto Freesle Semiondutors Dept ECE nd CS High Performne Tools Group Toronto, ON M5S 3G4 Austin, TX Astrt In tody s omplex nd hllenging VLSI design proess, multiple logi errors my our due to the humn ftor nd ugs in CAD tools. The designer often fes the hllenge of orreting n erroneous design implementtion. This study desries simultion-sed logi deugging solution for omintionl iruits orrupted with multiple design errors. Unlike other simultion-sed tehniques tht identify ll errors t one, the proposed method works inrementlly. At eh itertion of inrementl deugging, single ndidte lotion is retified with liner time lgorithms. This is done so tht the funtionlity of the erroneous design grdully mthes the orret one. A numer of theorems, heuristis nd dt strutures help identify single ndidte solution t eh itertion nd they lso guide the serh in the lrge solution spe. Experiments on enhmrk iruits onfirm the effetiveness of inrementl logi deugging. Introdution The digitl VLSI design yle ommonly strts with ehviorl desription oded in some Hrdwre Desription Lnguge (HDL). This desription is next trnslted to Register-Trnsfer Level (RTL) representtion nd synthesized to gte-level (logi) implementtion. Design vlidtion nd optimiztion steps gurntee the orretness nd performne of the finl produt. Although utomted Computer-Aided Design (CAD) tools for synthesis nd optimiztion re ommonly used, iruit designers often need to mnully modify the netlists generted y these tools to hieve speifi optimiztion onstrints nd/or to mke smll speifition hnges. As the iruits grow in size nd omplexity, this mnul resynthesis proess eomes inresingly prone to error [, 8]. Additionlly, softwre ugs in CAD tools my introdue errors tht lter the funtionlity of the synthesized design [, 8]. These errors, known s design errors, re funtionl mismthes etween logi netlist nd its funtionl speifition. Experimentl dt hs reveled tht the nture of these errors usully involves the funtionl misehvior of some gte elements nd/or wire interonnetion errors [, 8]. The sme experiments show tht the numer of errors is usully smll (less thn or equl to 4 errors). Given orret implementtion of speifition nd n erroneous logi netlist, Design Error Dignosis nd Corretion (DEDC) is the utomted proess tht identifies erroneous lines nd proposes orretions on these lines to retify the netlist [5, 7, 0,, 2, 5, 6, 7, 8]. DEDC methods re rodly lssified s either simultion- or BDDsed [6]. Corretions proposed y DEDC method re usully seleted from predetermined set of different types of permissile logi trnsformtions, lso known s design error model. A design error model should e simple to preserve the engineering effort invested on the design. It is notle tht DEDC is n inherently diffiult prolem. Beuse the implementtion of the speifition (in the form of HDL, RTL, et) is n ritrry one, it hs to e treted s lk ox ontrol-

2 lle t primry inputs nd oservle t primry outputs. Consequently for the erroneous netlist, the solution (serh) spe for dignosis grows exponentilly with iruit lines nd inresing numer of errors [8]: (# errors) dignosis spe = (# iruit lines) The orretion spe is further ompounded y the lrge numer of potentil orretions pplile to eh line, whih is usully determined y the rdinlity of the design error model tht is used. Thus, the development of effiient DEDC tools to retify designs with multiple errors is hllenging tsk. The exponentil growth of the solution spe in terms of the numer of errors lso vils DEDC more options to orret design [8]. This is euse n error my e orreted y the tul or nother funtionlly equivlent trnsformtion [7]. Equivlent orretions exist euse there my e mny wys to synthesize funtion nd orret the design. We ll n tul or n equivlent orretion vlid orretion. Sine design errors nd orretions re symmetri terms in this ontext, we do not mke distintion etween them in our presenttion. In this pper, we desrie simultion-sed inrementl DEDC (deugging) pproh for omintionl iruits. Given n erroneous design, n implementtion of its speifition nd set of rndom input test vetors V, the method itertes to identify nd orret one error t time nd ring the design funtionlly loser to its speifition. Inrementl deugging termintes when the design is fully retified in terms of the test vetor set used. Test vetor genertion for these errors nd design verifition following simultion-sed DEDC method re not topis of this work [2, 4, 6]. The min differene etween this pproh nd other inrementl DEDC pprohes [, 5, 6] lies in the methods used to identify eh single error lotion nd its orretion(s). In detil, we prove theorem tht sserts lower ound on the numer of filed vetors eh vlid orretion must prtilly retify. This result llows us to exlude orretions tht might not led to solution nd urtils the exponentil explosion for the prolem in prtie. Another dvntge of the proposed inrementl DEDC proess lies its simpliity nd effiieny. All steps t eh itertion re dpted from single error DEDC lgorithms. Single error DEDC is well exmined prolem with liner time solutions [5, 7, 0,, 2, 5, 6, 7, 8]. We lso show tht during the exeution of n inrementl DEDC lgorithm, it my e neessry to onsider orretions tht do not look ttrtive ut my hve the potentil to led to solution in lter stges. Finlly, novel deision mking proess on serh tree is presented to explore the solution spe effiiently. Experiments on omintionl ISCAS 85 nd fullsn sequentil ISCAS 89 enhmrk iruits onfirm tht the pproh returns urte orretions nd it sles well with inresing numer of errors. In ft, in ll experiments it returns with set of orretions tht retify the design for ll test vetors used. Intuitively, its suess is ttriuted to the ft tht the solution spe usully ontins mny equivlent orretions. Theoretilly, sine it utilizes set of heuristis, the method my not return solution nd/or it my not find the omplete set of ll tul nd equivlent solutions. The pper is orgnized in the following. In the next setion, we give relevnt definitions nd desrie the error model. Inrementl DEDC pproh is presented in Setion 3. Experiments re found in Setion 4 nd Setion 5 ontins the onlusions. 2 Preliminries We investigte erroneous struturl netlists implemented with logi NOT, BUFFER, AND, NAND, OR nd NOR primitive gtes. The lgorithm n ommodte XOR nd XNOR gtes ut we do not onsider them expliitly. Further, we ssume tht oth the orret implementtion of the speifition nd the design re ompletely simultle. This ssumption n e relxed s disussed in [2, 20]. Throughout the disussion, line l, fn-in to n AND or NAND (OR or NOR) gte hs ontrolling vlue for input vetor v if the vlue of l is 0 (). If l drives NOT or BUFFER it lwys hs ontrolling vlue. A line whose vlue hnges during simultion under the presene of some fult(s) is lled sensitized line nd pth of sensitized lines is lled sensitized pth. This work onsiders logi error types similr to those from the model of [2], shown in Fig.. This model ontins olletion of simple logi gte or wire interonnetion errors, suh s gte replement, missing input wire, extr input wire, et, tht my our in logi synthesis [, 8]. Most DEDC tehniques [5, 7, 0,, 2, 5, 6, 7, 8, 9] use the er-

3 Error Extr Inverter Missing Inverter Gte Replement Missing Input Wire Extr Input Wire Inorret Input Wire Missing Input Gte Missing Output Gte Missing Gte Ciruit d INCORRECT BUFFER g f d d CORRECT d BUFFER Figure : Common design error types ror model y Adir et l. [2] due to its prtility nd its simpliity. Complex resynthesis lgorithms during orretion my lter the design glolly nd jeoprdize the engineering effort lredy invested in it. A simple design error model is desirle ut it my not e dequte when DEDC method is used s pltform to perform engineering hnges. In the prolem of engineering hnge one is required to modify netlist to meet new speifition. Its reltion to DEDC is disussed in detil in [4, 8]. Although the proposed DEDC method my e le to tkle some simple instnes of the engineering hnge prolem, solution to the generl prolem is not the topi of this work. Prior to the exeution of the lgorithm, we simulte set V of rndom input test vetors nd vetors g f for stuk-t vetors [9]. These types of vetors hve een shown to detet more thn 92% of design errors [2, 4, 8]. We use these vetors to rete two indexed it-lists, Verr l nd Vl orr, on every line l in the iruit. The i-th entry of the Verr l (Vorr) l list ontins the logi vlue of l when the i-th filing (non-filing) input test vetor from V is simulted. These it-lists re properly updted nd utilized during dignosis nd orretion. Most methods use simultion euse it hs een shown [2, 8, 8] tht simultion with smll (00 to 3000) numer of input vetors provides relile guide to DEDC. On verge, 92% of orretions qulified this wy re vlid ones nd pss forml verifition. In dignosis we use pth-tre, line mrking routine developed for fult dignosis in [2] nd similr to ritil-pth tring [3]. For n erroneous vetor v, pth tre strts from n erroneous primry output for v nd tres kwrds towrd the primry inputs of the iruit, while mrking lines of interest. Detils nd exmples of this liner time lgorithm re found in [2]. Pth-tre is importnt for multiple fult dignosis euse it lwys mrks one line from every set of vlid orretions [8]. 3 Inrementl Deugging The input to inrementl deugging is n erroneous design, high-level implementtion of the speifition, the mximum numer of possile design errors N nd set of input test vetors V. The output of the lgorithm is set of iruit lines ssoited with the orretions tht retify the design for the vetor set V. For n erroneous iruit, we n estimte N empirilly if we simulte vetors nd reord the perentge of filing primry output responses [8]. Usully the lgorithm strts with smll vlue for N nd inreses this user-speified prmeter if it fils to return with orretion(s). The lgorithm works in n itertive mnner shown in Fig. 2. It ses its opertionl flow on deision tree. Eh itertion is represented y different level in the tree where different options (deisions) re ville. At eh itertion, it identifies set of suspet lines (dignosis) nd devises set of orretions for these lines ording to the prmeters desried in susetions 3. nd 3.2. In most ses, eh orretion redues the numer of erroneous primry outputs for ll vetors in V.

4 However, the lgorithm does not disrd intermedite orretions tht my not look ttrtive. As reported in [6], the numer of erroneous primry output responses does not inrese monotonilly with the numer of injeted errors. Susetion 3.2 presents heuristis tht prevent deleting suh orretions. The deision flow of the inrementl lgorithm (tht is, the sequene of deisions mde t different levels of the tree) is ruil for its suess. At eh itertion, there my e lrge mount of orretions tht n model the error effets nd their intertion. Totl run-time nd finl resolution re gretly ffeted y erly deisions. If greedy Depth-First- Serh (DFS) pproh is used, wrong deision t the top level of the tree my led us to explore portion of the serh spe with no solution. A nive Bredth-First-Serh (BFS) pproh my result in exessive omputtion. Consequently we use n pproh whih is trde-off etween DFS nd BFS, desried in susetion 3.3. Pth-Tre 3. Dignosis Dignosis quikly redues the error spe nd elimintes lines with no potentil to led to solution. This proess is done in two steps. In the first step, pth-tre mrks suspet lines in the iruit. Pthtre lwys mrks t lest one lotion from every set of lotions where vlid orretions exist. We llow lines with high pth-tre ounts to qulify for the susequent dignosis, usully the top 5-20% of these lines. In the seond step, for eh line l, we invert the logi vlues in its V l err it-list nd propgte this differene throughout the fn-out one of l, proess known s error simultion [8]. Rell tht V l err ontins the logi vlues of line l for the suset of vetors tht tivte the errors. One done, we ount the numer of erroneous primry outputs tht re now retified nd rnk ll the lines ording to these ounts (heuristi ). In sense, the suspet lines re rnked y how muh orreting potentil they hve. During orretion, we visit these lines in deresing order of the ounts. Experiments indite tht lines with high ounts often led to vlid orretions. Suspet Line Rnking Corretion nd Rnking Dignosis Corretion A B C D E 0/0 G3 0/0 G G2 0/ 0/ Figure 3: Line rnking during dignosis X /0 Y NO Selet the the Top-Rnked Corretion Retified? YES Correted Design 94% vlid orretion(s) Figure 2: Algorithm desription. Exmple : Fig. 3 shows n erroneous implementtion for ISCAS 85 enhmrk C7 iruit. Gte G hs n extr input wire nd G2 is NAND gte repled y n OR. Test vetor v = (,,, 0, ) is simulted nd pirs of fult-free/fulty vlues re shown next to eh lines. Pth-tre mrks the lines with n sterisk. Rell, error simultion inverts the logi vlue t line nd simultes t its fn-out one for mny vetors in prllel. Tle 3. summrizes results of the rnking proess performing error simultion with the vetor v nd two more vetors. Letter C ( E ) in this tle indites tht error simultion vlue grees (does not gree) with the logi simultion one. We oserve, line G mthes more orret vlues for three vetors. For this re-

5 son, it rnks higher thn G3 for these vetors in this stge of the lgorithm. test vetor err. design inv G3 inv G (A,..., E) X Y X Y X Y 0 C E C E C C 0 0 C E C C C E 0 0 C E C E C C Tle : Error Simultion on Suspet Lines 3.2 Corretion In orretion, n instne of design error model is ssigned to eh suspet line tht qulified dignosis. This is done exhustively for eh orretion s in [8]. As disussed, the ility to se deisions on vlid orretions t eh itertion influenes the overll performne drmtilly. The serh for vlid orretions is not n esy tsk if we onsider the vst mount of possiilities tht n model vrious error effets nd different sensitized pths or o-sensitized pths (i.e. sensitized to more thn one error) t eh itertion of inrementl dignosis. In this setion we present numer of tehniques nd heuristis to prune the lrge solution spe nd guide the serh. The following theorem gives neessry ondition ll vlid orretions must stisfy. We use this theorem to sreen orretions tht nnot led to ny optiml solution. As indited in the experiments, tht this simple theorem provides relile guide to orretion. Theorem : Let L = {l, l 2,..., l N } e the set of lines where set of vlid orretions exists. Let V err e set of input test vetors with filing primry output responses nd let Verr li e the set of vetors from V err tht produe n erroneous logi vlue on l i (i.e., exite the error) nd propgte this differene to some primry output(s). Then there exists set Verr, li i N, whose size is t lest Verr N. Proof: The theorem is diret pplition of the pigeonhole priniple of ounting. By definition, eh vetor in V err exites t lest one error to rete sensitized pth(s) to some primry output(s). In other words, eh vetor in V err is ttriuted to t lest one Verr li for some l i, i N. Using the pigeonhole priniple nd the ove oservtions, it eomes evident tht there exists t lest one set Verr li with t lest Verr N test vetors from V err. The orretion lgorithm proeeds s follows. Given suspet lotion l, it exhustively ompiles list of orretions from the design error model. From these orretions, it keeps the ones tht stisfy the following sreening tests: Sreening test on Verr l vetors: Any qulifying orretion must omplement t lest Vl err N its in Verr l when the orretion is present on line l (heuristi 2). This sreening test is diret pplition of Theorem s it implies tht for every set of lines L where vlid orretion(s) exist, there is t lest one lotion l L responsile for some erroneous primry output(s) in t lest Vl err filing primry output test vetors. Sine these erroneous primry outputs re sensitized to respetive Verr l it-list entries, vlid orretion should omplement the itlist entries. Evidently, the nture of this sreening test my qulify orretions on lines tht do not elong in ny suh set L. It my lso disrd orretions on lines from set L just euse the numer of filing output vetors ttriuted to them is not lrge enough to qulify the requirement of the theorem. The former set of (flse) orretions will simply degrde the performne of the lgorithm. On the other hnd, sine it lwys qulifies one element from L, vlid orretions disrded t the present itertion will e disovered t lter itertions of the lgorithm. This is euse the lgorithm exmines inrementlly the omplete error spe, s disussed lter in susetion 3.3. The test required y heuristi 2 n e performed effiiently with single lol simultion step on the driver gte of l. The newly otined logi vlues re ompred to Verr. l This set Verr l is lso updted ppropritely one line l qulifies to ommodte future itertions of the lgorithm. Experiments indite tht this inexpensive simultion step disqulifies mny inpproprite orretions improving the orretion seletion proess drmtilly. Our implementtion follows n ggressive pproh nd initilly neessittes tht orretion omplements high numer of it entries. This limit is empirilly set to vlue of 70% nd redued progressively when the lgorithm returns with no orretions. This is euse some errors re esy to exite suh s errors with inversion. A vetor with erroneous primry output response from in V my lso N

6 exite more thn one error nd ttriute to multiple V l err sets in Theorem. Sreening Test on Vorr: l Any qulifying orretion n sensitize smll numer of new pths to previously orret primry outputs (heuristi 3). The numer of erroneous primry outputs does not neessrily inrese with the numer of injeted errors. This heuristi ounts for orretions tht my inrese the numer of erroneous outputs nd performs sreening with simultion of the Vorr l it-list t the fn-out one of l. We elorte on its rtionle with the following exmple. Exmple 2: Fig. 4 depits the sitution where the effets of two design errors on lines l nd l 2 hve two sensitized pths tht merge in gte G with logi vlues 0 nd respetively. Also ssume tht this vetor v produes orret primry output responses. It n e seen tht in the orret implementtion, l produes logi in the first input of G nd l 2 produes logi 0 in the seond input of tht gte. Therefore, when vlid orretion is pplied to l, under the presene of the seond error, the logi vlue t the fn-out of G swithes to. If primry output is sensitized to the fn-out of G, it now eomes erroneous. It remins so until vlid orretion is pplied to l 2 nd the fn-out of G swithes k to its orret logi vlue. err l l orr 0 l err 2 G Figure 4: Exmple of Sreening on V l orr This exmple suggests we my need to qulify orretions tht sensitize numer of new erroneous primry outputs. Experiments permit orretion to rete no more thn 3-8% new erroneous outputs on the verge. Empirilly, this numer hs shown to e suffiiently lrge to llow vlid orretions to qulify in most ses. An exeption is the se for NAND-implemented XOR iruits (e.g. C499, C432, et) [5]. Consider XOR gte implemented with four NAND gtes, s in Fig. 5, for exmple. Assume errors tht reples gtes G nd G2 with AND. If we orret ny single error, it gives lrger numer (> 20%) of new erroneous primry outputs. In experiments for suh iruits, the 0 lgorithm relxes this onstrint rpidly s lower vlues fil to qulify ny orretions. G Figure 5: A NAND-sed XOR 3.3 Deision Flow G2 Inrementl deugging uses n underlying dt struture sed on deision tree. At every node of this tree, the lgorithm omputes set of orretions. It then rnks these orretions ording to some riteri desried lter in this susetion. Next, it selets some of them to uild its hildren nodes nd it lso updtes the Verr l /Vl orr it-lists of eh line ppropritely. The deision mking proess hs n importnt impt on the performne nd resolution of the lgorithm. To void pitflls of stnd-lone BFS or DFS, it mkes deisions using BFS/DFS trde-off. We explin the deision mking with the deision tree shown in Fig. 6. Every node in this tree represents set of potentil orretions orretion is single error model pplied to one suspet line returned y single itertion of the lgorithm; n edge represents the pplition of single (highlyrnked) orretion to enter the next tree level; the level of node indites the numer of orretions performed on the implementtion so fr. In other words, pth in the tree from the root to lef represents set of orretions tht potentilly retify the design. To mke deision, we visit these nodes in rounds. At eh round, single (highly-rnked) orretion is seleted from every node urrently present. The orretion is pplied to otin new node in the next level of the tree. This tree trversl gurntees to reh solution in finite time [3]. The round in whih node is reted is shown next to the node in Fig. 6. Oserve tht the numer of nodes in the tree t most doules with eh round s the tree grows oth in depth nd redth. However,

7 ievel level 2 level 3 level round 3 round 4 Figure 6: Deision Flow: A BFS/DFS trde-off experiments indite tht the numer of tree nodes visited efore rehing solution remins smll in ll ses. Finlly, we elorte on the prmeters of the three heuristis introdued with the lgorithm. On eh suspet line, let h e the perentge of erroneous primry outputs retified in heuristi ; h 2 the perentge of it-entries tht re omplemented in heuristi 2; nd h 3 the perentge of orret primry outputs required y heuristi 3. Runs of the lgorithm strt with h /h 2 /h 3 = / nd they re redued progressively if it returns with no orretions. Oserve, inrementl deugging with prmeters h /h 2 /h 3 = / equls to the single error se in trditionl DEDC. When mny errors re present, h redues efore h 2 nd h 3, sine h 2 nd h 3 re error type dependent. An ggressive relxtion of the prmeters n led to numerous orretion ndidtes. A omintion whih is typil for three suspeted errors when higher vlues do not work is h /h 2 /h 3 = 0.3/0.7/0.95. If this lso fils, prmeters re relxed s h /h 2 /h 3 = 0.3/0.5/0.85 et. We lso set 0./0.3/0.5 s lower limit where orretion pth is delred to terminte with filure nd it is no longer ttempted. For NAND-sed XOR gtes, stringent vlues of h /h 2 /h 3 fil to return orretions until h /h 2 /h 3 = 0.4/0.5/0.5 is rehed. The orretions returned t level i re rnked ording to the formul: ( V rtio )h 3 + V rtio h nd they re visited in the deresing order of rnks during exeution. In this formul, V rtio indites the perentge of vetors with erroneous output responses in V prior to the orretion. The experiments show tht this formul provides good guidne. In ll of the ses vlid orretions rnk in the top 5-0% in their node nd solution is found efore muh of the deision tree is explored. 4 Experiments We implemented the lgorithm of Setion 3 using C lnguge nd rn it on SUN Ultr 5 worksttion with 28 MB of memory for ISCAS 85 nd fullsn versions of the ISCAS 89 enhmrk iruits orrupted y up to 4 design errors. The lotions of the design errors re seleted t rndom. Error types re lso seleted t rndom from Fig.. We perform twenty experiments per iruit nd per error se. Ten of these experiments involve gte relted errors nd the remining ten re wire relted errors. This setion presents nd disusses results of the ove experiments. All run-times re in CPU seonds nd do not inlude the initil rndom simultion step for V whih is performed only one with prllel vetor simultion. Run-times inlude the time to updte the it-lists t eh step of the inrementl pproh. Tle 2 shows verge vlues for the performne of the lgorithm for 2, 3 nd 4 design errors. Detiled results for single errors re found in [8]. To emulte relisti dignosti environment, we use the originl versions of ll enhmrks with redundnies (tht is, iruit 908 hs 908 lines, 535 hs 535 lines et). Redundnies inrese the solution spe nd the omplexity of the prolem. The first olumn of Tle 2 ontins the iruit nme. Columns 2, 6 nd 0 of the tle ontin the verge run-time for dignosis in single lgorithm exeution when 2, 3 nd 4 errors re present, respetively. As explined in susetion 3., dignosis tries to eliminte lines tht nnot serve s potentil error lotions for vlid orretion. The CPU times reported in these olumns show tht heuristi suessfully eliminte 70-90% of the lines in roughly seond. The experimentl results on orretion, disussed next, indite tht error modeling nd rnking ording to heuristis, 2 nd 3 fvors vlid orretions. The verge time spent to ompile nd rnk the orretions in single lgorithm exeution is listed in olumns 3, 7 nd. The numer of orretions in single lgorithm itertion vries from (the originl) to few thousnd nd it does not seem to give pttern. Columns 4, 8 nd 2 ontin the totl numer

8 Tle 2: Results for multiple errors kt 2 errors 3 errors 4 errors nme dig. orr. nodes time dig. orr. nodes time dig. orr. nodes time C C C C C C C C C S S S S S of lgorithm exeutions (proedure invotions) for eh error se. This orresponds to the numer of nodes in the finl deision tree of Fig. 6. Consider this tree, the leftmost pth in ny sutree onsists of deisions for orretions with the highest rnks in eh node. For exmple, the first possile triple solution is found in tree with 4 nodes. The seond solution n e found in tree with 6 nodes, whih ompleted hlf the wy through the 4th round. In most ses, the lgorithm ompletes in under 6 rounds with mximum of 32 nodes fter exploring the first severl leftmost pths of the deision tree. Some iruits suh s 355 nd 880 often require 9 rounds nd explore mximum of 256 nodes. For these iruits, DFS would explore muh of the tree efore it returns with solution. Figure 7 plots the verge numer of nodes in the tree dt struture to dignose some omintionl nd sequentil iruits with, 2, nd 4 errors. It is seen, the numer sles well nd it roughly doules s the numer of errors doules. This mens tht the method is spe effiient. The totl run-time to return vlid set of orretions is found in olumns 5, 9, nd 3. These runtimes demonstrte the roustness of this pproh tht retifies enhmrks suh s the 6-it multiplier C6288, hrd to dignose nd orret iruit, in few minutes of CPU time. Sine the proposed lgorithm uses set of heuristis to serh effiiently in the serh spe for orretions, in theory, it nnot gurntee tht it will return with set of orretions. Nevertheless, in ll experiments of Tle 2 it lwys returned with set of modifitions tht retify the design for the set of test vetors utilized. This onfirms the effetiveness of the theorems nd heuristis presented in Setion 3. To demonstrte the effetiveness of the orretion pruning heuristi 2, Figure 8 plots the verge numer (for 0 runs) of orretion ndidtes returned y the orretion lgorithm in eh itertion (white rs) versus the ones stisfying heuristi for two iruits. For eh iruit, dt for orreting 2 errors (left pir) nd 4 errors (right pir) re given. It is seen, the heuristi redues the orretion ndidtes one order of mgnitude (for over 000 orretions, to less thn 00). This, in effet, redues oth the runtime nd memory usge signifintly. Figure 9 shows the verge run-time performne for ll omintionl nd ll sequentil iruits used in the experiments s the numer of errors inreses. Performne shows to sle well nd the lgorithm remins time effiient. It is lso seen, inrementl deugging for full-sn sequentil iruits outperforms this for omintionl iruits. This is euse in full-sn mode, memory elements ehve s pseudo outputs/inputs to redue the struturl level of the iruit. Pth-tre is very effetive in these ses nd dignosis enefits from this ft.

9 Avg. Num. Nodes Avg. Num. Nodes error 2 errors 4 errors C499 C6288 C7552 () Comintionl iruits. S953 S494 S9234 () Sequentil iruits. Figure 7: Serh tree size Avg. Num. Corretions Time (CPU se.) C6288 S9234 Figure 8: Effetiveness of Heuristi Comintionl Sequentil Num. Errors Figure 9: Run-time ehvior iments, in Pro. of EURO ASIC, pp , Conlusion Design errors my our in logi synthesis environment. The designer often needs to deug design yet preserve the engineering effort. We propose simultion-sed inrementl deugging method for multiple design errors. The method retifies n erroneous design through sequene of interleving dignosis nd orretion steps. Eh suh step is fst nd rings the funtionlity of the design loser to its speifition. Experiments on enhmrk iruits orrupted y mny errors demonstrte the effiieny nd prtility of the pproh. Referenes [] E. J. As, K. Klingsheim nd T. Steen, Quntifying design qulity: model nd design exper- [2] M. S. Adir, J. Ferguson nd T. E. Kirklnd, Logi verifition vi test genertion, in IEEE Trns. on CAD, vol. 7, pp , Jnury 988. [3] M. Armovii, P. R. Menon nd D. T. Miller, Critil pth tring: n lterntive to fult simultion, in IEEE Design nd Test of Computers, vol., pp , Ferury 984. [4] H. A. Asd, nd J. Hyes, Logi Design Vlidtion vi Simultion nd Automti Test Pttern Genertion, in Journl of Eletroni Testing: Theory nd Applitions, Kluwer Ademi Pulishers, vol. 6, pp , [5] V. Boppn nd M. Fujit, Modeling the unknown!towrds model-independent fult nd error dignosis, in Pro. of Int l Test Conferene, pp , 998.

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