An Efficient 8b/10b Encoder and Decoder Design using Reversible Logic Gates

Transcription

1 Interntionl Journl of Eletril Eletronis & Computer Siene Engineering Volume 4, Issue 6 (Deemer, 207) E-ISSN : P-ISSN : Aville Online t An Effiient 8/0 Enoder nd Deoder Design using Reversile Logi Gtes Nyn D. K., Sujth B. K. Reserh Sholr, Jin University, Bnglore, Indi 2 Professor, Dept. of Teleommunition Engg. MSRIT, Bnglore, Indi nynjournl@gmil.om Astrt: The reversile logi sed omputtion (RLC) plys n importnt role in modern dys very lrge sle integrted (VLSI) iruit design. The RLC gives offers omputtion thn trditionl omputtion whih preserves dt while mnipulting it. Also, offers etter design mehnism whih performs etter ginst the thermodynmi onsequenes nd plys vitl role in emerging tehnologies. The reversiility is lso found in the modern omputers whih redues the power onsumption. Mny of the reserhers hve presented the RLC y onsidering the logil nd rithmeti units ontining multipliers, shifters, dders nd registers. Also, from vrious study nlysis found tht there re less fous on the reversile logi sed enoder nd deoder design. In this pper, we hve presented two reversile designs. Fredkin nd Peres sed enoder/deoder nd 2. Fredkin nd proposed SN gte sed enoder nd deoder. Lter, oth the designs were ompred to nlyze the etter mong them. The performne is mesured y onsidering the numer of reversile gtes used nd re in oth the designs. Keywords: Are, Deoder, Enoder,Fredkin Gtes,Peres gte, Propsed SN gte, Reversile Logi, Quntum Cost. 26 I. INTRODUCTION The omputtion y reversiility onept indites the informtion/dt is never lost during its omputtion. By using the reversiility sed omputtion the originl informtion n e reovered t ny point of omputtion nd un-omputing the reversile results nd is onsidered s reversile logi (RL) []. The physil form of reversiility n dissipte the thermodynmis in terms of energy loss. During the idel operting ondition, the energy dissiption of the RL iruit is zero. The low of physis indites tht the loss of informtion dissiptes the energy of "KTln2", where K represents the Boltzmnn s onstnt while T indites the system temperture. The RLC n lso rings the energy effiieny, whih ffets the iruits speed. Also, for devie portility the RLC is must [2]. The reversile gtes (RG)/iruits exhiit one-toone mpping property mong the input nd output vetors. By whih the input vetors sttes n e reonstruted/otined through output vetor sttes. In RG, oth the input nd output logi its will e equl. Also, eh signls fn out must e equl to in RG [3]. The RG helps in designing highly omplex system onsisting of vrious RL iruits s primitive omponent. Also, these RG n perform the exeution of omplited opertions y mking use of quntum omputers. The RL gtes lwys hve equl inputs nd outputs nd vie vers. Reently, vrious reversile gtes re proposed nd whih follow the reversiility onept very well. Some of the RL gtes inlude Fredkin gte (FG), Peres gte (), Toffoli gte (TG) nd Feynmn gte (FyG) et. The FG inludes quntum ost of 5 for 3x3 RL gte. The FyG hs quntum ost of for 2x2 RL gte [4]. In the work of Kur nd Bhndri [5] presented 4/2, 8/3 nd 6/4 enoder. In whih, for 4/2 enoding one FG nd three FyG re used nd whih gives two grge outputs. For 8/3 enoding two FG nd nine FyG re used nd whih gives five grge outputs. For 6/4 enoding five FG nd three FyG re used nd whih gives twelve grge outputs. All these models utilized in low power systems. Nhtigl nd Rngnthn [6] hve given 4/2 enoder nd deoder system design nd nlysis. This system yields signifint results over other reversile enoder/deoder onsidering grge output, quntum ost et. The uthor hs got etter improvement in the grge output elimintion. From the existing reserh nlysis, it is found tht the work on the reversiility sed enoder nd deoder re very less. Also, the works on the 8/0 enoding/deoding sed on RG re not up to the mrk. In this pper, two different RG sed 8/0 enoding/ deoding systems re presented. One system is designed with FG nd while the other system is repled with the proposed SN gte in ple of. Both the systems were ompred with eh other to find the signifint system mong them. The prmeters onsidered for the performne evolution re re nd totl numer of gtes used in oth the systems. In this reserh pper, we hve introdued two different 8/0 enoder/deoder systems nd performed omprtive performne nlysis. This pper is tegorized in following mnner. The setion II desries the introdutory fetures of the reversile gtes nd si RL gtes. In setion III relted works re highlighted while in setion IV prolem formultion is desried. The setion V gives the reserh method followed nd setion VI gives the iruit implementtion. The setion VII

2 Interntionl Journl of Eletril Eletronis & Computer Siene Engineering Volume 4, Issue 6 (Deemer, 207) E-ISSN : P-ISSN : Aville Online t disusses the omprtive results nlysis nd in setion VIII onlusion is given. II. REVERSIBLE GATES There re vrious reversile gtes (RG) re exist nd re riefed s elow. A. NOT Gte (NG): This is si RG hving input '' nd gives the output of 'Op=NOT()'.This NG gte hs the QC of 0. Op= TG Op2= Op3= Fig. 4. Toffoli Gte Tle. 2. Truth Tle of TG NG Op= Fig.. NOT Gte B. Feynmn Gte (FyG): This gte is in 2x2 RG form ontins two inputs '' nd ''nd gives the two output of Op= nd 'Op2= ' nd it hs QC of. E. Peres Gte (): This gte is in 3x3 RG form ontins two inputs '', '' nd ''nd gives the three output of 'Op', 'Op2' nd 'Op3' nd it hs QC of 4. Op= FyG Op2= Fig. 2. Fyenmn Gte Tle.. Truth Tle of FyG Op= Op2= Op3= Fig.. 5. Peres Gte Tle. 3. Truth Tle of C. Fredkin Gte (FG): This gte is in 3x3 RG form ontins three inputs, nd nd output of Op, Op2 nd Op3 nd it hs QC of 5. FG Fig. 3. Fredkin Gte Op= Op2= + Op3=+ D. Toffoli Gte (TG): This gte in 3x3 RG form ontins three inputs, nd nd gives the three output of Op, Op2 nd Op3 nd it hs QC of 5. F. Proposed SN Gte (SNG): This gte is in 3x3 RG form ontins two inputs, nd nd gives the three output of Op, Op2 nd Op3 nd it hs QC of 4. PNG Fig. 6. Proposed SN Gte Op= Op2= Op3= + 27

3 Interntionl Journl of Eletril Eletronis & Computer Siene Engineering Volume 4, Issue 6 (Deemer, 207) E-ISSN : P-ISSN : Aville Online t Tle. 4. Truth Tle of SNG III. RELATED WORK In Yelekr et l. [7] desried RG to design the omplited iruits nd to implement these iruits in sequentil iruits lso in omintionl iruits. Authors hve designed dder iruits y using the nd TSG. Also, 4-it reversile ounter is presented nd mentioned its signifine in digitl iruit s pplitions like timer/ounter, ALU design nd lso in reversile proessor. In Knth et l. [8] hve given the omprison of onventionl gtes nd RGs. Also, the uthor hs studied the opertions like ddition nd sutrtion y using the DKG gte nd done omprison with the onventionl logi gtes. In this, 4x4 reversile DKG gte t s reversile full dder/su-trtor. The results of the si onventionl dder re ompred with RGs on Xilinx 9. softwre. In Goyl et l. [9] disussed reversile onept for design of low power/loss omputtionl strutures in every ALU iruits pplied for quntum omputtion nd lso in digitl iruits pplitions. Author proposed the omintionl iruit with RG nd oding performed in VHDL. In Gripelly et l. [0] explined the onstrints for RG whih does not llow fn out nd required low quntum ost, less grge outputs nd onstnt input. The uthor lso presented 6x6 BSCL RGs. In Pndey et l. [] presented 2/4 nd 3/8 reversile deoder using FyG nd FG nd re implemented using trnsmission gte. Author hs ompred vrious spets of the proposed deoder nd existing deoder. In Mlhotr et l. [2] mentioned vrious kinds of reversile multiplexers y implementing modified FG. In this, multiplexers like 6:, 8:, 4: nd 2: re presented nd ompred with quntum ost nd power onsumption of proposed reversile multiplexers with exiting multiplexer. The extended work of Mlhotr et l. [3] desried the onept of multiplexer design y using modified FG nd ompred with outomes of the si FG sed multiplexers outomes onsidering quntum ost. Thus, the ove litertures sys tht, there re very less work on the enoder nd deoder y using the reversile logi. Also, the existing works whih re proposed re not effiient in improving the APF performne. Also, found tht there is no enhmrking study in 8/0 enoder/deoder. IV. PROBLEM FORMULATION Tody s growth in the field of VLSI is demnding the low power sed devies nd the performne of the system should e mintined onstnt. But hieving the stedy performne with low power utiliztion is the igger tsk. Thus, most of the reserhers re fousing on sme issue. Mny of the power optimiztion tehniques hve een introdued in reent pst. Among these tehniques some of them hve signifintly proven etter results ut fils to give the optimisti results. The lok gting method ws used to optimize the power usge y disling the unwnted gte. But the trditionl gting method uses si irreversile gtes like AND, NOR, nd NAND et. In this gting method, the numer of gtes requires is high. Thus, novel system 8/0 enoder nd deoder with reversile gtes is must to optimize the power usge of the devie. The 8/0 enoder will ring high speed tion. In this hpter 8/0 enoder nd deoder design with two si Fredkin nd Peres reversile gtes is desried. Also, the Fredkin nd proposed SN gte sed 8/0 enoder nd deoder design is desried. V. EXISTING SYSTEM The 8/0 enoder/deoder priniple (Shown in figure.7.) is mpping trnsfer, in whih 8 dt will e trnsferred to 0 dt [4, 5]. During enoding 8 dt will e dividing into two groups, one group is of 3 nd nother of 5 dt. After enoding, t output end one group will e seprted with 4 nd nother of 6 to get the 0. i.e. the 5 lines ABCDE (from input 8 ABCDEFGH ) re enoded s 6 lines dei nd the 5/6 diretions re represented with logi funtions nd disprity ontrol. Also, the 3 lines FGH will e enoded s fghj. 28

4 Interntionl Journl of Eletril Eletronis & Computer Siene Engineering Volume 4, Issue 6 (Deemer, 207) E-ISSN : P-ISSN : Aville Online t Input 8 A B C D E K F 5 opertion 6 it ontrol Disprity ontrol 5/6 Enoding swith d e i Output 0 f reversile Fiendkin gte (FG) ut hve Peres gte () nd Proposed SN gte (SNG) respetively. The design ws followed with the Enoder nd deoder seprtely. The otined results from the oth the designs were ompred for performne evlution. For performne nlysis, we hve onsidered the totl numer of gtes used y whih the re, dely is optimized. For nlysis, we hve used Xilinx 4.7 nd modelsim-6f simultor. The design rhiteture of the proposed designs re given in Figure.2. Design Design 2 Control Dt G H K 3 opertion 4 it ontrol 3/4 Enoding swith Fig. 7. Working of 8/0 Enoder The differene mong the 's nd 0's of lok is onsidered s the disprity. In generl, the positive (+ve) disprity indited s 's while the negtive (-ve) disprity is indited s 0's. The permitted disprity mong 6 nd 4 su-loks is 0, -2 or +2. The ytes oding priniple needs the polrity of the non-zero disprity loks seprtely. Thus, no distintion is provided mong the 6 nd 4 su-loks, whih mens the surplus of two ('s) of 6 loks n e ompensted y two extr (0's) of 6/4 lok in idiretionl (Vie-vers). The ode points of non-zero disprity n e indited in omplimentry pirs to dt point of single soure. The enoding funtions n generte one of them nd if the lternte polrity rules, the entire su-lok get inverted to enoder swith. The polrity nd the disprity determintion in the 6 enoder n e performed y relevnt opertions of the 4 enoder. Lter, the running disprity prmeters n e given for enoding of next yte. Most of the oded suloks in enoding re of zero disprity nd re independent of running disprity mens zero disprity does not exhiit ny omplement. The deoding proess n e followed in reverse order. VI. PROPOSED SYSTEMS In lst setion, we hve ome ross the urrent issues in the VLSI system, whih need the low power devies. The tehnique whih is desried in reent pst uses more numer of si gtes like NAND, AND, NOR et. Due to use of more numer of gtes the power onsumption my not e t optiml level. Thus, system with 8/0 enoder nd deoder is presented. In this pper, we hve presented two different designs re presented in whih design nd 2 hve ommon g h j Reversile Gtes (Fredkin nd Peres) 8/0 Enoder Reversile Gtes (Fredkin nd Peres) 0/8 Deoder Performne omprison Figure.8. Design rhiteture VII. CIRCUIT IMPLEMENTATION Reversile Gtes (Fredkin nd Proposed SN gte) 8/0 Enoder Reversile Gtes (Fredkin nd Proposed SN gte) 0/8 Deoder The Enoder iruits implementtion for oth design nd 2 re followed with the 5/6 nd 3/4 lssifition, primry vetors genertion, disprity lssifition, ontrol of omplementtion nd finl enoder output. The enoding proess is followed s disussed in setion V. The disprity ontrol is used to deide whether omplementing the pre-enoded output or not need to generte new disprity vlues. The deoder is lso followed with kwrd proesses of enoder. The figures 3 nd 4, shows the implementtion of Enoder nd deoder for oth the designs, where represents the Peres gte while SNG represents proposed SN gte. 29

5 Interntionl Journl of Eletril Eletronis & Computer Siene Engineering Volume 4, Issue 6 (Deemer, 207) E-ISSN : P-ISSN : Aville Online t 0 RTL Shemti of Enoder 0 0 d0 e0 Contention of ll the ten s 0 dt out (Enoded out) i0 f0 g0 h0 Fig.. RTL Shemti of 8 to 0 Reversile Enoders j0 Fig. 9. Enoder Ciruit d0 e0 f0 g0 Contention of ll dt out (Deoded out) Fig. 2. RTL Shemti of 8 to 0 Reversile Deoders Simultion Results h0 Fig. 0. Deoder Ciruit VIII. RESULTS COMPARISON The otined results from the two-different enoder nd deoder re desried in this unit. Both the designs re oded with Xilinx 4.7 nd simulted y using modelsim- 6. The otined results of respetive reversile designs re ompred to know the performne of the designs. A. Design- Results: This gives the otined results of Fredkin nd Peres gte sed enoder nd deoder. Fig 3. Simultion Results of 8/0 Reversile Deoders 30

6 Interntionl Journl of Eletril Eletronis & Computer Siene Engineering Volume 4, Issue 6 (Deemer, 207) E-ISSN : P-ISSN : Aville Online t B. Design-2 Results: This gives the otined results of Fredkin nd proposed SN gte sed enoder nd deoder. RTL Shemti of Enoder Fig. 2. Simultion Results of 8/0 Reversile Deoders C. Comprtive Anlysis: The elow tle indites the enoder nd deoder from design nd 2, FG nd, SNG. Tle. 5. Totl Gtes Used in FG nd Design 8 to 0 Enoder- Deoder Reversile Gtes Totl Bsi Gtes Inluded FG * 8 = * 3 = 60 Tle. 6. Totl Gtes Used in FG nd SNG Design Fig. 4. RTL Shemti of 8 to 0 Reversile Enoders 8 to 0 Enoder- Deoder Reversile Gtes Totl Bsi Gtes Inluded Proposed SNG * 6 = 950 FG * 8 = 68 From the tle.5, 6 it is found tht the numer totl numer of reversile gtes used in design- is 3668 while in design-2 is 38. Fig. 5. RTL Shemti of 8 to 0 Reversile Deoders Simultion Results Fig.. Simultion Results of 8/0 Reversile Enoders IX. CONCLUSION The reversile logi sed omputtion (RLC) plys n importnt role in modern dys very lrge sle integrted (VLSI) iruit design. In this pper, we re presenting two different RG sed 8/0 enoding/ deoding systems. One system is designed with FG nd while the other system is repled with the proposed SN gte in ple of. Both the systems were ompred with eh other to find the signifint system mong them. The prmeters onsidered for the performne evlution re re nd totl numer of gtes used in oth the systems. X. REFERENCES [] Lnduer, R., Irreversiility nd het genertion in the omputing proess, IBM J. Reserh nd Development,5(3): pp. 83-9, 96. [2] Bennett, C.H., Logil reversiility of Computtion, IBM J.Reserh nd Development, 7: pp ,

7 Interntionl Journl of Eletril Eletronis & Computer Siene Engineering Volume 4, Issue 6 (Deemer, 207) E-ISSN : P-ISSN : Aville Online t [3] A.X.Widmer, P.A.Frnszek, A DC-Blned Prtitioned -Blok, 8B/0B Trnsmission Code IBM J.RES. DEVELOP Vol.27, No.5, nd Septemer 983. [4] K.V Mnoj, M.Amrnth Reddy," Design of Logi Ciruits Using Reversile Gtes", Interntionl Journl of Engineering Trends nd Tehnology (IJETT) Volume 6 Numer 8 Ot 204 [5] Sukhjeet Kur, Amndeep Singh Bhndri, "Design nd Performne Anlysis of Enoders using Reversile logi gtes", Interntionl Journl of Sientifi & Engineering Reserh, Volume 6, Issue 6, June-205 [6] Nhtigl, Mihel, nd Ngrjn Rngnthn. "Design nd nlysis of novel reversile enoder/deoder." Nnotehnology (IEEE-NANO), 20 th IEEE Conferene on. IEEE, 20. [7] Prshnt.R.Yelekr,Prof. Sujt S. Chiwnde, Introdution to Reversile Logi Gtes & its Applition, 2nd Ntionl Conferene on Informtion nd Communition Tehnology (NCICT) 20. [8] B.Rghu Knth, B. Murli Krishn, M.Sridhr, V.G.Snthi swroop, A Distinguish etween Reversile nd Conventionl logi Gtes, Interntionl journl of engineering reserh nd pplitions,vol.2,issue2, pril 202. [9] Mr. Devendr Goyl, M.Teh, Ms. Vidhi Shrm, VHDL Implementtion of Reversile Logi Gtes, Interntionl Journl of Advned Tehnology & Engineering Reserh (IJATER),ISSN NO: volume 2, issue 3,my202. [0] Rghv Gripelly,P.Mdhu Kirn,A.Snthosh Kumr, A Review on Reversile logi gtes nd their Implemnttion, Interntionl journl of emerging nd dvned engineering, Mrh 203, volume3,issue3. [] Neet Pndey,Nlin Ddhih, Mohd. Zuir Tlh, Reliztion of 2:4 reversile deoder nd its pplitions, Interntionl Conferene on Signl Proessing nd Integrted Networks (SPIN). IEEE,204. [2] Ashim Mlhotr, Chrnjit Singh, Amndeep Singh, Effiient Design of Reversile Multiplexers with Low Quntum Cost nd Power Consumption,Interntionl Journl of Emerging Tehnology nd Advned Engineering, Volume 4, Issue 7, July 204. [3] Ashim Mlhotr, Chrnjit Singh, Amndeep Singh, Effiient Design of Reversile Multiplexers with Low Quntum Cost, Int. Journl of Engineering Reserh nd Applitions, Vol. 4, Issue 7(Version 4), July 204. [4] Xu Qioyu, Liu Huijie, "8/0 Enoder Design", The 2nd Interntionl Conferene on Computer Applition nd System Modeling, 202. [5] Widmer A X, Frnszek P A. A DC -Blne, Prtitioned -Blok 8B/0B Trnsmission Code [J]. IBM Journl of reserh nd development, 983, 23(5):