Comparison between nmos Pass Transistor logic style vs. CMOS Complementary Cells*

Transcription

1 Comprison etween nmos Pss Trnsistor logi style vs. CMOS Complementry Cells* Rkesh Mehrotr, Mssoud Pedrm Xunwei Wu Dept. of E.E.-Systems Dept. of Eletroni Eng. University of Southern Cliforni Hngzhou University Los Angeles, CA 989, USA Hngzhou, Zhejing 328, Chin Astrt This pper ompres three different logi styles for implementing ritrry Boolen funtions of upto three inputs in terms of their lyout re, dely nd power dissiption. The three styles re nmos pss trnsistor sed design, NAND gte sed design, nd CMOS omplementry logi design. Results of the omprison show tht pss trnsistor sed design is superior to NAND sed design, ut loses to CMOS omplementry logi design. I. Introdution Dely nd power dissiption hve emerged s the mjor onerns of designers. The gte dely depends on the pitive lod of the gte. The dominnt term in power dissiption of CMOS iruits is the power required to hrge or dishrge the pitne in the iruit. Thus y reduing pitne we n derese the iruit dely nd power dissiption. Cpitne is in turn funtion of logi ells eing used in the design. There is urrently inresed interest in nmos pss trnsistor sed ells euse they pper to redue the pitne ompred to their stti CMOS ounterprts. There re indeed reent reports [] sed on full dder iruit omprison whih show tht nmos pss trnsistor logi to e more effiient thn CMOS omplementry logi. However some key questions remin unnswered. One of these questions is how the nmos pss trnsistor sed ell ompres to the NAND-sed ell or the CMOS omplementry ell (lso referred to ustom CMOS in the sequel) in terms of its performne hrteristis. In this pper we use the pss trnsistor sed ell Y in [] to onstrut si three input ell: NMUX2 ( multipleer followed y n inverter). Net we implement nd ompre 2 PNN-omplete three-input funtions whih over ll possile oolen funtions of less thn three-inputs y doing the physil lyout using the NMUX2 ell, using the three input NAND gte, nd finlly using CMOS omplementry logi gte. Our results show tht using the ustom CMOS ells yields the est performne hrteristis in terms of re, delynd power dissiption. The NMUX2-sed design rnks seond wheres the NAND3 sed design is distnt third. This onlusion should however e viewed in light of * This work ws supported in prt y DARPA under ontrt #F C-627. the ft tht the urrent tehnology mpping methods (e.g.,[7]) perform est when mpping is done to CMOS ells However there is room for improvement y using BDD sed tehniques to diretly synthesize pss trnsistor sed logi. For emples see [5, 6]. This pper is orgnized s follows. In the net setion we propose si three-input pss trnsistor ell NMUX nd ompre it with three-input NAND gte. In setion III we provide omprehensive omprison etween the three different logi styles: NMUX sed logi design, NAND gte sed logi design nd CMOS omplementry logi sed design. Setion IV desries our onlusions. II. Pss Trnsistor NMUX ell vs. CMOS NAND Gte A ell lirry is proposed in [], whih inludes four CMOS inverters with different driving pilities nd three psstrnsistor sed ells, Y, Y2, Y3 s shown in Fig.(). The output inverters mrked y lrge dot in these ells re omposed of five or three MOS trnsistors s shown in Fig.(). It is seen tht feedk inverter nd pull up pmos trnsistor, oth onsisting of minimum-size MOSFET s re inluded in the left onfigurtion to void DC lekge urrent in the CMOS inverter. If the onfigurtion with five trnsistors is used, the timing of the feed k signl is stle no mtter how lrge the lod pitne is. However, when the design proess is suh tht the designer n ensure tht the lod pitne of ell remins within n llowle rnge, the right onfigurtion in Fig.() with three trnsistors my e used. We hose ell Y in Fig.() nd onventionl CMOS ell of similr size for omprison. If we use onventionl NAND gtes in the design, emintion of rel designs indites tht the verge fnin ount of NAND gte is out 2.7 [2]. Thus, we hose the three-input NAND gte shown in Fig.2() for the purpose of omprison. Sine the ndidte reliztion using pss trnsistor sed ells should hve the sme numer of trnsistors s tht of three input NAND ells, we ompose ell Y with the three trnsistor inverter in Fig.() nd use stndrd inverter to generte the omplement ontrol signl C s shown in Fig.2(). Thus, oth ells in Fig.2 hve three-input terminls nd nerly the sme numer of trnsistors. (Cell in Fig.2() hs one etr minimum size pull up pmos trnsistor). The ell in Fig.2() n e nmed NMUX

2 V DD V DD Y Y 2 Y 3 Fig.() Pss Trnsistor Bsed Cell () output inverter V DD + Fig.2() Three input NAND gte () Three input pss-trnsistor sed NMUX ell Fig.3() Pss-trnsistor sed three input NAND gte euse it is multipleer (MUX gte) followed y n inverter (NOT gte). Comprison etween two si ells (whih hve equl numer of input terminls) my inlude the following: () logi struture with MUX. Silion re. 2. numer of ells required to relize ny funtion of k vriles 3. signl propgtion dely through the ell

3 4. power dissiption of eh ell for typil input vetor sequene. Criteri () nd (2) determine hip re wheres riteri (3) nd (4) ffet the iruit timing nd power dissiption. Tle. Comprison etween CMOS NAND nd Pss Trnsistor Bsed NAND Three-input Fig.2(): Fig.3(): Psstrnsistor-sed NAND gte Conventionl Tr. Count 6 () 3 (2.7) Are 329µm 2 () 579µm 2 (.75) Dely 295ps () 465ps (.58) Power.9µW/MHz ().96µW/MHz (.5) In [], Y 2 ell nd two inverters re used to form pss-trnsistor sed three-input NAND gte, s shown in Fig.3(). If we use the MUX legend to epress the iruit, we otin its orresponding logi struture s shown in Fig.3(). Comprison etween the pss-trnsistor sed three-input NAND gte nd the onventionl CMOS NAND gte is given in Tle. The re, dely nd power re evluted sed on.6 µm tehnology. The gte width of the output inverters in Y 2 ell is shown in Fig.(). The lod pitne is set to ff for the purpose of dely lultion. This tle shows tht the pss-trnsistor sed NAND hs more trnsistors (2.7 times), lrger re (.75 times), nd higher dely (.58 times). However, its power dissiption is etter thn epeted (only.5 times worse). In ft, we should ompre the three-input CMOS NAND gte of Fig.2() with the three-input pss-trnsistor sed NMUX ell of Fig.2(). This is euse these two gtes re the uilding loks of the iruits designed using NAND-sed logi nd pss trnsistor sed logi. It should e ler tht the re nd propgtion dely of the ells in Fig.2() nd 2() re nerly the sme, however, the ltter ells should hve lower power dissiption. This is euse Fig.3() nd Fig.2() hve omprle power dissiption, ut Fig.2() lerly hs lower power dissiption thn Fig.3(). In the following disussion, however, we will e onservtive nd ssume tht oth ells in Fig.2() nd Fig.2() hve omprle re, dely nd power dissiption. Fig.3 nd Tle show tht if we use the onventionl CMOS NAND gte nd pss-trnsistor sed NMUX ell to relize, the CMOS NAND gte is muh etter. However, this emple nnot e used to prove tht the CMOS NAND gte is etter in designing other iruits. For emple, onsider the three-input psstrnsistor sed NMUX ell shown in Fig.2(). If we use the three-input NAND gte nd inverter to relize the sme funtion we will need t lest three NAND gtes nd two inverters [2]. Consequently, the NAND nd NMUX ells hve to e ompred y implementing lrge numer of funtions nd verging results over these funtions s shown net nd in Tle 5. Consider ll funtions of n input. Beuse of the rpid inrese in the numer of funtions s n rises, we onfine our investigtion herewith to n 3. This hs the further merit tht detiled sttistis re lredy ville on the reliztion of n 3 funtions using three-input NAND gtes (nd three-input NOR gtes) [2]. Here we report nd ompre the sttistis for the threeinput pss-trnsistor sed ell to the NAND results. For onveniene, the 256 funtions of n 3 vriles re lssified into 8 representtive Permute(P)- omplete funtions; the 256 funtions re otined from these 8 funtions y input permuttions. Furthermore, we use the deiml numer funtion identifition system of [3] to tke the output vetor of the funtion truth tle nd re-epress it in deiml nottion. For emple, the ove funtion + hs n output vetor of (where the output vlue of minterms through re red from right to left), whih in deiml nottion eomes funtion 39. An emple of P- omplete trnsformtion would e the trnsformtion of the ove funtion + into funtion + y permuting nd. The 8 P-omplete funtions n e further lssified into 22 PN (Permute-Negte) equivlent funtions [3] Every funtion of given PN lss n e trnsformed into nother funtion in the sme lss y input permuttion nd/or input negtion. There re 22 PNomplete funtions for n 3 funtions. As n emple funtion + n e trnsformed into + y negting inputs nd The 22 PN-omplete funtions, n e further lssified into 4 representtive Permute-Negte-Negte (PNN) omplete funtions. Every funtion of given lss n e trnsformed to other funtions in the sme lss y input-negtion, input permuttion nd output negtion. For emple the ove funtion + n e trnsformed into funtion + + y negting inputs nd nd y negting the output. The numer of funtions in eh lss is shown in Tle 4. (The trivil lsses where the funtions re either onstnt or single vrile funtions re shown with *.) Minimum reliztions y using inverters nd NMUX gtes for the 2 non-trivil PNN-omplete funtions (one from eh lss) re tulted in Tle 2. Dt orresponding to NAND reliztion (tken from [2]) re lso listed in the tle for omprison). For eh iruit we report the numer of inverters nd NMUXs used (n inv, n nmu ), the numer of input onnetions (n ) for ll devies used, nd the numer of devie sde levels (n l ). We lso report the orresponding numers given in [2] when the inverter nd three-input NAND gte re used insted. From Tle 2, it n e seen tht if we use the NMUX2 nd inverter in design, we will sve n verge of 38% ells nd 73% inverters. There will lso e 55% redution in the numer of onnetions nd 28% redution in the numer of sde levels. Oviously, re, dely nd power dissiption of these iruits will signifintly e improved sine oth 3-input pss-trnsistor sed ell nd CMOS NAND gte hve pproimtely the sme re, dely, nd power dissiption.

4 We tke the full dder s prtil design emple to ompre oth ells. The sum nd the rry-out outputs re funtions (5) nd (232) respetively: S = ( ) +, Cout = ( ) +. The orresponding design with NMUX2 is shown in Fig.4(), where only three ells nd two inverters re used. However, the S output lone needs si 3-input NAND gtes, s shown in Fig.4(). III. Pss Trnsistor Bsed NMUX ell vs. CMOS Complementry Logi ell Although pss trnsistor sed design yields etter results ompred to NAND gte sed design, the omprison is not tht useful s logi design is lmost never done y using NAND gtes elusively. A relisti omprison would e etween logi design done using stndrd ell lirry (CMOS omplementry ells) nd pss trnsistor sed design. Thus we hve tken one funtion from eh of the 2 PNN non-trivil lsses nd implemented it using Y ells nd ustom CMOS ells. Here, we ssume tht the stndrd ell lirry ontins t lest one funtion of eh PNN-omplete lss. We use.6um tehnology for lying out ll the 2 funtions. We use the MAGIC lyout editor nd use the HP-CMOS4B proess prmeters for etrtion. The HP-CMOS4B Level-39 FET models were used for HSPICE [4] simultions. The lod pitne for eh of the iruits ws set to ff for iruit dely hrteriztion. Worst se dely mesurements were mde for eh funtion implemented using Y-ells, NAND gtes nd ustom CMOS ells y nlyzing the ell struture nd finding the slowest input to output pth hnge. We used the sme input vetors to lulte the power dissiption for eh design. A softwre progrm ws used to lulte the energy used y eh iruit for time period of ns during whih time the output swithed etly twie etween different voltge levels. The progrm lultes disrete version of the V.I.dt integrl when given the supply urrent t intervls of ns for ns. The results re shown in Tle 5. IV. DISCUSSION The tulted results shown ove indite tht lyout using CMOS omplementry ells (olumn 3) yields the est performne hrteristis in terms of dely, power dissiption nd re. This hrteriztion ws done to set referene point whih pss trnsistor logi would hve to improve upon to e vile for use in the future. If the ells were only mpped to NAND ells, then the Y-ell pss trnsistor implementtion would e superior for the 2 PNN - omplete funtions. This is however not ommon prtie. The purpose of this pper ws to investigte the viility of Y-ell pss trnsistor logi to synthesize iruits s opposed to 3-input NAND gtes nd ustom CMOS ells. From the ove tle, it n e seen tht the Y-ell implementtion yields lower res for given dely when ompred to NAND gte implementtion. However Y-ell sed implementtions ompred with ustom lyout implementtions tend to e inferior. It n e seen tht the Y-ell implementtion yields iruits of smller res thn the NAND gte implementtion in out of the 2 ses, ut when ompred to ustom lyout, they re lrger in 2 out of 2 ses. As for energy onsumption under the sme input vetor sequene, the Y-ell implementtion yields etter results in only 5 ses when ompred to NAND ells nd ompred to ustom CMOS ells Thus in terms of power dissiption the results re somewht unertin. In summry, the Y-ell implementtion seems to yield etter results for dely nd re mesurements when ompred with NAND gte sed implementtion ut is inferior to CMOS omplementry ells. Our onlusion is however sed on the premise tht the sme synthesis nd mpping tehnology is used for oth stndrd ell sed design nd pss trnsistor sed designs. If the synthesis nd mpping sripts re hnged it is possile tht pss trnsistor logi style would e etter hoie thn stndrd ell logi. Our pper does neither support nor rejet this possiility. Furthermore we ssumed tht the ASIC lirry is PNN omplete with respet to ll 2 nd three input funtions. REFERENCES [] K.Yno, Y. Sski, K.Rikino nd K. Seki, Top-down pss-trnsistor logi design, IEEE J. Solid-stte Ciruits, Vol.SC-3, pp , 996. [2] L.Hellermn, A tlogue of three-vrile OR-Invert nd AND-Invert logi iruits, IEEE Trns. Eletron Computers, Vol.E-2, pp98-223, 963. [3] G. J. Klir, Introdution to the Methodology of Swithing Ciruits, D. Vn Nostrnd Compny, 972. [4] HSPICE refrene mnuls y Met Softwre. [5] P. Buh, A. Nryn, A. R.Newton, A. Sngiovnni- Vinentelli, On synthesizing pss-trnsistor networks, Interntionl Workshop on Logi Synthesis, 997. [6] V.Berto, S.Minto, P.Verpletse, L.Benini, G. De iheli, Deision digrms nd pss trnsistor logi synthesis, Interntionl Workshop on Logi Synthesis,997. [7] K.Keutzer, Tehnology mpping nd lol optimiztion, Pro. of the 24 th Design Automtion Conferene, pp , 987.

5 Funtion Funtionl epression NMUX nd inverter NAND nd inverter (deiml) n inv n nmu n n l n inv n nnd n n l (27) ( ) (26) () + ( ) (63) (5) ( ) (52) (47) (232) ( ) (22) (2) (5) ( ) (53) Tle 2:Fourteen representtive funtion for n<4 + = Tle 3: NMUX vs. NAND sttistis for n = 2,3 funtions Type of iruit ell 3-input NMUX 3-input NAND Numer of input terminls per ell 3 () 3 () Totl numer of devies required for ell funtions 593 (.53) 5 () Averge inverter ount per funtion.5 (.36).4 () Averge ell ount per funtion.8 (.58) 3.9 () Averge input onnetion ount per funtion 5.3 (.44).4 () Averge sde level ount per funtion 2.5 (.7) 3.8 () S C out S Fig.4() Full Adder y using NMUX2 () Sum reliztions y using three input NAND gte Tle 4: Clssifition of n<4 funtions into 4 PNN lsses Clss I II III IV V VI VII VIII IX X XI XII XIII XIV Funtion in (Deiml) Numer of funtions * *

6 Tle 5: Detiled Comprison FUNCTION (Deiml) AREA(um 2 ) DELAY(ns) ENERGY(pJ) TWO && THREE INPUT NAND GATE CMOS COMPLEMENTARY LOGIC PASS TRANSISTOR LOGIC 27: AREA DELAY