THEORETICAL BACKGROUND FOR THE APPLET DESIGN AND TEST OF DIGITAL SYSTEMS ON RT-LEVEL AND RELATED EXERCISES

Transcription

1 TALLINN TECHNICAL UNIVERSITY Faculty of Informaton Technology Department of Computer Engneerng Char of Computer Engneerng and Dagnostcs THEORETICAL BACKGROUND FOR THE APPLET DESIGN AND TEST OF DIGITAL SYSTEMS ON RT-LEVEL AND RELATED EXERCISES TALLINN 2003

2 TABLE OF CONTENTS PRINCIPLES OF HIGH-LEVEL DESIGN REPRESENTATION...4. LEVELS OF ABSTRACTION REGISTER-TRANSFER DESIGN THE CONCEPT OF DATAPATH THE CONCEPT OF CONTROL UNIT INTRODUCTION TO TESTING TESTING TEST GENERATION BRIEF DESCRIPTION OF FAULT MODELS SINGLE STUCK FAULT MODEL MULTIPLE STUCK-FAULT MODEL FAULT SIMULATION FAULT COVERAGE DETERMINISTIC TEST INTRODUCTION TO DETERMINISTIC TEST BASIC OPERATIONS OF DETERMINISTIC TEST THEORY AND OPERATION OF LINEAR FEEDBACK SHIFT REGISTER BRIEF DESCRIPTION OF LFSRS STRUCTURE CHARACTERISTIC POLYNOMIALS PERIODICITY OF LFSRS CHARACTERISTICS OF MAXIMUM LENGTH SEQUENCES LFSRS USED AS SIGNATURE ANALYZERS SHIFT REGISTER POLYNOMIAL DIVISION ERROR POLYNOMIAL AND MASKING MULTIPLE-INPUT SIGNATURE REGISTER SELECTION OF THE POLYNOMIAL P (X) INCREASING THE EFFECTIVENESS OF SIGNATURE ANALYSIS CONCLUDING LFSRS THEORY BUILT-IN SELF-TEST (BIST) INTRODUCTION TO BIST CONCEPTS TEST-PATTERN GENERATION FOR BIST EXHAUSTIVE TESTING PSEUDORANDOM TESTING PSEUDOEXHAUSTIVE TESTING CIRCULAR SELF-TEST PATH (CSTP) BUILT-IN LOGIC BLOCK OBSERVATION (BILBO) FUNCTIONAL TESTING INTRODUCTION TO FUNCTIONAL TESTING EXHAUSTIVE AND PSEUDOEXHAUSTIVE TESTING PARTIAL-DEPENDENCE CIRCUITS PARTITIONING TECHNIQUES FUNCTIONAL BIST APPLET DESIGN AND TEST OF DIGITAL SYSTEMS ON RT-LEVEL DESCRIPTION...39 REFERENCES

3 PRINCIPLES OF HIGH-LEVEL DESIGN REPRESENTATION. LEVELS OF ABSTRACTION Wthn the product defnton, desgn and manufacturng process, each person looks at the product from a slghtly dfferent pont of vew and requres specfc nformaton to support hs or her work. For ths reason, each product, and consequently each desgn, requres several dfferent representatons or vews, whch dffer n the type of nformaton that they emphasze. In addton the same representaton often requres dfferent levels of detal n dfferent phases of the desgn. The three most common types of representaton that are used are behavoral, structural, and physcal representatons. System Level Behavoral Doman A RTL Level Logc Level Crcut Level Structural Doman P Physcal Doman Fgure. The Y-chart To defne and dfferentate types of representatons, use the Y-chart, a trpartte representaton of desgn, whch s shown n Fgure. The aes n the Y-chart represent three dfferent domans of descrpton: behavoral, structural and physcal. Along each as are dfferent levels of the doman descrpton. As to move farther away from the center of the Y, the level of descrpton becomes more abstract. Drawng concentrc crcles on the Y can etend ths chart. Each crcle ntersects the Y- as at a partcular level of representaton wthn a doman. The crcle represents all the nformaton known about the desgn at some pont of tme. The outer crcle s the system level; the net s mcroarchtectural or regster-transfer (RT) level, followed by the logc and crcut levels. Table lsts these levels. In the behavoral doman desgners are nterested n what a desgn does, not n how t s bult. Usually desgn s treated as one or more black boes wth a specfed set of nputs and outputs and a set of functons descrbng the behavor of each output n terms of the nputs over tme. A behavoral descrpton ncludes an nterface descrpton and descrpton of constrants mposed on a desgn. The nterface descrpton specfes the I/O ports and tmng relatonshps or protocols among sgnals at those ports. Constrants 4

4 specfy technologcal relatonshps that must hold for the desgn to be verfable, testable, manufacturable and mantanable. Level Name Behavoral Representaton Structural Representaton Physcal Representaton System level System specfcaton Blocks Chp Regstertransfer level RTLspecfcaton Regsters Macro cells Logc level Boolean functons Logc gates Standard cells Dfferental Crcut level Transstors Contacts equatons Table. Objects desgn at dfferent abstracton levels To descrbe behavor, transfer functons and tmng dagrams are used on a crcut level and Boolean epressons and state dagrams on the logc level. On the RT level, tme s dvded nto ntervals called control states or steps. Regster-transfer descrpton specfes for each control state the condton to be tested; all regsters transfers to be eecuted, and the net control state to be entered. On the system level varables and language operators are used to epress functonalty of system components. Varables and data structures are not bound to regsters and memores, and operatons are not bound to any functonal unt or control states. In a system level descrpton, tmng s further abstracted to the order n whch varable assgnments are eecuted. A structural representaton brdges the behavoral and physcal representaton. It s oneto-many mappng of a behavoral representaton onto a set of components and connectons under constrants such as cost, area and delay. The most commonly used levels of structural representaton are dentfed n terms of the basc structural elements used. On the crcut level the basc elements are transstors, resstors and capactors, whle gates and flp-flops are the basc elements on the logc level. ALU s, multplers, regsters; RAM s and ROM s are used to dentfy regster-transfers. Processors, memores and buses are used on the system level. The physcal representaton gnores, as much as possble, what the desgn s supposed to do and bnds ts structure n space or to slcon. The most commonly used levels n the physcal representaton are modules, mult-chp modules (MCMs) and prnted crcut (PC) boards. [3].2 REGISTER-TRANSFER DESIGN In ths secton the concept of datapath and control unt, dfferent technques of specfyng control unt and mnmzng datapath for the desgn synthess on regster- 5

5 transfer level wll be presented. Snce each RT mplementaton defnes both a control unt and a datapath, we can approach the concept o these parts separately..2. THE CONCEPT OF DATAPATH RT-level desgns are composed of two nteractng parts: datapath and control unt. Usually datapath conssts of storage unts such as regsters, regster fles, and memores, and combnatoral unts such as ALUs, multplers, shfters etc. Buses connect these unts, the nput and output ports. The datapath takes the operands from storage unts, performs the computaton n the combnatoral unts, and returns the results to storage unts durng each state, whch s usually equal to one clock cycle. The control unt controls the selecton of operands, operatons, and the destnaton for the results by settng proper values of datapath control sgnals. The datapath also ndcates through status sgnals when a partcular value s stored n a partcular storage unt or when a partcular relaton between two data values stored n the datapath s satsfed. For many hgh-speed applcatons smple datapaths are too slow. In order, to ncrease the performance smple datapath redesgn so that several operatons could be performed concurrently. These faster datapaths are called parallel datapath. The obvous way to parallelze datapath would be to ncrease the number of regsters and use several functonal unts. But note, that the performance ncrease n a parallel datapath wll depend not just on the number and type of unts n the datapath, but also on ther connectvty and the amount of parallelsm that s avalable n the algorthm whch s eecutng on datapath. For the best performance/cost rato, the types of unts and ther connectvty must match the parallelsm n the gven algorthm. There are some general technques to optmze, to mnmze the mplementaton of the datapath, whch based on the followng component types used n the datapath: storage components and functonal unts. By focusng on the storage components, for eample, we note that the varables n the datapath must be stored n regsters, regster fles, and memores. However, snce not varables are used at the same tme, t s possble for certan varables to share the same regster or the same locaton n a regster fle or memory. So we can merge the datapath varables n a way that reduces the number of storage locatons n the datapath. Alternatvely, certan optmzaton technques can focus on mnmzng the number of functonal unts n the datapath. In each state, selected varables are to be assgned new values through varous arthmetc, logc or shft operatons, each of whch can be performed by a separate functonal unt. However, snce most of these operatons are eecuted n dfferent states, they could share the same functonal unt. So, we can reduce the number of unts n the datapath by combnng dfferent operatons nto groups, allowng each group of operatons to be eecuted n a sngle functonal unt. Mnmzng the number of functonal unts n a datapath we deal wth functonal unt sharng. Functonal unt sharng s possble, because wthn any gven state, a datapath wll not perform every operaton. Therefore, smlar operators can be grouped nto a sngle multfuncton unt, whch wll be used more frequently, thus ncreasng the unt utlzaton. In some cases, of course, groupng operatons n ths manner may not reduce 6

6 the cost of the datapath, snce dssmlar operators often requre structurally dfferent desgns, groupng them can sometmes result n no gan or even n a hgher cost. a b c d a c b d selector selector + - +/- y y (a) No shared desgn (b) Shared desgn Fgure 2. Functonal unt sharng In ths eample s assumed that the datapath wll perform two dfferent operatons, addton and subtracton, on dfferent operands n dfferent states. If we use snglefuncton unts, we wll get the desgn shown n Fgure 2(a), n whch the datapath requres both an adder and a subtractor. We can, however, obtan the same functonalty by usng only one adder/subtractor and two selectors, as shown n Fgure 2(b). Obvously, the second desgn wll be preferable when the cost of an adder/subtractor and two selectors s less than the cost of a separate adder and subtractor..2.2 THE CONCEPT OF CONTROL UNIT Smlar to the datapath, a control unt has a set of nput and a set of output sgnals. Each sgnal s a Boolean varable that can take value of 0 or. There are two types of nput sgnals: eternal sgnals and status sgnals. Eternal sgnals represent the condtons n the eternal envronment on whch crcut must respond. The status sgnals represent the state of the datapath. Ther value s obtaned by comparng values of selected varables stored n the datapath. There are also two types of output sgnals: eternal sgnals and datapath control sgnals. Eternal sgnals dentfy to the envronment that crcut has reached a certan state or fnshed a partcular computaton. The datapath controls select the operaton for each component n the datapath. In order to specfy control unt we wll look at two dfferent technques. The frst technque s based on fnte state machnes that are usually represented graphcally. The second technque, called mcroprogrammed control, uses a programmng representaton for control unt. The frst technque we use to specfy a control unt s fnte state machne. The fnte state machne (FSM) conssts of a set of states and drectons on how to change states. The FSM can be defned abstractly as the quntuple <S, I, O, f, h>, where S, I, and O represent a set of outputs, respectvely, and f and h represent the net state and output functons. The net state functon f s defned abstractly as a mappng S * I S. The FSM model assumes that the tme s dvded nto unform ntervals and these transtons from one state to another occur only at the begnnng of each tme nterval. Therefore, the net state functon f defnes what the state of the FSM wll be n the net tme 7

7 nterval gven the state and nput values n the present nterval. The output functon h determnes the output values n the present state. There are two dfferent types of FSM, whch correspond to two dfferent defntons of the output functon h. One type s a state-based or Moore FSM, for whch h s defned as a mappng S O. The output symbol s assgned to each state of the FSM, and depends only on the current state. The other type s an nput-based or Mealy FSM, for whch h s defned as the mappng S * I O. In ths case, a par of state and nput symbols defnes an output symbol n each state. As t was told earler, the second technque of specfyng the control unt s mcroprogrammed control, whch s based on follows: A set of control sgnals that must be asserted n a gven state s defned by mcronstructons selected n mcroprogram. In order to control dfferent transtons between the states of mcroprogram are defned by a set of datapath status sgnals. Whch, usually, take a value of 0 or. Desgnng a control unt as an algorthm that mplements the smpler mcronstructons s called mcroprogrammng. The key dea of mcroprogrammng s to represent the asserted values of control lnes symbolcally, so the mcroprogramm s a representaton of mcronstructons. Mcroprogram s a representaton of the control unt that wll be translated by algorthm to control logc.[6] 8

8 2 INTRODUCTION TO TESTING 2. TESTING Testng of a system s an eperment n whch the system s eercsed and ts resultng response s analyzed to ascertan whether t behaved correctly. If ncorrect behavor s detected, a second goal of a testng eperment may be to dagnose, or locate, the cause the msbehavor. Dagnoss assumes knowledge of the nternal structure of the system under test. These concepts of testng and dagnoss have a broad applcablty; consder, for eample, medcal tests and dagnoses or debuggng a computer program. An mportant problem n testng s test evaluaton, whch refers to determnng the effectveness, or qualty of a test. Test evaluaton s usually done n the contet of a fault model, and the qualty of a test, fault coverage. Test evaluaton s carred out va a smulated testng eperment called fault smulaton. Fault coverage and fault smulaton wll be descrbed n ths secton as well. 2.2 TEST GENERATION Test generaton (TG) s the process of determnng the stmul necessary to test a dgtal system. TG depends prmarly on the testng method employed. On-lne testng methods do not requre TG. Lttle TG effort s needed, when a feedback shft regster workng as a pseudorandom sequence generator provdes the nput patterns. Automatc TG (ATG) refers to TG algorthm that, gven a model of a system, can generate tests for t. Random TG (RTG) s a smple process that nvolves only generaton of random vectors. However to acheve a hgh-qualty test a large set of random vectors s needed. TG can be fault orented or functonal orented. In fault-orented TG, ones try to generate tests that wll detect (and possbly locate) specfc faults. In functon-orented TG, one tres to generate a test that, f t passes, shows that the system performs ts specfed functon. 2.3 BRIEF DESCRIPTION OF FAULT MODELS. Falure modes are manfested on the logcal level as ncorrect sgnal values. A fault s a model that represents the effect of a falure by means of the change that s produced n the system sgnal. Several defects are usually mapped to one fault model. But some defects can be also represented by more than one fault model. The table lsts the common fault models. Fault model Descrpton Sngle stuck-at faults (SSF) One lne takes the value 0 or. Multple stuck-at faults Two or more lnes have fed values, not necessarly the same. Brdgng faults Two or more lnes that are normally ndependent become electrcally connected. Delay faults A fault s caused by delays n one or more paths n the 9

9 crcut. Intermttent faults Caused by nternal parameter degradaton. Incorrect sgnal values occur for some but not all states of the crcut. Degradaton s progressve untl permanent falure occurs. Transent faults Incorrect sgnal values caused by coupled dsturbances. Couplng may be va power bus capacty or nductve couplng. Table 2. Most commonly used Fault Models. Faults defned n conjuncton wth a structural model are referred to as structural faults; ther effect s to modfy the nterconnectons among components. Functonal faults are defned n conjuncton wth a functonal model. Although ntermttent and transent faults occur often, ther modelng requres statcal data on ther probablty of occurrence. These data are needed to determne how many tmes an off-lne testng eperment should be repeated to mamze the probablty of detectng a fault that s only sometmes present n the crcut under test. Unfortunately, ths type of data s usually not avalable. Intermttent and transent faults are better dealt wth by on-lne testng. The smplfyng sngle-fault assumpton s justfed by the frequent testng strategy, whch states that we should test a system often enough so that the probablty of more than one fault developng between two consecutve testng eperments s suffcently small. Thus f mantenance ntervals for a workng system are too long, we are lkely to encounter multple faults. But even when multple faults are present, the tests derved under a sngle-fault assumpton are usually applcable for the detecton of multple faults, because, n most cases, a multple fault can be detected by the tests desgned for the ndvdual sngle faults that compose the multple one. In general, structural fault models assume that components are fault-free and only ther nterconnectons are affected. Typcal faults affectng nterconnectons are shorts and opens. A short s formed by connectng ponts not ntended to be connected, whle an open results from the breakng of a connecton. For eample, n many technologes, a short between ground or power and a sgnal lne can make the sgnal reman at a fed voltage level. The correspondng logcal fault conssts of the sgnal beng stuck at a fed logc value v (v {0, }), and denoted by s-a-v. A short between two sgnal lnes usually creates a new logc functon. The logcal fault representng such a short s referred to as a brdgng fault. The effect of an open on undrectonal sgnal lne wth only one fanout s to make the nput that has become unconnected due to the open assume a constant logc value and hence appear as a stuck fault (Fgure 3(a)). An open n a sgnal lne wth fanout may result n multple stuck fault, as t shown n Fgure 3(b). 0

10 open Stuck lne open Stuck lnes (a) Sngle stuck at fault (b) Multple stuck fault Fgure 3. Stuck faults caused by opens 2.4 SINGLE STUCK FAULT MODEL The sngle-stuck fault model s also referred to as the classcal or standard fault model because t has been the frst and the most wdely studed and used. Although ts valdty s not unversal, ts usefulness results from the followng attrbutes: It represents many dfferent physcal faults. It s ndependent of technology, as the concept of a sgnal lne beng stuck at a logc value can be appled to any structural model Compared to other fault models, the number of SSFs n a crcut s small. SSFs can be used to model other types of faults. The last pont s llustrated n Fgure 4. To model a fault that changes the behavor of the sgnal lne z, we add to orgnal crcut a multpleor that realzes the functon z = z f f = 0 z = z f f = f The new crcut operates dentcally to the orgnal crcut for f=0 and can realze any faulty functon z f by nsertng the fault s-a-. For eample connectng to z f would create the effect of a functonal fault that changes the functon of the nverter from z = to z =. Connectng to z f va an nverter wth a dfferent delay would create the effect of delay model. z z 0 zf Z Fgure 4. Model modfcaton f

11 2.5 MULTIPLE STUCK-FAULT MODEL The multple stuck-fault (MSF) models are a straghtforward etenson of the SSF model n whch several lnes can be smultaneously stuck. If we denote by n number of possble SSF stes, there are 2n possble SSFs, but there are (3 n ) possble MSFs (whch nclude the SSFs). If we assume that the multplcty of a fault, the number of lnes smultaneously stuck, s no greater than a constant k, then the number of possble MSFs s k n ( ) 2 = Ths s usually too large number to allow dealng wth all multple faults. To detectng MSFs, t s always possble to use ehaustve and pseudoehaustve testng. However, t s not practcal for large crcuts. The most mportant factors that affect the detectablty of MSFs are the number of prmary outputs and reconvergng fanouts. Stmul Desgn Smulator Lbrary Response Fgure 5. Elements of smulaton We are not gong to descrbe other fault models, such as brdgng faults, delay faults and temporary faults, the short descrpton of these models s gven n Table FAULT SIMULATION Fault smulaton s performed durng the desgn cycle to acheve the followng goals: Testng specfc faulty condtons. Gudng the test pattern generaton program. Measurng the effectveness of the test patterns. Generatng fault dctonares. To perform the task of fault smulaton, the fault smulaton program requres, n addton to the crcut model, the stmul, and the responses of a good crcut to the stmul, a fault model and a fault lst. As t was mentoned above, there are dfferent fault models, and the most wdely used s the stuck-at model. The responses deduced by the fault smulator are used to determne the fault coverage. The fault smulaton process s shown n Fgure 5. A fault s consdered from the lst and a pattern s appled to the crcut. If the fault s detected, t s dropped from the fault lst 2

12 and the net fault s consdered. Otherwse, another pattern s appled; the fault s then consdered undetectable by the test and s removed from the fault lst. The process s contnued untl the fault lst s empty. After fault smulaton, the faults are ether detected or undetected. The fault s detected f t has been controllable and observable by one of the patterns n the test set. In such case, at least one of the prmary outputs of the faulty crcut s dfferent from the good crcut. Otherwse, t s not detected by any of the patterns of the test set. 2.7 FAULT COVERAGE The effectveness of the test set s quantfable. It s the percentage of the faults detected by a test and s known as fault coverage, defned as fault coverage = And a more realstc epresson s fault coverage = faults detected total number of faults detected detectable faults faults In other words, ths s a percentage of detectable faults n the crcut under test (CUT) that are detected by a test set. The set s complete f ts fault coverage s 00%. The level of fault coverage s desrable but rarely attanable n most practcal crcuts. Moreover, the 00% fault coverage does not guarantee that the crcut s fault-free. The test checks only for falures that can be represented by the model used, such as stuck-atfault-model. Other falures are not necessarly detected. 2.8 DETERMINISTIC TEST 2.8. INTRODUCTION TO DETERMINISTIC TEST In contrast to Random Test Generaton, whch s generally works wthout takng nto account the functon or the structure of the CUT, determnstc test generaton produces tests by processng a model on the crcut. But determnstc test s more epensve, but t produces shorter and hgher-qualty tests. Model ATG Tests Fault Unverse Dagnostc Data Fgure 6. Determnstc test generaton system 3

13 Determnstc test can be fault-orented or fault-ndependent. In a fault-orented process, tests are generated for specfed faults, whereas a fault-ndependent test works wthout targetng faults. Fgure 6 shows a general vew of a determnstc test generaton system. Tests are generated based on a model of the crcut and a gven fault model. The generated tests nclude both the stmul to be appled and the epected response of the fault-free crcut. Some test generaton systems also produce dagnostc data to be used for fault locaton. As t was told generated tests based on a gven fault model, the fault model n our case s the stuck-at fault model. Usng determnstc test generaton some heurstc algorthms can be proposed. The best known are the D-algorthm, crtcal path algorthm, PODEM and SOCRATES. All algorthms are based on the four man operatons processes of ectaton, senstzaton, justfcaton, and mplcaton. The D-algorthm starts at the faulty lne, and ts man dffculty s n reconvergng fan-out. The crtcal path algorthm starts from the prmary outputs of the crcut and generates a test pattern for several faults, whle PODEM starts from the prmary nputs BASIC OPERATIONS OF DETERMINISTIC TEST To generate the pattern for a stuck at fault on a lne, we need to provoke or ecte the fault, senstze the results to a prmary output, and justfy the logc values requred on the other lnes n the crcut. It s needed to fnd mplcatons of these values on other gates. To provoke or ecte a lne s to control t to a logc value that s the complement of the value at whch t s stuck; ths s equvalent to placng the faulty sgnal on the lne. The sgnal s a dscrepancy from the fault-free crcut. For eample, to provoke the stuck-at fault on lne W, W/, of the crcut n Fgure 7, we must put 0 on ths lne, W=0. It s necessary to senstze or propagate the fault to a prmary output n order to observe t. The path from the faulty locaton to the prmary output s a senstzng or propagaton path. A fault may have more than one senstzng path to the same output or to dfferent outputs. The fault W/ has one senstzng path: trough G3, G4, and G6. To senstze the fault to the output of G3, we must have E=. Fnally to propagate the fault to the prmary output, Z, we need to have H=. The values on E and H need to be justfed to the prmary nputs. 4

14 Senstzaton or Propagaton A=0 B=0 Justfcaton W/ C G E= G3 Implcaton G2 0 V U = 0 F G G4 G 6 H= Justfcaton G5 Z Fgure 7. Test pattern generaton termnology We justfy on E by havng A =B =0. Net we fnd the mplcaton of B on gate G2. Sometmes n propagatng and justfyng we encounter a conflct because some of the lnes we need to control have values already assgned. In such cases t s sad that we encountered an nconsstency. [2] 5

15 3 THEORY AND OPERATION OF LINEAR FEEDBACK SHIFT REGISTER In ths secton some of the formal propertes assocated wth lnear feedback shft regsters wll be presented. LFSRs are used etensvely n two capactes n DFT and BIST desgns, as a source of pseudorandom bnary test sequences and as a means to carry out response compresson known as sgnature analyss. 3. BRIEF DESCRIPTION OF LFSRs STRUCTURE Consder the feedback shft regsters shown n Fgure 8. These crcuts are all autonomous they have no nputs ecept for clocks. Each cell s assumed to be a clocked D flp-flop. It s well known that such crcuts are cyclc n the sense that they clocked repeatedly; they go through a fed sequence of states. For eample, a bnary counter consstng of n flp-flops would go through a fed sequence of states 0,, 2 n-, 0,,. The mamum number of states for such a devce s 2 n. The shft regster shown n a Fgure 8(a) cycles through only two states. If the ntal state were 00 or, t would never change state. An n-bt shft regster cycles through at most n states. Notce that the output sequence generated by such a devce s also cyclc. The crcut of Fgure 8(b) startng n the ntal state (or 000) produces a cyclc sequence of states of length. The sequence generated for the crcut of Fgure 8(c) f the ntal state s 0 s shown n Fgure 8(b). In Fgure 8(d) s llustrated the case where sequence generated by the feedback shft regster s of the length (2 3 -). The crcut of Fgure 8(d) s sad to be a mamal-length shft regster, snce t generated a cyclc state sequence of length (2 n -), as long as ts ntal state s not all zeros. Also f one of these crcuts generates a cyclc state sequence of length k, then the output sequence also repeats tself every k clock cycles. Output sequence State S 0 0 Repeated.. subsequence S 0 S S = S 0 S 2 = S 0 0 (a) (b) 6

16 S 0 0 S 0 0 S S S 4 = S S 0 0 S S S 4 0 (c) S 5 0 S S 7 = S 0 0 Fgure 8. Feedback shft regsters (d) A lnear crcut s a logc network constructed from the followng basc components: unt delays or D flp-flops; modulo- 2 adders; modulo- 2 scalar multplers; In the analyss of such crcuts, all operatons are done modulo 2. The truth table for modulo- 2 addton and subtracton s shown below. ± Thus + = - - = - = o Such a crcut s consdered to be a lnear snce t preserves the prncple of superposton, because ts response to a lnear combnaton of stmul s the lnear combnaton of the responses of the crcuts to the ndvdual stmul. In ths secton wll be descrbed a class of lnear crcuts, known as autonomous lnear feedback shft regsters that have the canoncal form shown n Fgures 9. and 9.2. Here c s a bnary constant and c = mples that a connecton ests, whle c = 0 mples that no connecton ests. When c = 0 the correspondng XOR gate can be replaced by a drect connecton from ts nput to ts output. 7

17 D Q Fgure 9.. Type (eternal- XOR) LFSR D Q Fgure 9.2. Type 2 (nternal-xor) LFSR 3.2 CHARACTERISTIC POLYNOMIALS A sequence number a 0, a,,a m, can be assocated wth a polynomal, called a generatng functon G(), by the rule G()= a 0 + a + a a m m. Let { a m }= a 0, a, represent the output sequence generated by an LFSR, where a =0 or. Then ths sequence can be epressed as = G ( m ) a m () m=0 For the type LFSR, t could be shown, that f the current state of Q s a m-, for =, 2,, n, then a m n = ca = Thus recurrence relaton can defne the operaton of the crcut. Let the ntal state of LFSR be a, a 2,, a n+, a n. The operaton of the crcut starts n clock perods before generatng the output a 0. Snce m (2) Substtutng for a m we get = G ( ) a m m=0 m 8

18 9 [ ]. ) ( ) ( G a a c a a a c a c a c G n m m m n m m m n m m n m = = = = = = = = = = = = Hence ( )... ) ( ) ( = = = a a c G c G n n Or ( ) = = = n n c a a c G... ) ( (3) Thus G () s a functon of the ntal state a, a 2,, a n+, a n of the LFSR and the feedback coeffcents c, c 2,, c n. The denomnator n (3), denoted by n c n c c P =... ) ( 2 2 Is referred to as the characterstc polynomal of the sequence [a m ] and of the LFSR. For an n-stage LFSR, c n =. Note that P () s only a functon of the feedback coeffcents. If we set a = a 2= = a -n =0, and a n =, then (3) reduces to ) ( ) ( P G = Thus the characterstc polynomal along wth the ntal state characterzes the cyclc nature of an LFSR and hence characterzes the output sequence. So for a = a 2= = a -n =0, and a n =, then functon G () s follow: m m a m P G = = = 0 ) ( ) ( (4) 3.3 PERIODICITY OF LFSRs As t was told before an LFSR goes through a cyclc or perodc sequence of states and that the output produced s also perodc. The mamum length of ths perod s 2 n-, where n s the number of stages. In ths secton we consder propertes related to the perod of an LFSR. Most results wll be presented wthout proof.

19 If the ntal state of an LFSR s a = a 2= = a -n =0, and a n =, then the LFSR sequence [a m ] s perodc wth a perod that s the smallest nteger k for whch P () dvdes (- k ). Mamum-length sequence s the sequence generated by an n-stage LFSR has perod (2 n -) Prmtve polynomal s the characterstc polynomal assocated wth a mamumlength sequence. An rreducble polynomal s one that cannot be factored, because t s not dvsble by any other polynomal other than and tself. An rreducble polynomal P () of degree n satsfes the followng two condtons:. For n 2, P () has an odd number of terms ncludng the term. 2. For n 4, P () must dvde (evenly) nto (+ k ), where k= (2 n ). An rreducble polynomal s prmtve f the smallest postve nteger k that allows the polynomal to dvde evenly nto (+ k ) occurs for k=(2 n ), where n s the degree of the polynomal. The number of prmtve polynomals for n-stage LFSR s gven by the net formula where λ 2 (n)=φ(2 n -)/n Φ ( n) = n p n p and p s taken over all prmes that dvde n. Table 3 shows some values of λ 2 (n). N λ 2 (n) Table 3. Number of prmtve polynomals of degree n 3.4 CHARACTERISTICS OF MAXIMUM LENGTH SEQUENCES Sequences generated by LFSRs that are assocated wth a prmtve polynomal are called pseudorandom sequences, snce they have many propertes lke those of random 20

20 sequences. However, snce they are perodc and determnstc, they are pseudorandom, not random. Some of these propertes are lsted net. In the followng, any strng of (2 n ) consecutve outputs s referred to as an m- sequence. Property. The number of s n an m-sequence dffers from the number of 0s by one. Property 2. An m-sequence produces an equal number of runs of s and 0s. Property 3. In every m-sequence, one half the runs have length, one fourth have length 2, one eghth have length 3, and so forth, as long as the fractons result n ntegral numbers of runs. These propertes of randomness make feasble the use of LFSRs as test sequence generators n BIST crcutry. 3.5 LFSRs USED AS SIGNATURE ANALYZERS Sgnature analyss s a compresson technque based on the concept of cyclc redundancy checkng (CRC). In the smplest form of the scheme shown below, the sgnature generator conssts of a sngle-nput LFSR. The sgnature s the contents of ths regster after the last nput bt has been sampled. Fgure 0 llustrates ths concept. G() c = c c D Q Fgure 0. A type 2 LFSR used as a sgnature analyzer It s possble, that we get a sgnature of faulty crcut same as the normally functonng one, ths effect called errors maskng. The proporton of error streams that mask to the correct sgnature S (R 0 ) s ndependent of actual sgnature. For a test bt stream of length m, there are 2 m possble response streams, one of whch s correct. The number of bt streams that produce a specfc sgnature s 2 2 m n = 2 m n where the LFSR conssts of n stages and the all-zero state s now possble because of the estence of an eternal nput. For a partcular fault-free response, there are (2 m-n ) erroneous bt streams that wll produce the same sgnature. Snce there are a total of (2 m - ) possble erroneous response streams, the proporton of maskng error stream s 2

21 where, the appromaton holds for m>>n P SA m n 2 ( M m, n) = 2 m 2 If all possble error streams are equally lkely, whch s rarely the case, then P SA ( M m, n) s probablty that an ncorrect response wll go undetected,.e., the probablty of no maskng (-2 -n ). Ths s somewhat strange result snce t s only a functon of the length of the LFSR and not of the feedback network. Increasng the regster length by one stage reduces the maskng probablty by a factor of 2. Note that because of the feedback network, all sngle- bt errors are detectable. However, there s no drect correlaton between faults and error maskng. Thus a 6-bt sgnature analyzer may detect 00(-2-6 )= percent of the erroneous responses but not necessarly ths same percentage of faults. Sgnature analyss s the most popular method employed for test data compresson because t usually produces the smallest degree of maskng. n 3.6 SHIFT REGISTER POLYNOMIAL DIVISION The theory behnd the use of an LFSR for sgnature analyss s based on the concept of polynomal dvson, where the remander left n the regster after completon of the test process corresponds to the fnal sgnature. Consder to the type 2(nternal-XOR) LFSR shown n Fgure 0. The nput sequence [a m ] can be represented by the polynomal G () and the output sequence by Q () The hghest degree of the polynomals G () and Q () corresponds, respectvely, to the frst nput bt to enter LFSR and the frst output bt produced n clock perods later, where n s the degree of the LFSR. If the ntal state of the LFSR s all zeros, let the fnal state of the LFSR be represented by the polynomal R (). Then t can be shown that these polynomals are related by the equaton G( ) = Q( ) + P ( ) R( ) P ( ) where P*() s the recprocal characterstc polynomal of the LFSR. The recprocal characterstc polynomal s used because a m corresponds to the frst bt of the nput stream rather than the last bt. Type (eternal-xor) LFSRs also carry out polynomal dvson and produce the correct quotent. However, the contents of the LFSR are not the remander as s for the type 2 LFSRs. But t can be shown that all nput sequences, whch are equal to each other modulo P (), produce the same remander. 3.7 ERROR POLYNOMIAL AND MASKING Let E() be an error polynomal, where each non-zero coeffcent represents an error occurrng n the correspondng bt poston. As an eample, let the correct response be R 0 =0 and the erroneous response be R ()=0. Then the dfference or error polynomal s 000. Thus G 0 ()= , G ()= , and 22

22 E()= 3 +. Clearly G ()= G () +E ()(modulo 2). Snce G ()=Q () P* () + R (), an undetectable response sequence s one that satsfes the equaton G ( ) = G( ) + E( ) = Q ( ) P ( ) + R( ) G () and G () produce the same remander. From ths observaton we obtan the followng well-known result from algebrac codng theory. Let R () be the sgnature generated for an nput G () usng the characterstc polynomal P () as a dvsor n a LFSR. For an error polynomal E (), G () G ()=G ()+E () have the same sgnature R () f and only f E () s a multple of P (). Thus both type and type 2 LFSRs can be used to generate the sgnature R (). Henceforth, the fnal contents of the LFSR wll be referred to as the sgnature, because sometmes, dependng on the ntal state and polynomal P (), the fnal state does not correspond to the remander of G ()/P (). For an nput data stream of length m, f all possble error patterns are equally lkely, then the probablty that an n-bt sgnature generator wll not detect an error s whch, for m>>n, approaches 2 -n. P ( M ) = m 2 2 n m Ths result follows drectly from the prevous theorem because P () has ( 2 m n ) nonzero multples of degree less than m. It also corresponds to the same result gven earler but based on a dfferent argument. Note that ths result s ndependent of the polynomal P (). Ths ncludes P ()= n, whch has no feedback, t s just a shft regster. For ths case, the sgnature s just the last n bts of the data stream. In fact one can use the frst n bts and truncate the rest of test sequence and obtan the same results. These strange conclusons follow from the assumpton that all error patterns are equally lkely. But n ths case long test sequences would not be necessary. To see why ths assumpton s done, consder a mnmal-length test sequence of length m for a combnatonal crcut. Clearly the -th test vector t detects some fault f not detected by t j, j =, 2,, -. Thus f f s present n the crcut, the error pattern s of the form 00 0, the frst - bts must be 0. Several other arguments can be made to show that all error patterns are not equally lkely. An LFSR sgnature analyzer based on any polynomal wth two or more non-zero coeffcents detects all sngle-bt errors. Assume P () has two or more non-zero coeffcents. Then all non-zero multples of P() must have at least two non-zero coeffcents. Hence an error pattern wth only one non-zero coeffcent cannot be multple of P () and must be detectable. A (k, k) burst error s one where all erroneous bts are wthn k consecutve bt poston, and at most k bts are n error. If P () s of degree n and the coeffcents of 0 s, then all (k, k) burst errors are detected as long as n k. Rather than assumng that all error patterns are equally lkely, one can assume that the probablty that a response bt s n 23

23 error s p. Then for p=0,5 the probablty of maskng s 2 -n. For very small or very large values of p, the probablty of maskng approaches the value 2 n + (2 n )( 2 p ) n m( /(2 )) where m s the length of the test sequence. Epermental results also show that usng prmtve polynomals helps n reducng maskng effect. In concluson, the bound of 2 -n on error maskng s not too useful snce t s based on realstc assumptons. However, n general, sgnature analyss gves ecellent results. Results are senstve to P () and mprove as n ncreases. Open problems deal wth selectng the best characterstc polynomal P () to use, characterzng error patterns, correlatng fault coverage to P () and determnng the probablty of maskng. 3.8 MULTIPLE-INPUT SIGNATURE REGISTER Sgnature analyss can be etended to testng multple-output crcuts. Normally a sngle-output sgnature analyzer s not attached to every output because of the resultng hgh overhead. A sngle sgnature analyzer could be tme-multpleed, but that would requre repeatng the test sequence for each output, resultng n a potentally long test tme. The most common technque s to use a multple-nput sgnature regster (MISR), such as the one shown n Fgure. Here we assume that the CUT has n (or less) outputs. It s seen that ths crcut operates as n sngle-nput sgnature analyzer. For eample, by settng D =0 for all j, the crcut computes the sgnature of the data enterng on lne D j. The mathematcal theory assocated wth MISRs wll not be presented, but t follows as a drect etenson of the results presented prevously for Sngle Input Sgnature Regsters (SISR). An error pattern can be assocated wth each nput D. These error patterns are merged wthn LFSR. Agan, assumng all error patterns are equally lkely, the probablty that a MISR wll not detect an error s appromately 2 -n. D D2 D3 Dn D Q Cn Cn- Cn-2 C Fgure. Multple-nput sgnature regster 24

24 3.9 SELECTION OF THE POLYNOMIAL P (X) As stated prevously, a MISR havng n stages has a maskng probablty appromately equal to 2 -n for equally lkely error patterns long data streams. Also, ths result s ndependent of P (). Let the error bt assocated wth D at tme j be denoted by e j, where =, 2,..., n, and j =, 2,, m. Then the error polynomal assocated wth D s Then the effectve error polynomal s m E = ej j= n = j E ( ) = E assumng that the ntal state of the regster s all zeros. The error polynomal E () s masked f t s a multple of P (). So a comple-feedback LFSR structure s typcally used on the assumpton that t wll reduce the chances of maskng an error. When the characterstc polynomal s the product of the party generator polynomal g()= + and a prmtve polynomal of degree (n-), an n-stage MISR has the property that the party over all the bts n the nput streams equals the party of the fnal sgnature. Hence maskng wll not occur for an odd number of errors. 3.0 INCREASING THE EFFECTIVENESS OF SIGNATURE ANALYSIS There are several ways to decrease the probablty of maskng. Based on the theory presented, the probablty of maskng can be reduced be ncreasng the length of the LFSR. Also a test can be repeated usng a dfferent feedback polynomal. When testng combnatonal crcuts, a test can be repeated after frst changng the order of the test vectors, thus producng a dfferent error polynomal. Ths technque can be also used for sequental crcuts, but now the fault-free sgnature also changes. Maskng occurs because once an error ests wthn an LFSR, t can be canceled by new errors occurrng on the nputs. Inspectng the contents of the sgnature analyzer several tmes durng the testng process decreases the chance that a faulty crcut wll go undetected. Ths technque s equvalent to perodcally samplng the output of the sgnature analyzer. The degree of storage compresson s a functon of how often the output s sampled. [] 3. CONCLUDING LFSRs THEORY Usng lnear feedback regsters for test pattern generatng and as a response compactors s wdely used snce they are easy to mplement, they can be used for feld test and selftestng, and can provde hgh fault coverage, though the correlaton between error coverage and fault coverage s hard to predct. Sgnature analyss s wdely used because t provdes ecellent fault and error coverage, though fault coverage must be determned usng a fault smulator or a statcal fault 25

25 smulator. Unlke the other technques, several means est for mprovng the coverage wthout changng the test, such as by changng the characterstc polynomal or ncreasng the test length of the regster. 26

26 4 BUILT-IN SELF-TEST (BIST) 4. INTRODUCTION TO BIST CONCEPTS The man dea of Bult-n self-test (BIST) s the capablty of a crcut (chp, board, or system) to test tself. BIST technques can be classfed nto two categores, namely on-lne BIST, whch ncludes concurrent and no concurrent technques, and off-lne BIST, whch nclude functonal and structural approaches (Fgure 2). Forms of testng Off-lne On-lne Functonal Structural Concurrent Non-concurrent Fgure 2. Forms of testng In on-lne BIST, testng occurs durng normal functonal operatng condtons;.e., the crcut under test (CUT) s not placed nto a test mode where normal functonal operaton s locked out. Concurrent on-lne BIST s a form of testng that occurs smultaneously wth normal functonal operaton. In no concurrent on-lne BIST, testng s carred out whle a system s n an dle state. Ths s often accomplshed by eecutng dagnostc software routnes or dagnostc frmware routnes. The test process can be nterrupted at any tme so that normal operaton can resume. Off-lne BIST deals wth testng a system when t s not carryng out ts normal functons. Systems, boards, and chps can be tested n ths mode. Ths form of testng s also applcable at the manufacturng, feld and operatonal levels. Often Off-lne testng s carred out usng on-chp or on-board test-pattern generators (TPGs) and output response analyzers (ORAs) or mcrodagnostc routnes. Off-lne testng does not detect errors n real tme,.e., when they frst occur, as s possble wth many on-lne concurrent BIST technques. Functonal off-lne BIST deals wth the eecuton of a test based on a functonal descrpton of the CUT and often employs a functonal, or hgh-level, fault model. Normally such a test s mplemented as dagnostc software or frmware. Structural off-lne BIST deals wth the eecuton of a test based on the structure of the CUT. An eplct structural fault model may be used. Fault coverage s based on detectng structural faults. Usually tests are generated and responses are compressed usng some form of an LFSR. The theory of LFSR wll be descrbed later. In the net secton varous forms of testng and related TPGs wll be descrbed. 27

27 4.2 TEST-PATTERN GENERATION FOR BIST 4.2. EXHAUSTIVE TESTING Ehaustve testng deals wth the testng of an n-nput combnatonal crcut where all 2 n nputs are appled. A bnary counter can be used as TPG. If a mamum-length autonomous LFSR s used, ts desgn can be modfed to nclude the all-zero state. Ehaustve testng guarantees that all the detectable faults that do not produce sequental behavor wll be detected. Dependng on the clock rate, ths approach s usually not feasble f n s larger than about 22. Other technques to be descrbed are more practcal when n s large. The concept of ehaustve testng s not generally applcable to sequental crcuts PSEUDORANDOM TESTING Pseudorandom testng deals wth testng a crcut wth test patterns that has many characterstcs of random patterns but where the patterns are generated determnstcally and hence are repeatable. Pseudorandom patterns can be generated wth or wthout replacement. Generaton wth replacement mples that each pattern s unque. Not all 2 n test patterns need be generated. Pseudorandom test patterns wthout replacement can be generated by an autonomous LFSR. Pseudorandom testng s applcable to both combnatonal and sequentonal crcuts. Fault coverage can be determned by fault smulaton. The test length s selected to acheve an acceptable level of fault coverage. Unfortunately, some crcuts contan random-pattern-resstant faults and thus requre long test length to nsure hgh fault coverage PSEUDOEXHAUSTIVE TESTING Pseudoehaustve testng acheves many of the benefts of ehaustve testng but usually requres far fewer test patterns. It reles on varous forms of crcut segmentaton and attempts to test each segment ehaustvely. There are several forms of segmentaton, a few of whch are lsted below:. Logcal segmentaton Cone segmentaton Senstzed path segmentaton 2. Physcal segmentaton 4.3 CIRCULAR SELF-TEST PATH (CSTP) The crcular self test path (CSTP) s ntended for regster- based BIST archtecture, where self-test cells are grouped nto regsters, CSTP employs a self-test desgn shown n Fgure 3 and partal self-test, where not all regsters must consst of self-test cells. Some necessary features of ths archtecture are all nputs and outputs must be assocated wth boundary scan cells and all storage cells must be ntalzable to a known state before testng. 28

28 D j S j- 0 m u Z D Q R Qj Sj N/T N/T Z Mode 0 D j System D j S j- Test Fgure 3. Storage cell desgn for use n CSTP BIST archtectures. R PIs R 2 PIs C C 2 R 5 R 3 C 5 C 3 R 6 R 4 C 6 C 4 R 7 R 8 POs POs R -Self-test path R -conventonal regster Fgure 4. A desgn employng the crcular self-test path archtecture 29

29 Consder the crcut shown n Fgure 4. The regsters R, R 2, R 3, R 7 and R 8 are part of the crcular self-test path. Note that the self-test cells form a crcular path. If ths crcular path contans m cells, then t corresponds to a MISR havng the characterstc polynomal (+ m ). Regsters R 4, R 5 and R 6 need not to be n the self-test path, nor do they requre reset or set lnes, snce they can be ntalzed based on the state of the rest of the crcut. That s, once R, R 2 and R 3 are ntalzed, f R 4, R 5, and R 6 are ssued two system clocks, then they too wll be ntalzed to known state The same cannot be sad of R 3 because of the feedback loop formed by the path R 3 -C 3 - R 6 -C 6 -R 3. However, f R 3 has a reset lne, then t needs not to be n the self-test path. Increasng the number of cells n the self-test path ncreases both the BIST hardware overhead and the fault coverage for a fed test length. The test process requres three phases.. Intalzaton: All regsters are placed nto a known state 2. Testng of CUT: The crcut s run n the test mode; regsters that are not n the self-test path operate n ther normal mode. 3. Response evaluaton. Durng phase 2 the self-test path operates as both a random-pattern generator and response compactor. Durng phase 3 the crcut s agan run n the test mode. But now the sequences of outputs from one or more self-test cells are compared wth precomputed fault-free values. Ths comparson can be done ether on-chp or off-chp. Fgure 5 shows the general form of a crcular self-test path desgn. The crcular path corresponds to an LFSR havng the prmtve polynomal p ()=+ m. In ths secton some theoretcal and epermental results about certan performance aspects of ths class of desgn wll be brefly presented. These results are applcable to many desgns where a MISR s used as PRPG. Z X Z 2 X2 C Z m Fgure 5. General form of a crcular self-test path desgn Let z (t) and (t) be the nput and output, respectvely, to the th cell n crcular self-test path. Then assume that the sequences of bts appled to each cell n the path are ndependent and that each sequence s characterzed by a constant (n tme) probablty of a, for nput z (t), p =Prob {z (t)=}, t=, 2,. If there ests an nput to the crcular path, z, such that 0< p <, then ndependent of the ntal state of the path, lm prob{ ( t) = } = 0. 5, j=, 2,, m. t j 30

30 Thus f response of the crcut to the ntal state of the crcular path s nether the allzeros nor the all-ones pattern, then some tme after ntalzaton the probablty of a at any bt poston of the crcular path s close to 0,5. The number of clock cycles requred for (t) to converge to 0,5 s a functon of the length of the crcular path, and s usually small compared to the number of test patterns normally appled to the crcut. The pattern coverage (also known as the state coverage) s denoted by C n,r and s defned as the fracton of all 2 n bnary patterns occurrng durng r clock cycles of the self-testng process at n arbtrary selected outputs of the crcular path. These outputs can be the n nputs to a block of logc C. As the length of the crcular path ncreases, the mpact of the value of p on the pattern coverage decreases. The crcular path provdes a block C wth an almost ehaustve test for test lengths a few tmes longer than an ehaustve test. When the number of clock cycles assocated wth a test eceeds the length of the crcular path, the mpact of the locaton of the n cells feedng the block C on the pattern coverage s neglgble. For long test tmes, the pattern coverage assocated wth n cells s almost ndependent of the length of the path. 4.4 BUILT-IN LOGIC BLOCK OBSERVATION (BILBO) One major problem of the most BIST desgns s that they deal wth an unpartoned verson of a CUT, where all prmary nputs are grouped together nto one set, all prmary outputs nto a second set, and all storage cells nto a thrd set. These sets are then assocated wth PRPGs and MISRs. Snce the number of cells n these regsters s usually large, t s not feasble to consder ehaustve or pseudoehaustve test technques. For eample, a chp can easly have over 00 nputs and several hundred storage cells. To crcumvent ths problem one can attempt to cluster storage cells nto groups, commonly called regsters. In general these groups correspond to the functonal regsters found n many desgns, such as the program counter and the nstructon regster. Some BIST archtectures take advantage of the regster aspects of many desgns to acheve a more effectve test methodology. One such archtecture employs bult-n logc-block observaton (BILBO) regsters, shown n Fgure 6(a). In ths regster desgn the nverted output Q of a storage cell s connected va a NOR and a XOR gate by the data nput of the net cell. A BILBO regster operates n one of four modes, as specfed by the control nputs B and B 2. When B = B 2 =, the BILBO regster operates n ts normal parallel load mode (see Fgure 6 (b)). When B = B 2 =0, t operates as a shft regster wth scan nput S (see Fgure 6(c)). Note that the data s complemented as t enters the scan regster. When B =0 and B 2 =, all storage cells are reset. When B = and B 2 =0, the BILBO regster s confgured as an LFSR (see Fgure 6(d)), or more accurately the regster operates as a MISR. If the Z s are the outputs of a CUT, then the regster compresses the response to form a sgnature. If the nputs Z, Z 2,, Z n are held at a constant value of 0, and the 3

31 ntal value of the regster s not all-zeros, then the LFSR operates as a pseudorandompattern generator. A smple form of a BILBO BIST archtecture conssts of parttonng a crcut nto a set of regsters and blocks of combnatonal logc, where the normal regsters are replaced by BILBO regsters. In addton, the nputs to a block of logc C are drven by a BILBO regster R, and the outputs of C drve another BILBO regster R j. C C 2 Scan-n (a) Z Z 2 Zn D Q Q Q 2 (b) S D Q S0 (c) Qn 32

32 Z Z2 Z3 Zn Q Q2 Qn- Qn (d) Fgure 6. n-bt BILBO regster R R C C R2 R2 C2 (b) (a) Fgure 7. BIST desgns wth BILBO regsters Consder the crcut shown n Fgure 7(a), where the regsters are all BILBOs. To test C, frst R and R 2 are seeded, and then R s put nto the PRPG mode and R 2 nto the MISR mode. Assume the nputs of R are held at the value 0. The crcut s then run n ths mode for N clock cycles. If the number of nputs of C s not too large, C can even be tested ehaustvely, ecept for the all-zero pattern. At the end of ths test process, called a test sesson, the contents of R 2 can be scanned out and the sgnature checked. Smlarly confgurng R to be a MISR and R2 to be a PRPG can test C2. Thus the crcut s tested n two test sessons. Fgure 7(b) shows a dfferent type of crcut confguraton, one havng a self-loop around the R 2 BILBO regster. Ths desgn does not conform to a normal BILBO archtecture. To test C, R must be n the PRPG mode. Ths s not possble for the desgn shown n Fgure 6(a). What can be done s to place R 2 n the MISR mode. Now ts outputs are essentally random vectors that can be used as test data to C. One feature of ths scheme s that errors n the MISR produce erroneous test patterns that are 33

33 appled to C, whch s tend to produce more errors n R 2. The bad aspect of ths approach s that there may est faults that are never detected. Ths could occur, for eample, f the nput data to C never propagate the effect of a fault to the output of C. BUS R Rn C Cn R2 Rn Fgure 8. Bus-orented BIST archtecture The stuaton can be rectfed by usng a concurrent bult-n logc-block observaton (CBILBO) regster. Ths regster operates smultaneously as a MISR and a PRPG. Recall that when a BILBO regster s n the PRPG mode, ts nputs need to be held at some constant value. Ths can be acheved n several ways. Often the BILBO test methodology s appled to a modular and bus-orented system n whch functonal modules, such as ALUs, RAMs, ROMs, are connected va a regster to a bus (see Fgure 8). By dsablng all bus drvers and usng pull-up or pull-down crcutry, the regster nputs can be held n a constant state. PIs C BILBO C 2 BILBO Cn POs Fgure 9. Ppelne-orented BILBO archtecture However, some archtecture has a ppelne structure shown as n Fgure 9. To deactvate the nputs to a BILBO regster durng ts PRPG mode, a modfed BILBO regster desgn havng three control states, and one can be used to specfy the MISR mode and another the PRPG mode. 34

34 One aspect that dfferentates the BILBO archtecture from the other BIST archtectures s the parttonng of storage cells to form regsters and the parttonng of the combnatonal logc nto blocks of logc. Other types of regsters, such as constantweght counters or more comple forms of LFSRs can replace the BILBO regsters.[] 35

35 5 FUNCTIONAL TESTING In ths secton wll be descrbed functonal testng methods that are based on functonal model of the system. 5. INTRODUCTION TO FUNCTIONAL TESTING A functonal model reflects the functonal specfcatons of the system and, to a great etent, s ndependent of ts mplementaton. Therefore functonal tests derved from a functonal model can be used only to check whether physcal faults are present n the manufactured system, but also as desgn verfcaton tests for checkng that the mplementaton s free of desgn errors. The objectve of functonal testng s to valdate the correct operaton of a system wth respect to ts functonal specfcatons. Ths can be approached n two dfferent ways. One approach assumes specfc functonal fault models and tres to generate tests that detect the faults defned by these models. By contrast, the other approach s not concerned wth the possble types of faulty behavor and tres to derve tests based only on the specfed fault-free behavor. Between these two there s a thrd approach that defnes an mplct fault model, whch assumes that almost any fault can occur. Functonal tests detectng almost any fault are sad to be ehaustve, as they must completely eercse the fault-free behavor. Because of the length of the resultng tests, ehaustve testng can be appled n practce only to small crcuts. By usng some knowledge about the structure of the crcut and by slghtly narrowng the unverse of faults are guaranteed to be detected, we can obtan pseudoehaustve tests that can be sgnfcantly shorter than the ehaustve ones. 5.2 EXHAUSTIVE AND PSEUDOEXHAUSTIVE TESTING The Unversal Fault Model Ehaustve tests detect all the faults defned by the unversal fault model. Ths mplct fault model assumes that any fault s possble, ecept those that ncrease the number of states n a crcut. For a combnatonal crcut N realzng the functon Z(), the unversal fault model accounts for any fault f that changes the functon to Z f ().The only faults not ncluded n ths model are those that transform N nto a sequental crcut. For a sequental crcut, the unversal fault model accounts for any fault that changes the state table wthout creatng new states. To test all the faults defned by the unversal fault model n a combnatonal crcut wth n prmary nputs, we need to apply 2 n possble nput vectors. The eponental growth of the requred number of vectors lmts the practcal applcablty of ths ehaustve testng method only to crcut wth less than 20 prmary nputs. Further pseudoehausve testng methods wll be presented PARTIAL-DEPENDENCE CIRCUITS Let O, O 2,, O m be the prmary outputs of a crcut wth n prmary nputs, and let n be the number of prmary nputs feedng O. A crcut n whch no prmary outputs depend 36

36 on all the prmary nputs, s sad to be a partal-dependence crcut. For such crcut, n pseudoehaustve testng conssts n applyng all 2 combnatons to the n nputs feedng every prmary output O PARTITIONING TECHNIQUES The pseudoehaustve testng technques descrbed n the prevous secton are not applcable to total-dependence crcuts, n whch at least one prmary output depends on all prmary nputs. Even for a partal-dependence crcut, the sze of a pseudoehaustve test set may stll be too large to be acceptable n practce. In such cases, pseudoehaustve testng can be acheved by parttonng technques. The prncple of s to partton the crcut nto segments such that the number of nputs of every segment s sgnfcantly smaller than the number of prmary nputs of the crcut. Then the segments are ehaustvely tested. The man problem wth ths technque s that, n general, the nputs of a segment are not prmary nputs and ts outputs are not prmary outputs. Then we need a means to control the segment nputs from the prmary nputs and to observe ts outputs at the prmary outputs. One way to acheve ths, referred to as senstzed parttonng, s based on senstzng path from prmary nputs to the segment nputs and from the segment outputs to prmary outputs. 5.3 FUNCTIONAL BIST Functonal BIST s a promsng soluton for self-testng comple dgtal systems at reduced costs n terms of area and performance degradaton. To ncrease the functonalty, acheve hgher performance, and decrease cost, desgners are actually movng quckly towards very deep sub-mcron technologes. From one hand, the vast avalablty of gates permts the ntegraton of a varety of memores, processors and analog unts on a sngle chp. On the other hand tradtonal testng approaches based on an eternal ATE become more and more unfeasble. The number of eternally accessble I/O pns countng up to several hundreds strongly lmts the controllablty and observablty of embedded cores. In tradtonal BIST archtectures, LFSRs and multfunctonal regsters, lke BILBO, mostly perform test pattern generaton. The functonal BIST strategy, eplots functonalty s and modules embedded nto the system tself for test pattern generaton. In Fgure 20 both modules M and M j are part of the system logc. And durng testng M s controlled n such way that outputs serve as a test patterns for module M j. Typcally M s a sequental crcut used as test pattern generator (STPG) for a gven unt under test (UUT), n ths case M j. 37

37 Fgure 20. Functonal BIST Further wll be descrbed the unversal method to control and ntalze sequental structures so that they work as an STPG for a gven unt under test. The sequence of values appearng on the STPG s a functon of the trplet (σ, δ, τ) as well as of the logc functon embedded nto the block. Ths s shown n Fgure 2. Frst the state regster of the STPG s ntalzed wth ntal state (δ) and ts prmary nputs are fed at an nput value (σ), then the STPG s let evolve for a certan number of clock cycles (τ). Intal state and the nput value are often collectvely referred to as seed of the STPG. Set of trplets Reseedng process Input regster PIs Logc functon BIST controller Fgure 2. The STPG State regster stpg POs UUT For sake of effcency and fleblty, the STPG can be perodcally reseeded, stoppng ts evaluaton and restartng t wth a new trple (σ, δ, τ) untl the target fault coverage s reached. In such a case, the global test length s a functon of the number of reseedng: 0 τ n When adoptng functonal approach, the desgner can trade-off between: Mamzng the fault coverage. Mnmzng the test tmes, global test length Mnmzng the complety of the BIST controller, by selectng a proper common τ. 38

38 6 APPLET DESIGN AND TEST OF DIGITAL SYSTEMS ON RT- LEVEL DESCRIPTION The applet s ntroduced as the teachng system wch shows how to provde dgtal desgn on RT-level and also shows a varety of dfferent modern testng technques ncludng functonal and detemnstc testng, a number of BIST solutons. Overall descrpton of the teachng system RT-Level teachng system llustrates many problems related to both RT-level control ntensve dgtal desgn and test. Ths gves a possblty to teach all of them n a consecutve teratve approach. The range of problems ncludes: Desgn of datapath and a control part (mcroprogram) on RT- level Investgaton of tradeoffs between speed & HW cost n the system RT- level smulaton and valdaton gate-level determnstc test generaton and functonal testng fault smulaton logc BIST, crcular BIST, functonal BIST, etc. desgn for testablty The teachng system nterface conssts of the followng major parts: Schematc Vew - panel provdes the schematc representaton of a desgn. Ths panel allows user to defne or change some propertes of datapath of the desgn. Some components (functonal unts) can be enabled /dsabled or ther functonalty can be changed. In the step-by-step smulaton mode the results of the smulaton are vsually demonstrated on the Schematc Vew after each step of the smulaton. Mcroprogram tab-panel s used to defne control part of the system. Durng the smulaton ths panel shows, whch part of the mcroprogram, s currently eecuted. Smulaton tab-panel and Test tab-panel are used to smulate and test desgn correspondngly. The smulaton can be carred out n dfferent ways: ) Step-by-step smulaton mode. In ths case each row of the mcroprogram s eecuted separately and all the results of ths eecuton (ncludng state of regsters and functonal blocks, nputs and outputs, status sgnals, etc) can be vewed drectly on Schematcs Vew sub-panel. Ths mode of smulaton s useful for llustratng how the desgn works or for debuggng. 2) Test mode: Ths mode s used to test the desgn repeatedly wth some set of nput data. User flls n the Test data table n the Test tab-panel wth the data that wll be used n testng. Then the desgn smulaton can be eecuted for a partcular row of test table or for all the rows at once. The results of the smulaton or test are placed to Smulaton Results tab-panel. Smulaton Results tab-panel reflects the results of fault-free smulaton. Fault smulaton module provdes fault smulaton for the datapath and ts unts. Global Test Panel s used to provde fault coverage nformaton as for the whole datapath as for each sngle unt under test. Local Test Panel provdes means for manual local test patterns generaton for a selected unt of datapath. It also provdes the fault coverage for each unt as well as for the datapath as whole. 39

39 Test Mcroprogram allows change the specal test mcroprogram, whch s used n Determnstc test, Logcal and Crcular BIST modes. Fgure 22. The nterface of the teachng system The teachng system has a fleble desgn, wth several mplemented RT-level system models (mplemented RT model wll be descrbed n secton 9), the latter allow developng dfferent algorthms wth dfferent HW cost and speed. The teachng system has a bult-n etendable collecton of eamples mplementng dfferent algorthms (multplcaton, subtracton, etc). They help users to understand prncples the system operaton. For connectng the system to other applcatons as well as for provdng users wth a possblty to save the results of ther work for further use, the applet has a data mport/eport capablty. [4] Datapath descrpton MUX m j: B j = R =,,n Regster number; j = 0,,2,4 Bus number where B 0 s Data OUT Bus, B s the Bus to F etc. DMUX d j: R j = B = 0,3,4 Bus number where B 0 s Data IN Bus, B 3 s the Bus from F3 etc. j =,,n Regster number F (F3) f j (f 3j) unary mcrooperatons lke: varous shftngs, nvertng, countng (+, -) etc. F2 f 2j varous bnary mcrooperatons (wth 2 operands) F4 f 4j varous unary and bnary mcrooperatons (wth 2 operands); there s a overlay between functons of F4 and the ones of F, F2 and F3 to allow a parallelzaton of the gven algorthm Fgure 23. Descrpton of datapath functonalty 40

40 Each functonal unt (FU) of the datapath F Fn contans a number of mcrooperatons (functons: unary and bnary), whch are labeled by correspondng control sgnals actvatng chosen functon. The descrpton of the datapath functonalty n format control sgnal: mcrooperaton s presented n Fgure 23. The user can select one or more mcrooperatons for each unt of datapath when mplementng hs own algorthm (lke subtracton, multplcaton etc). Each mcrooperaton has a gate-level mplementaton, and the number of gates determnes ts cost. All selected mcrooperatons determne the fnal HW cost of the system. Dfferent archtectures of the datapath can be chosen for mplementaton of the gven algorthm, so the user can compare them consderng ether the cost or tmng requrements. For eample, the user can use only one functonal unt, n order to carry out a sngle mcrooperaton n one clock cycle. In ths case the hardware cost s saved but the speed s low. There s another possblty, n whch all functonal unts can be used, n a parallel or sequental mode, n order to carry out mamum number of mcrooperatons durng a sngle clock cycle, f the algorthm allows to. In ths case the speed s hgher than n the prevous case. The speed (the number of clock cycles) of the algorthm s measured by smulaton. In ts turn the smulaton s supported by an RT-level model of the system as a whole and by gate-level models of each mcrooperaton n each FU. Control part The control part s a mcroprogrammed controller, whch mplements Mealy FSM (Fnal State Machne). The controller conssts of a mcroprogram table and an nterpreter. The mcroprogram s developed by the user to realze a gven algorthm based on the selected resources of the datapath. The user flls n the rows of mcroprogram table, whch contan nformaton about the address of the current and the net mcronstructon, MUX and DMUX confguratons, Data IN values, selecton of functons n FUs (F to Fn) at each mcronstructon, and status sgnal confguraton. In Fgure 24 an eample of subtracton algorthm of two operands A and B s presented. The result of subtracton s stored n REG3 and fed out to the data output. Fgure 24. Subtracton algorthm mcroprogram The frst two columns of the mcroprogram table represent the address of current mcronstructon and the address of the net mcronstructon correspondngly. The current mcronstructon can be splt nto several rows n case f ts operaton depends on the set of condtons C. Then the only proper row wll be selected. Columns F(n)...,Fn(n) correspond to MUX and ndcate whch regster (REG REGn) wll be multpleed nto whch functonal unt (F,.., Fn). Regsters where the nput data from 4

41 Data IN (column Input ) wll be wrtten are specfed n column IN. The nput data are the operands of the mplemented algorthm. Columns F to Fn stand for a certan mcrooperaton selected for a correspondng functonal unt (F to Fn) n a certan clock cycle. The DMUX secton s specfed n columns F (out),...,fn(out). It shows to whch regster the data from functonal unts Fn and Fn n wll be wrtten. Column OUT ndcates the regster, whch wll be redrected to Data OUT. The last columns (C,, Cn) stand for condtons where the followng values must be specfed: 0,, X (don t care). The RT-level smulaton s carred out at the hgher level by usng correspondng to functonal unts Java subroutnes, whch are actvated accordng to condton values by the control sgnals n the order gven n the mcroprogram table. The smulaton data s stored n the Smulaton Results subpanel, presented n Fgure 25 below. Fgure 25. The Smulaton Result panel Column Test Nr. defnes the number of data group from the Test Data Table. The clock number Clock s specfed n the net column. The smulaton data s wrtten n all other cells of the Smulaton Results table at each clock cycle. Ths data reflects the states of all the regsters, outputs of all the functonal blocks, data nput and output of the devce, current states at each clock cycle and condton sgnals. The smulaton data can be used by the student as a debuggng nfo as well as for the mprovng the effcency: the speed or the cost of the system. Testng The toolkt of the modern desgn and test engneer contans qute a few methods of testng of a SoC desgn. All of them have come from the earler tmes and have been adopted for the new paradgm. The RT teachng system shows a varety of dfferent modern testng technques ncludng functonal and determnstc testng, a number of BIST solutons. Pror to enterng the test mode, the system under test must be desgned and verfed. The user can do t hmself or use one of prepared eamples. When the test mode s selected, the mcroprogram and the structure of the datapath are frozen and cannot be modfed anymore. At the same tme the user selects target mcrooperatons of the data path for test generaton and fault smulaton. The fault smulaton nformaton s reflected (dependng on a mode selected) at the Global Test Panel for the whole system and at the Local Test Panel for a sngle selected unt. In the followng we descrbe the test modes n detal. 42

42 Functonal Testng In ths mode the cheapest test technque s nvestgated, whch does not requre desgnng specal test programs and embeddng of specal test structures nto the system. The same unmodfed mcroprogram and datapath are used nstead.the requred level of fault coverage must be acheved then only by a smart selecton of nput data. The fault smulaton nformaton s presented at the Global Test Panel. The nput operands (A, B, C, D) are specfed frst. The same mcroprogram s used then repeatedly for fault smulaton for all the nput data. The fault coverage s calculated for each selected FU and for the whole system as well. The cumulatve fault coverage (column total ) for each nput vector s also provded n the Global Fault Coverage table, shown n Fgure 26 presented below. Fgure 26. Global Fault coverage table. Determnstc Test Determnstc Test mode s amed at a gate-level test generaton and fault smulaton for each selected FU separately, see Fgure 27. They are consdered by the user n seres and test vectors are generated. The smulaton results are provded n the fault table at the Local Test Panel. For each vector the fault coverage (FC (vec)) s calculated and the nformaton on tested nodes s gven. The cumulatve fault coverage (FC) s also shown for each smulaton step. The herarchcal RT-level fault smulaton s also appled n order to evaluate the global fault coverage of those vectors for the datapath as a whole. For ths purposes a test program s composed for each selected FU. The smulaton data s reflected n the Global Test Panel n the same way as t s done n the Functonal Test mode. In order to help the user generatng gate-level test vectors, the gate-level schematc of currently selected FU s dsplayed. The user selects a target fault and generates a test vector. After pressng the Smulate button ths vector s fault smulated at the gate level and the results (local fault coverage) are added nto the fault table. At the same tme, the same vector s sent to RT-level herarchcal fault smulator n order to fll n the Global Test Panel. The test mcroprogram, used for RT-level fault smulaton must provde a good access to the selected FU. A smple verson of such a program s generated automatcally. It can be used as a template by a student n order to develop a more sophstcated test program f needed. 43

43 BIST mode Fgure 27. Determnstc test pattern generaton n Local Test Panel RT teachng system allows to provde testng wth dfferent BIST solutons, whch are based on a scan-path technology (Fgure 28), where the nputs and outputs of the combnatonal blocks n datapath are drectly accessble by TPGs, SAs or TPG/SA (combned TPG and SA). CSTP BILBO TPG/SA TPG SA F F2 F3 F4 Fgure 28. Scan-path desgn Teachng system allows reconfguraton of nternal regsters n the BIST mode. Dependng on the chosen BIST method some of them can perform functons of TPG, SA or TPG/SA. If the Logc BIST (BILBO) method s to be evaluated, the TPG and SA functons must be separated and located n dfferent regsters. On the contrary, n Crcular BIST (CSTP) both TPG and SA are stuated n the same regster. In the both modes t s possble to confgure the TPG on-lne from the nteractve graphcal panel, see Fgure

44 Fgure 29. Interactve LFSR confguraton graphcal panel When the confguraton s completed, the gate-level and the herarchcal fault smulaton are performed and the results are dsplayed n the way smlar to the one used n Functonal and Determnstc test modes. There s another BIST mode, called Functonal BIST. Ths mode has very much n common to Functonal Testng. The only dfference between the two modes s that n the former one there s possblty to nsert SAs at any arbtrary pont wthn the data path. In ths way we ncrease the observablty of the system, snce each such SA s capable of collectng data at each clock compressng t nto an observable sgnature. 45