Research Article A Formal Model for Performance and Energy Evaluation of Embedded Systems

Transcription

1 Hndaw Publshng Corporaton EURASIP Journal on Embedded Systems Volume 2011, Artcle ID , 12 pages do: /2011/ Research Artcle A Formal Model for Performance and Energy Evaluaton of Embedded Systems Bruno Noguera, 1, 2 Paulo Macel, 1 Eduardo Tavares, 1 Ermeson Andrade, 1 Rcardo Massa, 1 Gustavo Callou, 1 and Rodolfo Ferraz 1 1 Informatcs Center, Federal Unversty of Pernambuco, Recfe, Brazl 2 Academc Unt of Garanhuns, Federal Rural Unversty of Pernambuco, Garanhuns, Brazl Correspondence should be addressed to Bruno Noguera, bcsn@cn.ufpe.br Receved 2 June 2010; Accepted 21 September 2010 Academc Edtor: Detmar Bruckner Copyrght 2011 Bruno Noguera et al. Ths s an open access artcle dstrbuted under the Creatve Commons Attrbuton Lcense, whch permts unrestrcted use, dstrbuton, and reproducton n any medum, provded the orgnal work s properly cted. Embedded systems desgners need to verfy ther desgn choces to fnd the proper platform and software that satsfy a gven set of requrements. In ths context, t s essental to adopt formal-based technques to evaluate the mpact of desgn choces on system requrements. To be useful, such technques must produce accurate results wth mnmal computaton tme. Ths paper proposes an approach based on Coloured Petr Nets for evaluatng embedded systems performance and energy consumpton. In partcular, ths work presents a method for specfyng and evaluatng the workload and the platform components, such as processors and shared or prvate memores. The method s appled to model sngle processor and multprocessor platforms. Expermental results demonstrate an average accuracy of 96% n comparson wth the respectve measures assessed from the real hardware platform. 1. Introducton The desgn of embedded systems usually must take nto account several nonfunctonal constrants, such as performance, sze, weght, cost, relablty, and durablty. The rapd growth of embedded systems n new applcaton domans ntroduces new restrctons, whch n turn rases new research and techncal challenges. One promnent research area s related to battery-operated devces, n whch energy consumpton plays an mportant role. The low-power desgn has grown n mportance wth the prolferaton of such devces. The man challenge s to reduce energy consumpton wthout jeopardzng the performance requrements. Modern embedded systems are composed of a set of nterconnected processng, communcaton, and storage elements. Very often, these elements are ntegrated nto a sngle crcut (System-on-Chp). Software (nstructons streams/workload) executng on the processng elements drves the behavor of the system. In contrast to a desktop system, whch executes a varety of workloads, normally embedded systems execute only one workload, repeatedly. The characterstcs of the workload and the processng elements dctate the usage of communcaton and storage elements. In turn, the characterstcs of the communcaton and storage elements nfluence the rate at whch the workload s executed. Therefore, energy consumpton and performance are a functon of the characterstcs of the workload and the archtectural elements, and thus, estmatng these metrcs s not an ordnary task. Gven the wde range of platform optons and software optmzatons, desgners need to verfy ther desgn choces to fnd the proper platform and software that satsfy a gven set of requrements. Measurement of the actual performance and energy consumpton characterstcs on real hardware s often not feasble, snce ths would requre the constructon of a large number of hardware prototypes. In ths context, many model-based approaches for estmatng energy consumpton and performance have been developed over the last years (e.g., [1 4]). Some of these model the energy consumpton adoptng cycle-level smulators (also known as

2 2 EURASIP Journal on Embedded Systems archtecture level model approach) [2, 5]. Despte provdng very accurate estmates, the low abstracton level adopted by current approaches demands an enormous computatonal effort, whch restrcts the applcablty for large codes. Ths work presents a dscrete event modelng strategy, based on Coloured Petr Net formalsm (CPN) [6], for performance and energy consumpton evaluaton of embedded systems usng the archtecture level model approach. In partcular, ths paper presents a novel method for specfyng and evaluatng the performance and energy consumpton of embedded systems consderng dfferent confguratons for workload and the platform components, such as processors and memores. The method s appled to model a real platform, namely, NXP LPC2106, and a theoretcal multprocessor platform. The hgh level of abstracton of the proposed models allows for fast but accurate estmates. Addtonally, although specfc platforms have been consdered, the modelng approach can be easly appled to other archtectures. Petr Nets (PNs) [7] are well suted to model computer archtectures, snce both parallelsm and conflct, two mportant characterstcs present n modern computer systems, are easly modeled usng ths formalsm. Besdes, PN extensons, such as CPN, have proven to be a powerful technque to evaluate performance ndces n computer systems [8]. Ths paper s organzed as follows. Secton2 presents related work. Secton 3 ntroduces the requred concepts for a better understatng of ths work. Secton 4 presents the proposed approach. Secton 5 presents some experments and Secton 6 concludes the paper. 2. Related Work Many approaches have been conceved to model energy consumpton n embedded systems. However, few consder multprocessor archtectures. The approaches can be generally classfed nto two man categores: () archtecture level (or hardware level) models and () nstructon level models. Archtecture level models calculate power and energy from detaled descrptons that may comprse crcut level, gate level, and regster transfer (RT) level. Instructon level models dealonly wthnstructons and functonal unts from the software pont of vew and wthout knowledge of the underlyng hardware organzaton [9]. The frst energy nstructon model was ntroduced n [1, 10]. These works assgn an energy cost to each nstructon (or sequence of nstructons). The cost per nstructon s assessed by measurng the average current of the processor when t executes that nstructon. Internstructon effects are also consdered. However, the tme requred to characterze an archtecture s a great ssue, snce the number of measurements grows exponentally wth the number of nstructons n the Instructon Set Archtecture (ISA). Olvera et al. [11] proposed a smulaton approach based on Coloured Petr Net. That work proposed a stochastc model for the 8051 mcrocontroller nstructon set. The method adopted CPN to model the control flow of a gven applcaton and assgned probabltes to condtonal branch nstructons, whch were translated to CPN transton guard expressons. The man drawback of that strategy s the model complexty, whch grows wth the applcaton sze, hence causng consderable negatve mpact on smulaton tme. Such an approach does not allow the evaluaton of real-lfe complex applcatons or even reasonable sze programs. That method was extended n [3] to smplfy the model. Although the smulaton tme s sgnfcantly reduced, t s stll heavly affected by the code sze. Another nstructon level approach, known as functonal-levelpoweranalyss(flpa),wasntroducedn[12] and further extended n [4]. In ths method, the processor s separated nto functonal blocks (such as fetch unt, processng unt, and nternal memory). The power consumpton of each block s characterzed through mathematcal functons obtaned from several measurements and/or smulatons. Thus, the power consumpton s obtaned by addng up the consumpton of all blocks. Although beng very fast and havng relatve good accuracy for estmatng power consumpton, the proposed analytcal modelng presents some lmtatons for estmatng executon tme, whch n turn affects the energy consumpton estmaton as shown n ther expermental results [4]. Snce exstng approaches work at a very low level of abstracton (e.g., [2, 5]),archtecture levelmodelsareknown to be very tme consumng. Besdes, those approaches also need a low-level representaton (such as RTL level) of the archtecture to allow the power characterzaton. However, these detals of mplementaton are rarely avalable for most commercal processors. 3. Modelng Formalsms A stochastc dscrete event system (SDES) [13] s a system whch occupes a sngle state for some duraton of tme, after whch an atomc event causes an nstantaneous state transton to occur. They are called dscrete event systems because ther state does not change between subsequent events, whereas state changes occur contnuously n a contnuous event system. In SDES, stochastc delays (descrbed by probablty dstrbuton functons) and probablstc choces [13] are used to model uncertantes n the system, whch may be ntroduced by many factors such as unpredctable human actons and machne falures. Many SDES models have been developed, for nstance, stochastc automata, queung models, and stochastc Petr nets. In ths work, Coloured Petr Nets (CPNs) and Dscrete Tme Markov Chans (DTMCs) are adopted to model, respectvely, the platform and the workload. A comprehensve overvew of the modelng possbltes wth SDES s out of scope for ths paper, but basc concepts are sketched. A much more thorough descrpton of SDES s avalable n [13 15] Dscrete Tme Markov Chans. A Dscrete Tme Markov Chan {X t } can be defned as a sequence of random varables X 0, X 1, X 2,..., X k n whch each one of them takes a dscrete number of possble values, and where t s defned over a dscrete set. The value taken by X t s referred to as the state

3 EURASIP Journal on Embedded Systems 3 of the DTMC at tme t. Followng the Markov property, at any t = 0, 1, 2,..., k the condtonal probablty dstrbuton of the random varable X k gven the values of ts predecessors X 0, X 1,..., X k 1 depends only on the value of ts mmedate predecessor X k 1 but not on the values of X 0, X 1,..., X k 2. Thus, ths property states that Pr(X k = x k X 0 = x 0, X 1 = x 1,..., X k 1 = x k 1 ) = Pr(X k = x k X k 1 = x k 1 ). ADTMCssadtobetmehomogeneous,fPr(X k+1 = j X k = ) s ndependent of k. Inthswork,weconsder only tme homogeneous DTMCs. Assocated wth a DTMC s a matrx called the one-step probablty transton matrx, denoted by P, whose (; j)th element s gven by the probablty p j of a state transton from state X k = to X k+1 = j n a sngle step (p j = Pr[X k+1 = j X k = ]): p 11 p 12 p 1n p 21 p 22 p 2n P =.,..... p n1 p n2 p nn 0 p j 1, n p j = 1foreach. j=1 DTMCs can be represented by a drected graph, known as the state-transton dagram. The nodes represent the states of the DTMC and the edges, the transtons between the states labeled by the respectve one-step transton probabltes. The man purpose of establshng a DTMC and the correspondng probablty transton matrx P s to obtan the probablty for the modeled system to be n a partcular state. From the state probabltes, several performance metrcs can be obtaned. Let π = (π 1, π 2, π 3,..., π n )bethe unque vector such that π = πp and n k=1 π k = 1wth π k 0. If the DTMC s fnte and rreducble, such unque π exsts and s called statonary probablty vector [16]. More specfcally, π s proporton of tme spent n state n the long-run. Moreover, t can be shown that the average number of vsts v j to state j between occurrences of state s gven by v j = π j. (3) π To evaluate DTMC models, the SHARPE tool [17] has been adopted by ths work Coloured Petr Nets. ACPN[6] s a bpartte-drected graph, consstng of two types of vertces: () places (drawn as crcles) and () transtons (drawn as bars). Places model the states, and transtons represent the events of the system. In CPN, a transton s able to fre (enabled) when () t has one token of the proper type on each of ts nput arcs, and () the guard (Boolean expresson) attached to the transton holds. (1) (2) An enabled transton can fre and thus remove tokens from ts nput places and generate tokens for ts output places. The concept of herarchcal desgn s supported by CPN. The basc dea s to allow the constructon of a large model by usng a number of smaller models. These small models are called pages and are connected to each other by places called ports. Such places can be nput or output types. It s also possble to use tme n CPN models. Tme s handled by ntroducng a global clock and allowng each token to carry a tme stamp. A token cannot be used unless the value of the clock has passed or s equal to the value of the tme stamp. Intutvely, each tme stamp ndcates the earlest tme at whch the token may be used. In order to show some concepts of CPN, a very smple model s depcted n Fgure 1(a) whch models the frst two stages of a generc ppelned processor. The CPN model conssts of two components: ppelne flow and ppelne controller. The places start, fetchng, fd, decodng, and execute model the states of the nstructon n the ppelne flow. The place control models the control of the flow of nstructons through the ppelne. Attached to the transtons f2 and d2, there s a delay of 1, whch means one clock cycle, that s, the tme requred to fetch and decode an nstructon n ths processor. The markng of places start and fetchng conssts of one token each, both wth value (colour) undefned and tme stamp 0, meanng that there s one nstructon beng fetched and the other s watng to be fetched. Snce these nstructons have not been decoded yet, they are classfed as undefned n the model. As can be seen n Fgure 1(a), transton f2 s enabled because there s a token of type n tsnputplace (fetchng), and transton f1 sdsabled because there s no token of colour fetch n the place control. Smlar concepts apply to the other dsabled transtons. When the transton f2 s fred (see Fgure 1(b)), a token s removed from place fetchng and two tokens are created n places control and fd. The new tokens get a tme stamp whch s the current tme plus one. At ths moment, transton f1 s enabled as well as transton d1. The smulaton contnues as long as enabled transtons can be found. As can be seen, the model structure makes t mpossble for two nstructons occupy the places fetchng or decodng at the same tme. Addtonally, the functon dec() n the arc (d2, execute) generates nstructons and puts them to execute. Ths functon wll be explaned n more detals n Secton 4.1. To assst our modelng we use the tool CPN Tools [18], whch s a mature and well-tested tool that supports edtng, smulaton, and analyss of CPN. 4. Modelng Approach In ths secton, the proposed method s presented and appled to evaluatng software applcatons runnng on the NXP LPC2106, an ARM7TDMI-S-based archtecture [19] Archtecture Modelng. The LPC2106 has 128 kb of on-chp FLASH and 64 kb of on-chp SRAM. It has an ARM7TDMI-S processor whch enables system desgners to buld embedded devces requrng small sze, low power,

4 4 EURASIP Journal on Embedded Systems 1 f1 fetchng 1 start f2 1`fetch 1`decode@0 Clock: 0 1 control 1`decode dec() execute d2 PIPELINE decodng (a) 1`fetch fd 1`decode d1 1`undefned@0 1 start Clock: 1 dec() execute d2 f1 fetchng f2 1`fetch 1`fetch@1+++ 1`decode@0 2 control 1`decode (b) PIPELINE decodng 1`fetch 1`undefned@1 1 fd 1`decode d1 Fgure 1: CPN model for the frst two stages of a ppelned processor. EXECUTE execute PIPELINE EXECUTE control 1`execute++1`decode++1`fetch r2 MEMORY c2 FETCH/DECODE FETCHDECODE CACHE CACHE c1 FLASH MEMORY FLASH MEMORY RAM MEMORY RAM MEMORY r1 MEMORY 3`undef start Fgure 2: CPN model for the LPC2106 archtecture (Hgh-level vew). and hgh performance. Such processor s a 32-bt RISC archtecture that conssts of a program control unt, an address generator, an nteger data path, a general-purpose regster bank, and a 3-stage ppelne. An mportant characterstc of the LPC2106 s an nstructon prefetch module, known as Memory Accelerator Module (MAM). The MAM s connected to the local bus and s placed between the FLASH memory and the ARM7TDMI-S core. Lke a cache, the MAM attempts prefetch the next nstructon from the FLASH memory n tme to prevent CPU fetch stalls. In order to model the LPC2106 archtecture, a lbrary of generc blocks of CPN models has been constructed. These blocks can be combned n a bottom-up manner to model sophstcated behavors. Modelng a complex archtecture thus becomes a relatvely smple process. The proposed CPN models are hgh-level representatons that focus on what the archtecture should perform nstead of on how t s mplemented. Moreover, t s mportant to stress that once constructed, a buldng block can be reused n other platform models. Fgure 2 presents the hghest-level vew of the model, whch s composed of the followng buldng blocks (pages, see Secton 3.2): flash memory, ram memory, fetch/decode, and execute. The fetch/decode and execute blocks model, respectvely, the frst two and the last stages of the LPC2106 s ppelne. Between these two blocks, there s a place (control), whch controls the flow of nstructons through the ppelne (see Fgure 1). The markng of place control represents the set of avalable functonal unts. The ram memory block models the SRAM memory, and the flash memory block, the FLASH memory. In these models, tmng nformaton s expressed n cycles and s represented through transton frng delays. The energy consumpton s expressed n nj unts and s modeled through the addenergy functon, whch adds the specfed energy consumpton to the global smulated consumpton. Informaton regardng tme and energy consumpton was

5 EURASIP Journal on Embedded Systems 5 f c = false then 1`++3`bubble else 1` f2 fetchng mamaccess() f1 c In End flash CACHE flash Out CACHE c [c=true] Cache ht c c1 In CACHE c2 Out CACHE Cache mss c [c = false] acton (addenergy(0.27)); In start Flash connecton (a) Fetch/decode buldng block (b) FLASH memory buldng block Fgure 3: Fetch stage and FLASH memory mul [#t =mul] acton (addenergy(3 1.3)); [#shft =false] Not shft executng1 alu executng2 executng3 [#t <> mul andalso #t <> bubble] acton (addenergy(1.54)); Shft [#shft =true] acton (addenergy(1.32)); [#t =bubble] nop acton (addenergy(1.26)); Fgure 4: Excerpt of the execute buldng block. assessed through measurements usng the AMALGHMA platform (see Secton 4.4) as well as from LPC2106 datasheet [20] and ARM7TDMI-S reference manual [19]. Except for two dfferences, the fetch/decode block s equal to the model presented n Fgure 1. Snce, n LPC2106 archtecture, the FLASH memory stores the applcaton code, the frst dfference s that the fetch stage s now connected to the flash memory block. Fgure 3(a) shows ths connecton and Fgure 3(b) shows the flash memory block. IfthedatatobefetchedsavalablentheMAMlatches (c =true), no flash access s requred. Otherwse (c =false) one flash access s requred and, thus, the respectve energy consumpton must be computed. The functon mamaccess returns a Boolean value. Gven the ht rato of the applcaton under evaluaton, frstly t generates a random number wth unform dstrbuton between 0 and 1 and then compares t to the MAM ht rato. If the random number s less or equal to the ht rato, ths functon returns true, or false, otherwse. Accesses to the FLASH memory stall the ppelne, causng the ntroducton of ppelne bubbles n the wake of the stalled nstructon (see the output arc of transton f2). The bubbles pass through all stages of the ppelne lke any other nstructon and then are dscarded n the last ppelne stage. The MAM mss rato must be provded to defne the evaluaton scenaro. To obtan ths nformaton, a smple trace-drven smulator was mplemented for supportng the

6 6 EURASIP Journal on Embedded Systems estmaton of mss ratos related to specfc nstructon patterns. Ths smulator receves as nput a trace of the executed nstructon addresses and reports the estmated MAM mss rato. The second dfference s that there are addtonal transtons n the fetch/decode block that are responsble for exchangng the nstructons n the fetch and decode stages for bubbles. These transtons become enabled when place control receves a token wth colour flush, generated by the execute block when t smulates a branch nstructon. The LPC2106 nstructon set has been dvded nto fve classes of nstructons accordng to ther performance and energy consumpton characterstcs: load, store, condtonal branch, uncondtonal branch, data operatons, and multply. For each nstructon class, the execute block defnes the next states and what should be done on the way from one state to another. Fgure 4 shows an excerpt of the execute block. As can be seen, dependng on ts class, the nstructon may take one of the paths descrbed n the model and the correspondent delay and energy consumpton computed. At decode stage, dec functon (see Fgure 1) classfes nstructons nto one of the nstructons classes. Ths functon returns a value of type n a probablstc way, such that f an nstructon of class c1 s executed wth a frequency of 50% n the code to be evaluated, ths functon wll return an value of class c1 wth probablty of 50% Workload Specfcaton. As stated earler, the dec functon generates nstructons accordng to the frequency n whch each nstructon class s executed n the applcaton under evaluaton. Snce ths frequency dstrbuton s dependent on a gven software and nput data, we devsed a method for capturng ths nformaton. The method conssts n mappng the applcaton code (wth annotatons) nto a DTMC. More specfcally, the Control Flow Graph (CFG) of the applcaton s mapped nto an rreducble DTMC. Each basc block B n the CFG s mapped nto a state X n the DTMC. Smlarly, control flow edges are mapped as transtons between states and are labeled by the state transton probabltes, as P ( B, B j ) = Pr ( B jumps to B j ), (4) whch defnes the probablty of executng B j after B. Such probabltes are obtaned from annotatons n the applcaton code. Fgure 5(a) shows an example of code, n whch annotatons are comments. In ths example, the annotaton at lne 4 ndcates that the expresson x<10 evaluates to true wth a probablty of 50%. The annotaton at lne 6 ndcates that the teratve structure s executed 9 tmes. The values for the annotatons may be captured, for nstance, from () ad hoc desgner knowledge, () a more abstract system model, and/or () extensve proflng. Several executon scenaros can be evaluated by smply changng these values. Fgure 5(b) depcts the resultng DTMC, where the reader should note an addtonal transton from state 5 to state 1 (.e., from the fnal to the startng pont of the applcaton), whch s added to make the DTMC rreducble. The objectve n such a mappng s to compute the average number of tmes each basc block n the CFG executs (vstng number). Gven the statonary probablty vector π = (π 1, π 2,..., π k ) of the mapped DTMC, whch s obtaned numercally by the SHARPE tool, let v = (v 1, v 2,..., v k )be the vector wth the average number of executons of each basc block B 1, B 2,..., B k,whereb k contans the endng pont of the applcaton. Then, v s determned by (see (3)) ( π1 v =, π 2,..., π ) k. (5) π k π k π k Gven the average number each basc block executs, the frequency n whch each nstructon s executed can be obtaned, and hence the executon frequency of each class. The methodology flow for the estmaton of the energy consumpton and executon tme n an archtecture for a gven applcaton s shown n Fgure 6. Thearchtectural model s constructed by the composton of CPN buldng blocks (rght sde of Fgure 6). The buldng blocks represent functonal unts of the archtecture under evaluaton and are modeled n a hgh abstracton level, allowng flexblty, reuse, and rapd evaluaton. These buldng blocks are annotated wth values regardng energy consumpton (addenergy functon) and performance (CPN delays) of the modeled functonal unt. Next, the code whch wll execute on the embedded platform s mapped on the archtectural model by a compler (see Secton 4.5). Fnally, the model evaluaton s made by means of stochastc smulaton (Secton 4.3) Evaluaton. The evaluaton s made by means of smulaton. The facltes of CPN Tools have been adopted to defne analyss functons and to perform data collecton. Bascally, two performance metrcs were defned: () the average executon tme per nstructon and () the average energy consumpton per nstructon. Gven these metrcs and the number of executed nstructons n the applcaton and the processor s operatng frequency, the overall energy consumpton and executon tme of an applcaton s obtaned. Frstly,a breakpont montor [8] was defned and assgned to the last transton n the execute block. Ths transton s always fred by all nstructon classes. The breakpont montor collects data and tests f the metrcs satsfy the stop crteron. If so, the smulaton stops; otherwse, the smulaton contnues. To calculate the metrcs, two data are collected on the frng of the transton lnked wth the breakpont montor: () the nterval frng tme, that s, the current tme mnus the last frng tme, and () the nterval energy consumpton, that s, the current global energy consumpton mnus the global energy consumpton of the last frng. We desgned a set of statstcal functons so that a confdence nterval for the metrcs could be constructed. The stop crteron defnes that f the confdence nterval of these two metrcs satsfes the specfed precson, the smulaton stops. The precson s specfed by two parameters: () the confdence level and () the relatve error. Ths work adopted

7 EURASIP Journal on Embedded Systems 7 Table 1: Expermental results. Executon Tme (μs) Energy Consumpton (μj) Estmated Measured Error Estmated Measured Error adpcm % % bcnt % % bnary search % % bubble sort % % convoluton % % fdct % % oxmeter (1) % % oxmeter (2) % % oxmeter (3) % % (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) } nt man() { nt x, y f (x < 10) // <0.5> { for (y = 0; y < 9; y++) { //<9> x++; } } else { // <0.5> x = 0; } (a) Code wth annotatons (b) Mapped DTMC Fgure 5: Code mappng example. Annotated source code Processor 2 Memory1 Protocol 1 Transformng code DTMC Processor 1 Memory2 Cache 1 DTMC DTMC evaluaton Component composng #nst. count #Inst. freq. Mappng the workload nto the archtecture model Archtecture model Evaluaton Fgure 6: Proposed methodology flow.

8 8 EURASIP Journal on Embedded Systems Aglent DSO03202A Seral communcaton PC wth AMALGHMA Channel 1 Channel 2 Phlps LPC2106 CPU I/O Port Fgure 7: Measurement scheme. GND 1Ohm (1) vod BubbleSort (nt Array[]) (2) { (3) nt, j; (4) nt k = NUMELEMENS-1; (5) (6) for (I = 0; < NUMELEMENS; ++) // <100> (7) { (8) 8 for (j = 0; j<k; j = j+1) //<4950> (9) { (10) f (Array[j] > Array[j + 1]) // <0.5> (11) { (12) swap(array,j,j+1); (13) } (14) } (15) (16) k ; } (17) } Fgure 9: Bubblesort algorthm Orgnal Measured Estmated 2level unrollng Energy consumpton (µj) 3level unrollng 8 level unrollng Fgure 8: Code optmzatons Inlnng Energyconsumpton (µj) MAM ht rato Table 2: Smulaton tme comparson. A1 (s) A2 (s) Task Task Task a confdence level of 95% and a maxmum relatve error of 2% Measurng Strategy. Ths secton descrbes the measurng method adopted to obtan the energy consumpton and executon tme values employed n the proposed models. To capture the average energy consumpton of each functonal unt defned n the model, assembly codes that stmulate, separately, the respectve functonal unt of the LPC2106 have been mplemented, uploaded on the platform, executed, measured, and then the obtaned data were statstcally analyzed. For example, to capture the average power consumpton when a MAM mss occurs, an assembly code that forces MAM msses was desgned. Fgure 10: Bubblesort: energy consumpton n functon of the MAM ht rate varatons. The AMALGHMA (Advanced Measurement Algorthms for Hardware Archtectures) tool has been mplemented for automatng the measurng actvtes. AMALGHMA adopts a set of statstcal methods, such as bootstrap and parametrc methods, whch are mportant n the measurement process due to several factors, for nstance, () osclloscope resoluton and () resstor error. Besdes, the results estmated by AMALGHMA were compared and valdated consderng LPC2106 datasheet as well as ARM7TDMI-S reference manual. The measurement scheme s shown n Fgure 7. Tomeasure power consumpton, a workstaton executng the AMALGHMA tool s connected to an Aglent DSO03202A osclloscope, whch captures the platform-draned current by measurng the voltage drop across a 1 Ohm sense resstor (average mcrocontroller mpedance s order of magntude hgher than ths). The osclloscope s also connected to an I/O port of the LPC2106, whch s used to montor the code s startng and end tmes. Gven ths, the code s executon tme s also estmated. Even for very short duraton software functons, the AMALGHMA tool s able to estmate

9 EURASIP Journal on Embedded Systems 9 Mcrocontroller 1 (LPC2106) Mcrocontroller 2 (LPC2106) Proc PROC 1 Data Code Data Code e1 [] EXTMEMORY EXTMEM EXTMEM e2 MEMORY External memory (a) Multprocessor envronment PROC 2 Proc (b) Multprocessor CPN model Fgure 11: Multprocessor case study. [check(i, acton (addenergy(3)); I read mem EXTMEMORY ext1 In rmread(i) getread(i) Out ext2 MEMORY rm wrte I (a) I [check(i, wrte)] wrte acton (addenergy(3.5)); 1`wrte Fgure 12: External memory model. DECLARATIONS colset MEMORY = wth read wrte tmed; colset EXTMEMORY = lst MEMORY tmed; fun rmread (x::l) = f x = read then rmread (l) else x::l rmread ([]) = []; fun getread (x::l) = f x = read then read::getread (l) else [] getread ([]) = []; fun check (x::l, t) = f x = t then true else false check ([],t) = false (b) the average executon tme, ts energy consumpton, and other related statstcs. For dong that, samplng and statstcs strateges have been mplemented [21] PECES Tool. An addtonal contrbuton of ths work was the development of a computatonal tool to automate same steps of the proposed methodology. The tool was named PECES (Performance and Energy Consumpton Evaluaton of Embedded Systems). It receves the annotated source code and the archtecture model as nput and returns the average executon tme and energy consumpton as output. The followng steps are performed by PECES to evaluate acode. (1) It comples the applcaton source code usng the opton to generate ntermedate assembly code. GCC (arm-uclbc-gcc [22]) has been adopted as compler. (2) PECES bulds the Control Flow Graph (CFG) usng the ntermedate code generated n the prevous step. (3) It uses the CFG and the annotatons from the source code to generate the correspondng rreducble DTMC. (4) The DTMC s numercally evaluated n SHARPE, so as to obtan the statonary probabltes. (5) It uses the statonary probabltes to calculate the average number of executon for each basc block and, then, the number of tmes each nstructon s executed. Next, PECES clusters nstructons from the same class and calculates the frequency each class executs. (6) The dstrbuton frequency s wrtten n the archtecture model. (7) PECES nvokes Access/CPN tool [23] tosmulatethe archtecture model. (8) Fnally, the tool uses the average executon tme per nstructon and the average energy consumpton per nstructon obtaned from the prevous step to calculate the average executon tme and the energy consumpton.

10 10 EURASIP Journal on Embedded Systems 5. Expermental Results Ths work has conducted some case studes to evaluate the proposed estmaton methods. The case studes consst of () Motorola s Powerstone benchmark sute codes (adpcm, bcnt, and fdct), () common search/orderng/sgnal processng algorthms (bnarysearch, bubblesort, and convoluton), () a customzed example, and (v) a real-world bomedcal applcaton (a pulse oxmeter). The pulse oxmeter case study s composed of three concurrent tasks; hence t has been dvded nto three separate experments. All experments were performed on an Intel Core 2 Duo 1.67 GHz, 2 Gb RAM, and Wndows Vsta OS. Table 1 shows the estmated energy consumpton and executon tme compared to the measured values for the case studes. The comparson yelds an average error of 3.36% and maxmum error of 10.2% for the estmated executon tme. Regardng the energy consumpton, the average error was of 3.81% wth maxmum of 10.02%. The pulse oxmeter experment was adopted to compare the smulaton tme of the proposed approach aganst the nstructon-smulaton method presented n [3], whch also modeled the LPC2106 (although the MAM has not been consdered) and reported an average error of 4% for the estmated metrcs. Table 2 depcts quanttatve results, n whch A2 represents the proposed approach, and A1 represents the approach presented n [3]. Results n A2 also ncludethetmetogenerateandevaluatethedtmcs,whch took less than one second for all codes. Results show that the smulaton tme n both methods are almost the same, except for the thrd task. In ths task, the proposed approach was 542 tmes faster. The huge dfference s manly because [3] smulates the control flow of the applcaton; hence, the smulaton model and the smulaton tme grow wth the code sze. On the other hand, n the method proposed by ths work, the model has a fxed sze; the varatons occur only on the frequency n whch each nstructon class s executed Applcatons of the Method. Code optmzatons, such as loop unrollng and functon nlnng, have proven to be successful technques to mprove the system performance. A very useful applcaton for the proposed method s to verfy the effect of these common code optmzatons on system energy consumpton. The bubblesort experment has been used to demonstrate how such what-f analyss may be carred out. The bubblesort code was optmzed n four steps. From step to step more aggressve optmzatons have been ncluded. Fgure 8 shows the results of ths experment. It can be seen that by applyng such optmzatons the energy consumpton was optmzed n 225%. The average error for the estmated values was of 4.38%, showng that the proposed method may be successfully employed for performng energy aware code optmzatons. The proposed method s also useful when t comes to evaluatng code operaton scenaros, such as best-case, average-case, and worst-case scenaros. The bubblesort code has been used to evaluate such applcaton. The bubblesort code s depcted n Fgure 9, wherethe reader should note that all code flow varance s defned by the three structures at lnes 6, 8, and 10. The teraton number at lnes 6 and 8 s array-length dependent, n whch a determnstc behavor s performed. On the other hand, the control structure at lne 10 has a probablstc behavor, dependng on the orderng level of the array. In the worst-case scenaro, the array s fully unordered; hence the functon swap wll becalledeverytme. Suchscenaro maybe evaluated by settng the annotaton value at lne 10 to 1. The best-case scenaro happens when the array s fully ordered. In ths case, the functon swap wll never be called. By smply settng the annotaton value at lne 10 to 0,thsscenaromay be evaluated. On the other hand, the average-case scenaro happens when the array s partally ordered. Such scenaro may also be evaluated by settng the annotaton value at lne 10 to 0.5. Table 3 shows the results for each scenaro. The estmated values for the executon tme yeld an average error of 1.69% and maxmum error of 3.94%. Regardng the energy consumpton, the average error was of 2.34% wth maxmum of 5.24%. Asstatedearler,theMAMhtratemustbegvennorder to allow accurate evaluatons. Nevertheless, meanngful results may also be obtaned f we consder the energy consumpton (or the executon tme) n functon of the MAM ht rate varatons. Fgure 10 shows the estmated energy consumpton of the bubblesort code n functon of the MAM ht rate varatons, where t can be seen that the energy consumpton ncreases when the MAM ht rate decreases Modelng Multprocessors Archtectures. In what follows, we present how the CPN basc models can be used to represent and evaluate more complex system archtectures. In partcular, ths secton presents a shared memory multprocessor archtecture, n whch each mcrocontroller has ts own MAM latches (actng as very small cache devces). Hence, ths case study presents a study of a herarchcal shared memory multprocessor archtecture, where each mcrocontroller has a three-phase ppelne. Thus, consder a hardware platform wth two LPC2106 sharng an external memory (see Fgure 11(a)). The external memory nterface can only sustan one wrte access every two cycles, whereas no such lmtaton exsts for read accesses. Incomng requests are placed n a queue and processed n a Frst In-Frst Out polcy. It s mportant to remember that each LPC2106 s also connected to two prvate memores contanng program code and data. The hardware platform descrbed above was modeled by replcatng the model already presented for the LPC2106 and creatng a new buldng block to represent the external memory. Fgure 11(b) depcts the proposed model for ths envronment, and Fgure 12 presents the external memory model. Fgure 12 also presents the CPN declaratons for the external memory. Incomng requests to the external memory are placed n a queue n e1 (Fgure 11(b)). Transtons read mem or wrte mem (see Fgure 12) become enabled whenever there are ncomng requests n the queue of place ext1.

11 EURASIP Journal on Embedded Systems 11 Table 3: Bubblesort typcal scenaros results. Executon Tme (μs) Energy Consumpton (μj) Estmated Measured Error Estmated Measured Error best-case ,5 0.74% % average-case ,8 3.94% % worst-case % % one adpcm (one mcrocontroller) two adpcms (two mcrocontrollers) Table 4: Multprocessor evaluaton results. Evaluaton tme (s) Energy consumpton (μj) Executon tme (μs) When read mem or wrte mem s fred, the correspondent energy consumpton and delay are computed. Ths model was evaluated usng the adpcm experment, where one adpcm code runs on each mcrocontroller. We also assumed that 30% of the memory nstructons access the external memory. Table 4 shows the results (lne 2) of ths experment as well as the results (lne 1) regardng the executon of one adpcm n just one mcrocontroller (already show n Table 1). Comparng the two results, the energy consumpton almost doubled, snce besdes the energy consumpton of the external memory, two processors consume more energy than just one. On the other hand, the executon tme remaned almost the same. Actually, snce the external memory ntroduces a bottleneck, there s a slghtly ncrease n ths value. However, as n lne 1 just one adpcm s runnng, the reader should note the executon tme mprovement n the parallel executon of two adpcms codes n comparson to the sequental executon of these codes. 6. Conclusons Ths work presented a method for evaluatng energy consumpton and performance n embedded systems. The proposed method adopts Coloured Petr Nets for modelng the functonal behavor of processors and memory archtectures at a hgh-level of abstracton. Further, the workload under evaluaton s mapped nto the hardware model to carry out the performance and energy consumpton estmaton. A tool, named PECES, was mplemented for automatzng the method. Addtonally, a measurng platform, named AMAL- GHMA, was constructed for characterzng the platform and for comparng the respectve results provded by the proposed method. Ths work adopted a real-world embedded platform as case study, and the expermental results show that the proposed approach may be used to ensure a rapd and relable feedback to the desgner. Besdes, applcatons of the method, such as the modelng of multprocessor archtectures, were demonstrated. As future work, we plan to mprove PECES for helpng the desgner n the platform model constructon and to valdate the method n other archtectures. References [1] V. Twar, S. Malk, and A. Wolfe, Power analyss of embedded software: a frst step towards software power mnmzaton, IEEE Transactons on Very Large Scale Integraton (VLSI) Systems, vol. 2, no. 4, pp , [2] D. Brooks, V. Twar, and M. Martonos, Wattch: a framework for archtectural-level power analyss and optmzatons, n Proceedngs of the 27th Annual Internatonal Symposum on Computer Archtecture (ISCA 07), pp , June [3] G. de Almeda Callou, P. Macel, E. de Andrade, B. Noguera, and E. Tavares, A coloured petr net based approach for estmatng executon tme and energy consumpton n embedded systems, n Proceedngs of the 21st Annual Symposum on Integrated Crcuts and System Desgn, pp , [4] E. Senn, J. Laurent, N. Julen, and E. Martn, Algorthmc level power and energy optmzaton for DSP applcatons: SoftExplorer, n Proceedngs of the IEEE Internatonal Symposum on Image/Vdeo Communcatons (ISIVC 04), [5] W. Ye, N. Vjaykrshnan, M. Kandemr, and M. J. Irwn, The desgn and use of SmplePower: a cycle-accurate energy estmaton tool, n Proceedngs of the 37th Desgn Automaton Conference (DAC 00), pp , June [6] K. Jensen, Coloured Petr Nets: Basc Concepts, Analyss Methods, and Practcal Use, Sprnger, New York, NY, USA, [7] T. Murata, Petr nets: propertes, analyss and applcatons, Proceedngs of the IEEE, vol. 77, no. 4, pp , [8] L. Wells, Performance analyss usng coloured petr nets, Ph.D. thess, Unversty of Aarhus, July [9] C. Bleakley, M. Casas-Sanchez, and J. Rzo-Morente, Software level power consumpton models and power savng technques for embedded DSP processors, Journal of Low Power Electroncs, vol. 2, no. 2, pp , [10] V. Twar and M. T.-C. Lee, Power analyss of a 32-bt embedded mcrocontroller, VLSI Desgn, vol. 7, no. 3, pp , [11] M. N. Olvera Jr., S. Neto, P. Macel et al., Analyzng software performance and energy consumpton of embedded systems by probablstc modelng: an approach based on coloured petr nets, n Proceedngs of the 27th Internatonal Conference on Applcatons and Theory of Petr Nets and Other Models of Concurrency (ICATPN 06), vol of Lecture Notes n Computer Scence, pp , [12] J. Laurent, E. Senn, N. Julen, and E. Martn, Hghlevel energy estmaton for DSP systems, n Proceedngs of the Internatonal Workshop on Power and Tmng Modelng, Optmzaton and Smulaton (PATMOS 01), pp , Yverdon-Les-Bans, Swtzerland, September [13] A. Zmmermann, Stochastc Dscrete Event Systems: Modelng, Evaluaton, Applcatons, Sprnger, New York, NY, USA, 2007.

12 12 EURASIP Journal on Embedded Systems [14] C. Cassandras and S. Lafortune, Introducton to Dscrete Event Systems, Sprnger, New York, NY, USA, [15] G. Bolch, S. Grener, H. de Meer, and K. Trved, Queueng Networks and Markov Chans, Wley-Interscence, New York, NY, USA, [16] W. Stewart, Probablty, Markov Chans, Queues, and Smulaton: The Mathematcal Bass of Performance Modelng, Prnceton Unversty, Prnceton, NJ, USA, [17] C. Hrel, R. Sahner, X. Zang, and K. Trved, Relablty and performablty modelng usng sharpe, n Proceedngs of the 11th Internatonal Conference on Computer Performance Evaluaton. Modellng Technques and Tools, vol of Lecture Notes n Computer Scence, pp , Schaumburg, Ill, USA, March [18] A. Vnter Ratzer, L. Wells, H. Lassen et al., CPN tools for edtng, smulatng, and analysng coloured petr nets, n Proceedngs of the 24th Internatonal Conference on Applcatons and Theory of Petr Nets, vol of Lecture Notes n Computer Scence, pp , Sprnger, Endhoven, The Netherlands, [19] ARM Lmted, ARM7TDMI-S Techncal Reference Manual (Rev. 4), [20] Phlps Electroncs, NXP LPC2104, LPC2105, LPC2106 Data Sheet, [21] D. Llja, Measurng Computer Performance: A Practtoner s Gude, Cambrdge Unversty Press, Cambrdge, UK, [22] Kel, Gcc compler, [23] M. Westergaard and L. Krstensen, The access/cpn framework: a tool for nteractng wth the CPN tools smulator, n Proceedngs of the 30th Internatonal Conference on Applcatons and Theory of Petr Nets, vol of Lecture Notes n Computer Scence, pp , Sprnger, 2009.