A Model-based Embedded Control Hardware/Software Co-design Approach for Optimized Sensor Selection of Industrial Systems

Transcription

1 A Model-based Embedded Control Hardware/Software Co-design Approach for Optimized Sensor Selection of Industrial Systems Kyriakos M. Deliparaschos, Konstantinos Michail, Spyros G. Tzafestas, Argyrios C. Zolotas 23rd Mediterranean Conference on Control and Automation (MED 215) Torremolinos SPAIN, June 215

2 Contents Introduction and proposed framework Electromagnetic suspension (EMS) test case FIL and FPGA architecture of LQG controller Results Conclusions 2

3 Hardware-in-the-loop (HIL) HIL widely used in developing/testing complex real-time control systems Simulation model of the plant is part of the test platform Model-based embedded control hw/sw co-design approach is followed Physical process FPGA System is realized in soft form, i.e., using a high-level language (e.g., MATLAB/Simulink) Software-based plant model Fig. 1. Communication protocol (Ethernet link) Hardware-based controller A simplified diagram of an embedded control system. In embedded control system: the model of the plant (realized on sw) interfaces with the actual controller (implemented on hw) via a communication link 3

4 System-level design Control design Maintain performance in an integrated framework Disturbances Uncertainties System Even if sensors/ actuators given, which may be the better set for the above? Faults Non-linearities Inherently Unstable Faults 4

5 Electromagnetic suspension test case EMS serves two purposes: Controller Track K Flux circulation Supports the vehicle and passengers Pole Airgap Electromagnet Driving Signal Current Power Amplifier Ensures proper ride quality 5 F Mg Vert. Accleration Vert. Velocity Suspended mass (m)

6 Input excitations and performance specs Deterministic Table 1 MAGLEV suspension constraints Constraints Value RMS acceleration & z& ) <.5ms -2 ( rms RMS gap variation, z z ) ) < 5mm (( t rms Control effort, ( u rms ) < 3V(3I o R o ) Air gap deviation, (( z t z ) p ) < 7.5mm Control effort, (u p ) < 3V(3I o R o ) Settling time, (t s ) < 3s Steady state error ( e ss ) = Stochastic - aiming for minimal set of sensors Performance specs 6 Test inputs

7 Design procedure Overall control constraint violation function Initialise Algorithm Select first Sensor set If Ω= then performance requirements are satisfied. If Ω then there is some violation of control constraints Controller selection criteria for final selection of controller Yes Optimize closed-loop performance by using Genetic Algorithms Select the best controller More sensor sets? No Select the best sensor set 7

8 Optimized sensor selection for the EMS LQR LQR full state With LQG Test maintaining Similar response performance 8

9 FPGA-in-the-loop (FIL) framework for optimized sensor selection FPGA-targetted HIL technique -> FPGA-inthe-loop (FIL) FIL schematic for EMS Physical Process (Non-linear MAGLEV suspension model) Network fabric Optimised sensor selection Out of all available outputs, yf, feed the best sensor set yo into the FIL-based LQG LQR Software model (MAGLEV) KBE Hardware model (LQG Controller) - + 9

10 LQG design architecture Sensor measurements A detailed LQG core model using explicitly scalar buses Control input K*u K*u K*u 3 sensor measurements (y1, y2, y3) airgap gain K*u current gain K*u velocity gain K*u Estimated states fixpt scaling K*u (a) 1

11 Hardware Description Language (HDL) code generation LQG conversion from floating-point domain to fixed-point domain MathWorks HDL Coder tool used to automate and speed up the process of translating high level simulation model into equivalent Register Transfer Level (RTL) HDL description (i.e., VHDL) 1 LIBRARY IEEE ; 2 USE IEEE. std_logic_1164.all ; 3 USE IEEE. numeric_std.all ; 4 5 ENTITY LQG IS 6 PORT( clk : IN std_logic ; 7 rst : IN std_logic ; 8 clk_en : IN std_logic ; 9 control_in : IN std_logic_vector(25 DOWNTO ) ; sfix26_en19 1 i_input_in : IN std_logic_vector(31 DOWNTO ) ; sfix32_en28 11 b_in : IN std_logic_vector(31 DOWNTO ) ; sfix32_en35 12 a_in : IN std_logic_vector(31 DOWNTO ) ; sfix32_en31 13 ce_out : OUT std_logic ; 14 uc_d_op : OUT std_logic_vector(34 DOWNTO ) ; sfix35_en27 15 i_op : OUT std_logic_vector(35 DOWNTO ) ; sfix36_en24 16 z_dot_op : OUT std_logic_vector(35 DOWNTO ) ; sfix36_en23 17 gap_op : OUT std_logic_vector(34 DOWNTO ) ; sfix35_en23 18 igap_op : OUT std_logic_vector(35 DOWNTO ) sfix36_en23 19 ); 2 END LQG; HDL Coder limitations in handling multi dimension matrices, hence: Detailed LQG core model using explicitly scalar buses was developed prior to HDL translation (i.e., architecture of A 3x3 sub-block) A(1,1) A(2,1) A(3,1) Out1 A(1,2) Out2 A(2,2) In1 In2 In3 (b) A(3,2) Out3 A(1,3) A(2,3) A(3,3) 11

12 HW/SW co-design FPGA flow Top-down method: for the design process of the LQG controller Model specifications and system requirements -> high level functional system model -> conversion to fixed-point (pre- FPGA implementation) Co-simulation of RTL model and fixed-point Simulink model using MathWorks HDL Verifier and Mentor Modelsim simulator Compare system implemented on FPGA chip (in real time) using a cycle accurate Simulink model forming a FIL setup Discretization Quantization MATLAB Model specifications Algorithmic analysis and implementation in floating point Model conversion in fixed point Testbench Algorithm Stimuli Diff + - Results RTL design Implementation on FPGA FPGA Integration with peripheral cores (Ethernet MAC, DCM) Implementation in RTL VHDL Co-simulation with MATLAB HDL Simulator Testbench 12 Logic synthesis Algorithm Diff + - Stimuli Results FPGA device configuration Place and Route ML65 FPGA Board FPGA-in-the-Loop simulation Ethernet link

13 Design utilization results FPGA design utilization Summary for the LQG controller with current/flux/ accel and flux modules FIL implemented on a Xilinx Virtex-6 ML65 development board utilizing a Xilinx Virtex-6 device (XC6VLX24T-1FFG1156) D of available Module(iba) Slices Slice Reg. LUTs DSP48E1 LQG /265 /113 /884 /73 KBE 49/221 77/77 17/717 1/5 A d 67/67 / 221/221 27/27 C d 3/3 / 99/99 14/14 Klqg d 75/75 / 227/227 8/8 LQR 44/44 36/36 167/167 23/23 Module(b) Slices Slice Reg. LUTs DSP48E1 LQG /25 /111 /696 /69 KBE 41/161 75/75 143/529 1/46 A d 69/69 / 22/22 27/27 C d 12/12 / 3/3 6/6 Klqg d 39/39 / 136/136 12/12 LQR 44/44 36/36 167/167 23/ Slices LQG KBE LQR D of available Slice Registers LQG KBE LQR LQG and the peripheral cores synthesized via Xilinx Synthesis Tool (XST) D of available LUTs LQG KBE LQR D of available DSP48E LQG KBE LQR 13

14 Design speed achievement* 29.1MHz clock operating freq (current/flux/accel) 3.5MHz clock operating freq (flux) Map and place and route effort was set to medium *according to post-place and route timing report on Xilinx ISE

15 EMS performance Airgap error with flux and current/flux/accel State estimation with flux (deterministic input) Continuous-time vs. FIL (discrete/quantized) x x Current with LQR Estimated current with FIL Velocity with LQR.4 Estimated velocity with FIL x 1 #3 Airgap with LQR Estimated airgap with FIL

16 Conclusions Embedded control system for EMS sensor optimization via FIL Matlab/Simulink hosts the physical process and LQG implemented on FPGA The design approach followed a fusion of system modeling and hw/sw co-design Economical FPGA implementation due to early quantization analysis in the design process Results on two sensor set examples and illustration of FIL advances in accelerating system validation 16

17 A Model-based Embedded Control Hardware/Software Co-design Approach for Optimized Sensor Selection of Industrial Systems Kyriakos M. Deliparaschos, Konstantinos Michail, Spyros G. Tzafestas, Argyrios C. Zolotas 23rd Mediterranean Conference on Control and Automation (MED 215) Torremolinos SPAIN, June 215