FPGA IMPLEMENTATION OF A PARALLEL PIPELINED HARDWARE GENETIC ALGORITHM (PPHGA) AND ITS APPLICATIONS IN FUNCTION APPROXIMATION

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1 FPGA IMPLEMENTATION OF A PARALLEL PIPELINED HARDWARE GENETIC ALGORITHM (PPHGA) AND ITS APPLICATIONS IN FUNCTION APPROXIMATION Ahmed I.Khadrag Hossam E. Mostafa Yasser Y. Hanaf Department of Computer Engneerng Arab Academy for Scence & Technology & Martme Transport Abstract Ths paper presents the research work drected regards the synthess and mplementaton of a parallel-ppelned hardware genetc algorthm (PPHGA) utlzng Very Hgh Speed Integrated Crcut Hardware Descrpton Language(VHDL) for programmng Feld Programmable Gate Arrays(FPGAs). The man desgn s dvded nto several modules. The modules are autonomous n operaton once the system starts to run. They communcate wth each other usng a handshakng protocol. Three applcatons are then expermented usng the PPHGA to test ts optmzaton power. These are lnear nterpolaton, thermstor data processng, and vehcle lateral acceleraton computaton. 1. Introducton Genetc algorthms are search algorthms based on the mechancs of natural selecton and natural genetcs. They combne survval of the fttest among strng structures wth structured yet randomzed nformaton exchange to form a search algorthm wth some of the nnovatve flar of human search. In every generaton, a new set of strngs (bts) s created usng bts of the fttest old creatures. Genetc algorthms use random ntatons to combne t wth drected schemes and explotng hstorcal nformaton n order to reach mproved performance. Due to ppelnng, parallelzaton and no functon call overhead, a hardware mplemented GA generates a really sgnfcant mproved performance and speedup over a software GA. Ths s very mportant when dealng wth real tme applcatons such as dsk schedulng and mage regstraton. We can fnd many dfferent research Department of Electrcal Engneerng Faculty of Engneerng Alexandra Unversty applcatons related to search [1,2,3], optmzaton [4, 5] and others [6, 7]. In ths research work, a PPHGA has been desgned and smulated usng VHDL [8,9] and mplemented on FPGA. Ths mplementaton s then tested n the feld of nterpolatng equatons by applyng the proposed desgn to several applcatons. The paper s organzed as follows. Secton 2 dscusses the dfferent optmzaton technques. The proposed PPHGA s ntroduced n Secton 3 Fnally Secton 4 llustrates three applcatons to the proposed desgn and compares the results wth other methods and system solutons. 2. Genetc Algorthms Superorty n Optmzaton Genetc Algorthm offers robust procedures that can explot massvely parallel archtectures appled to classfer systems. They provde a very good concepton of ntellgence and adaptaton. Tradtonal methods n search and optmzaton technques are manly three methods: (a) Calculus based methods. (b) Enumeratve methods. (c) Random methods. Frst, the problem wth the calculus methods s that they are local and depend upon the exstence of dervatves. Even f numercal approxmatons of dervatves are allowed, many practcal parameter spaces have lttle respect for dervatves. These problems do not exst n Genetc methods. Second, enumeratve methods handle each pont at a tme. Such scheme must be dscounted n the robustness race. They lack effcency and for large problem space t take too much tme and consume memory to pass through one pont 1

2 at a tme usng enumeraton. Even Dynamc Programmng enumeratve methods break on moderate szed and complex problems whch s not the case wth genetc algorthms. Thrd, random tradtonal methods wll do no better than the enumeratve schemes. On the other hand, genetc algorthm works on plan data wthout any a pror nformaton about the nature of the problem and can obtan optmum solutons n mnmum tme. 3. The Proposed PPHGA Ths secton presents the complete desgn, synthess and mplementaton of the proposed parallel-ppelned hardware genetc algorthm. Ths mplementaton s then tested n the feld of nterpolatng equatons by applyng several applcatons to the proposed desgn and perceve the results concludng the superorty of the desgn. The man software tools used for such an mplementaton are Mentor Graphcs Hardware Descrpton Language Desgner Seres (HDS) for desgn entry, ModelSm for smulaton, Leonardo Spectrum for syntheszng the hardware crcut, Xlnx Foundaton Seres 2.1, Xlnx Web Pack 4.2 and the XSTOOLs (GXSLOAD, GXSPORT, GXSETCLK, GXSTEST) that are used for testng and programmng the FPGA chps. The desgn was downloaded to three versons of chps. The frst one was an XC45 contanng 5 gates and partally contaned modules of the desgn, the second one was the SPARTAN2 XC2S1-5-tq144 contanng 1, gates, and the thrd one s the Vrtex XCV 8 contanng 8, gates The Proposed Desgn Unts The man desgn s dvded nto fve modules. The frst module s the random number generator module that s used manly to supply the system wth all the random numbers t requres. Here a lnear cellular automaton technque s chosen to produce the needed pseudo random number bt strngs. Ths method used n the random number generator uses 16 alternatng bt strng. Each cell or bt changes ts state and takes the value of xorng both sde bts and the next bt takes the value of xorng tself wth both the sde bts. Ths sequence produces a maxmum length cycle. It also produces more randomness than the lnear feedback shft regster (LFSR). The output of the pseudorandom number generator s suppled to the selecton module for scalng down the sum of ftness and to the crossover and mutaton module for determnng whether to perform crossover and mutaton and what the mutaton and crossover ponts are. The second module s the sequencer module whch s used to draw populaton members n sequence from memory usng a handshakng protocol whch s used n all the other modules. The thrd module s the selecton module whch n turn s used to select members that are subjected to the genetc operatons of reproducton, mutaton, and crossover. The genetc process s acheved usng the fourth module named the crossover and mutaton module. The ffth module s the ftness module that measures the ftness of the members and decdes whether or not the end of the run has been reached. Ths module has an embedded 32- bt floatng pont module to perform floatng pont arthmetc. Fnally s the memory nterface and control that organzes the work between all the modules and the memory. The regster confguraton for the floatngpont operatons s qute smlar to the layout for fxed-pont operatons. As a general rule, the same regsters and adder used for the fxed-pont arthmetc are used for processng the mantssas. The dfference les n the way the exponents are handled. The regster organzaton for the floatng-pont operatons s shown n the followng Fg.1. There are three regsters, BR, AC, and QR. Each regster s subdvded nto two parts. The mantssa part has the same uppercase letter symbols. The exponent part uses the correspondng lower case letter symbol. the sgn of the regstered number s n the bt wth a suffx s. The overflow result s ended up n the E bt of the regster. E Bs B b Parallel-adder As A1 Qs Q1 Parallel-adder and comparator Fg.1. Floatng pont regsters Smulaton and Synthess Results After smulaton and makng sure of the correctness of our desgn, the desgn unts were a q 2

3 syntheszed. The tmng reports, delay reports, mappng reports have been generated. Ths subsecton summarzes some measures and facts about the desgn. SCRIPTS of the Mentor Graphcs Report Number of External IOBs:15 out of 92 16% Number of Slce Flp Flops:146 out of 2,4 6% Total Number 4 nput LUTs:251 out of 2,4 1% Total equvalent gate count for desgn: 2,869 Max Delay (ns)= Fg.2 shows the regster level schematc of the whole system. Ths s produced after the generaton of the Electronc Data Interchange Format (EDIF) fle by the Leonardo Spectrum platform of the Mentor Graphcs. Fg.2. The Regster Level schematcs. Fg.3 shows a layout of the crtcal path causng the major delays n the whole system network. Ths crtcal path exsts through the ftness module. We can see by examnng all the asynchronous delay reports that the worst tme s n the ftness sgnal transmssons whch s slghtly over 6 ns delay. Fg.3. The Crtcal Path of the System. 4. PPHGA Practcal Applcatons Interpolaton s frequently used to estmate ntermedate values between precse data ponts. The most common name for ths method that s used for ths purpose s polynomal nterpolaton. The general formula used to represent an nth order polynomal s gven by 2 3 n f ( x) = a + a1 x+ a2 x + a3 x a n x (1) 4.1. Lnear Functon Interpolaton Usng the PPHGA To translate the genetc algorthm nto a search algorthm, the parameter set of the problem s coded as a fnte strng of bts. Gven a set of two dmensonal data ponts (x, y). It s requred to ft a lnear curve (a straght lne) through the gven data ponts. To get a lnear ft, the parameter set for a lne n Eq.2 s encoded by creatng ndependent bt strngs for the unknown constants c1 and c 2 whch are the parameter set descrbng the lne and then concatenate the strngs. y = c1 x + c 2 (2) The bt strngs are combnatons of s and 1 s whch represent the value of a number n bnary form. An n-bt strng can accommodate all ntegers up to the value 2 n 1. Ths bt strng could be mapped to the value of a parameter say, =1, 2 through the mappng Eq.3 below. C C C mn b + ( C L 2 1 max C = (3) mn Where b s the number n decmal form that s beng represented n bnary form. L s the length of the bt strng desgnatng the number of bts that are used to represent each chromosome or ndvdual member n the genetc algorthm populaton. C max and C mn are user defned constants dependng upon the nature of the problem. Here, they are chosen to be n the range that C 1 and C2 vary lnearly. The length of the bt strng s also arbtrarly chosen to sut the range to be represented nto the equaton parameters. Data Number x y Table.1. Data set through whch a lne ft s requred. ) 3

4 Table.1 has an nput pont set for tranng the genetc algorthm and calculate error. After runnng the proposed PPHGA for 5 generatons The graph n Fg.4 s constructed. showng the ncrease n the average ftness of each of the generatons. The ftness s a measure of how close we are to the actual output of the lnear functon presented n the prevous Table. Resstance ( Ω ) Measured A/D Counts Temperature ( o C ) Avg. Sum of Ftness Generatons Table.2. Measured resstance vs temperature vs A/D counts. Fg.5 shows the error versus the A/D counts receved from the A/D converter translatng resstance after runnng for 5 generatons. The work results n [12] are compared to our results. As perceved from the graph, the average s.8996 C. whch satsfes a.1 C error tolerance. Fg.4 The average ftness vs the number of generatons Thermstor Data Processng Usng the PPHGA Another applcaton s approxmatng polynomal parameters to calculate the temperature measured by a thermstor. Ths s done usng a genetc algorthm to compensate for the floatng pont roundng of a normal archtecture processor and to mnmze the memory problem that s used n enumeraton of the temperature tables aganst resstances. In ths research, a genetc algorthm s devsed to fnd a set of polynomals, wth nteger coeffcents, that n a pecewse fashon mnmzes the error over a set of expermentally gathered or functon sampled data. Ths work s a contnuaton of the work done n [1]. A thermstor s a temperature senstve resstor. The resstance changes approxmately 3 orders of magntude n a 1 degree C range. The Stenhart and Hart equaton, Eq.4, s a formula for computng the temperature T gven the resstance R of the thermstor [11]. T = 1/ ( a + b ln ( R) + c ( ln ( R) 3 ) (4) Sample of the PPHGA tranng data s gven n the followng Table.2. Error A/D counts Fg.5. Normal GA error vs [12]. Fgure.6 shows the degree of error versus the A/D counts of rounded MATLAB computed pecewse polynomals. The requred tolerance s not met by the MATLAB computatons. Ths s clear from the graph shown below and as the average error s C. Error A/D counts Fg.6. MATLAB rounded floatng pont error [12]. 4

5 The best results were found by applyng the problem to the proposed hardware genetc algorthm. The enhanced algorthm reduces all the floatng pont roundng errors due to the desgned 32-bt extended floatng pont arthmetc unt. Ths s shown n Fg.7. The average error s.463 C whch s far below the error tolerance and so ths proves the superor performance of our proposed desgn n functon nterpolaton. Error A/D counts Fg.7. PPHGA extended floatng pont error vs [12] Computaton of vehcle lateral acceleraton usng PPHGA The lateral acceleraton can be computed from vehcle speed and steerng wheel angle usng vehcle constants. The equaton for determnng lateral acceleraton s shown n Fg.8. Usng standard numercal methods such as the ones mentoned before results n the worst-case lateral acceleraton error exceedng.4g and a complex non-reusable ASIC mplementaton. SA * VS 2 LA = (GR * WB * k ) + (GR * US * VS 2 ) Where: GR : Gear Rato WB : Wheel Base VS : Vehcle Speed US : Understeer SA : Steerng Angle LA : Lateral Acceleraton k = Fg.8. Lateral acceleraton equaton. The gear rato, wheelbase, and understeer are dependent upon the vehcle. Ranges for these parameters are shown n Fg.9. Wheel Base: Gear Rato: Understeer: 225 to 432 mllmeters 5 to 45 degrees per degree to 1 degree per G Fg.9. Typcal parameter ranges. Usng extreme values for the constants and lmtng the vehcle speed to 16 mph and the steerng angle to 15 degrees, the maxmum value for the numerator s 3,84, (23 bts) and The maxmum value for the denomnator s 931,171 (21 bts). From the equaton n Fg.8, t s clear that the lateral acceleraton s dependent upon steerng angle and vehcle speed. The equaton must be re-evaluated every tme the steerng angle or vehcle speed changes. A value dependent on vehcle speed and the vehcle parameters can be computed and multpled by the steerng angle to obtan the lateral acceleraton. Dvson, n hardware, s relatvely slow and consumes valuable resources. But, at each vehcle speed, the steerng angle multpler s a constant. Usng the proposed desgn method, we can fnd a pecewse nterpolatng polynomal whch computes the multpler as a functon of the vehcle speed. The lateral acceleraton s then computed usng Eq.5. LA = SA_MULT * Steerng_Angle. (5) The multpler term s dependent only on the vehcle speed. The other terms, once defned, are constants. Therefore, at each vehcle speed there s a unque multpler term. The multpler term can be computed at selected vehcle speeds and used as the nput to the genetc algorthm. For the example calculatons, the vehcle constants n Fg.1 were used. Wheel Base : 289. Gear Rato : Understeer : 3.5 Fg.1. Characterstc vehcle parameters. Results ganed from usng standard numercal methods (n ths case, the secant method) are shown n Fg.11. Ths s establshed at the best performance ths numercal method would do by dvdng the speed axs n 2 MPH ntervals. Ths s done n comparson wth applyng the 5

6 problem to the hardware genetc algorthm wth 16 ponts to tran and runnng 3 generatons as shown n Fg.12, we reached an error degree of 9% n comparson wth 15% error n the case of the Secant method. Error per 1/ Tranng ponts Fg.11. Secant numercal method error vs tranng ponts. Average Error = References [1] P.D. Stroud, Kalman-extended genetc algorthm for search n nonstatonary envronments wth nosy ftness evaluatons, Evolutonary Computaton, IEEE Transactons, 5(1), Feb. 21, pp [2] G. Folno, C. Pzzut and G. Spezzano, Parallel hybrd method for SAT that couples genetc algorthms and local search, Evolutonary Computaton, IEEE Transactons, 5(4), Aug. 21, pp [3] A. Jaszkewcz, On the performance of multpleobjectve genetc local search on the /1 knapsack problem - a comparatve experment, Evolutonary Computaton, IEEE Transactons, 6(4), Aug. 22, pp [4] Y.W. Leung and Y. Wang, An orthogonal genetc algorthm wth quantzaton for global numercal optmzaton, Evolutonary Computaton, IEEE Transactons, 5(1), Feb. 21, pp Error per 1/ Tranng ponts Fg.12. Hardware genetc algorthm error vs tranng ponts. Average Error = Concluson Ths paper presents the desgn and mplementaton of an effcent hardware genetc algorthm. The proposed desgn has been appled to several optmzaton problems and t s shown that the genetc algorthm outperforms other optmzaton technques. Ths hardware mplementaton ntroduces a system on chp soluton for effcent functon approxmaton. [5] C.L. Valenzuela and P.Y. Wang, VLSI placement and area optmzaton usng a genetc algorthm to breed normalzed postfx expressons, Evolutonary Computaton, IEEE Transactons,6(4), Aug. 22, pp [6] S. Bhattacharyya, O.V. Pctet and G. Zumbach, Knowledge-ntensve genetc dscovery n foregn exchange markets, Evolutonary Computaton, IEEE Transactons, 6(2), Apr. 22, pp [7] H. Chou, G. Premkumar and C.H. Chu, Genetc algorthms for communcatons network desgn - an emprcal study of the factors that nfluence performance, Evolutonary Computaton, IEEE Transactons, 5(3), Jun. 21, pp [8] Armstrong, J. R. and F.G. Gray, VHDL Desgn Representaton and synthess, 2nd Edton, Prentce Hall, 2. [9] Wakerly, J. F. Dgtal Desgn, Prncples & Practces, 3rd Edton, Prentce Hall, 21. [1] Dhanwadda and Vemur, Curve Fttng of Temperature Sensor Data usng Genetc Algorthms, DAGSI Report, [11] YSI Precson Temperature Group, YSI Precson Thermstors & Probes, Dayton, Oho, [12] J.W. Hauser and C.N. Purdy, Sensor Data Processng Usng Genetc Algorthms, 2. 6