數位系統 Digital Systems 朝陽科技大學資工系. Speaker: Fuw-Yi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷
|
|
- Melvin Hutchinson
- 5 years ago
- Views:
Transcription
1 數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: Fuw-Yi Yang 楊伏夷 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷 Fuw-Yi Yang 1
2 Chap 3 Gate-Level Minimization 3.1 Introduction 3.2 The Map Method 3.3 Four-Variable Map 3.4 Five-Variable Map 3.5 Production-of-Sums Simplification 3.6 Don't-Care Conditions 3.7 NAND and NOR Implementation 3.8 Other Two-Level Implementation 3.9 Exclusive-Or Function 3.10 Hardware Description Language Fuw-Yi Yang 2
3 Chap 3.1 Introduction Gate-level minimization refers to the design task of finding an optimal gate-level implementation of the Boolean functions describing a digital circuit. It is important that a designer understand the underlying mathematical description and solution of a problem. Fuw-Yi Yang 3
4 Chap 3.2 The Map Method Boolean expression may be simplified by algebraic means as discussed in Section 2.4. However, this procedure of minimization is awkward because it lacks specific rules to predict each succeeding step in the manipulative process. The map method (also known as the Karnaugh map or K-map) provides a simple, straightforward procedure for minimizing Boolean functions. Fuw-Yi Yang 4
5 Chap 3.2 The Map Method two-variable map Figure 3.1 Two-Variable map Fuw-Yi Yang 5
6 Chap 3.2 The Map Method two-variable map Figure 3.2 Representation of functions in the map Fuw-Yi Yang 6
7 Chap 3.2 The Map Method three-variable map Figure 3.3 Three-variable map Fuw-Yi Yang 7
8 Chap 3.2 The Map Method Example 3.1 Simplify the Boolean function F(x, y, z) = Σ(2, 3, 4, 5) Figure 3.4 F(x, y, z) = Σ(2, 3, 4, 5) = x'y + xy' Fuw-Yi Yang 8
9 Chap 3.2 The Map Method Example 3.2 Simplify the Boolean function F(x, y, z) = Σ(3, 4, 6, 7) Figure 3.5 F(x, y, z) = Σ(3, 4, 6, 7) = yz + xz' Fuw-Yi Yang 9
10 Chap 3.2 The Map Method Example 3.3 Simplify the Boolean function F(x, y, z) = Σ(0, 2, 4, 5, 6) Figure 3.6 F(x, y, z) = Σ(0, 2, 4, 5, 6) = z' + xy' Fuw-Yi Yang 10
11 Chap 3.2 The Map Method Example 3.4 a. Express F as a sum of minterms. b. Find the minimum SOP. Figure 3.7 F = A'C + A'B + AB'C + BC = Σ(1, 2, 3, 5, 7) = C + A'B Fuw-Yi Yang 11
12 Chap 3.3 The Map Method Four-Variable Map Fuw-Yi Yang 12
13 Chap 3.3 The Map Method Four-Variable Map Fuw-Yi Yang 13
14 Chap 3.3 The Map Method Example 3.5 Simplify F(w, x, y, z) = Σ(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) Figure 3.9 F = Σ(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) = y'+ w' z'+ x z' Fuw-Yi Yang 14
15 Chap 3.3 The Map Method Example 3.5 Fuw-Yi Yang 15
16 Chap 3.3 The Map Method Example 3.6 Simplify F(A, B, C, D) = A'B'C' + B'CD' + A'BCD' + AB'C' Figure 3.10 F = A'B'C' + B'CD' + A'BCD' + AB'C' = B'C' + B'D' + A'CD' see next page Fuw-Yi Yang 16
17 Chap 3.3 The Map Method Example 3.6 Fuw-Yi Yang 17
18 Chap 3.3 The Map Method Prime implicants In choosing adjacent squares in a map, we must ensure that (1) all the minterms of the function are covered when we combine the squares, (2) the number of terms in the expression is minimized, and (3) there are no redundant terms (i.e., minterms already covered by other terms). Fuw-Yi Yang 18
19 Chap 3.3 The Map Method Prime implicants A prime implicant is a product term obtained combining the maximum possible number of adjacent squares in the map. If a minterm in a square is covered by only one prime implicant, that prime implicant is said to be essential. Simplify F(A, B, C, D) = Σ(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15) See next pages Fuw-Yi Yang 19
20 Chap 3.3 The Map Method prime Two essential prime implicants: BD and B'D' Fuw-Yi Yang 20
21 Essential prime implicants: BD and B'D' Prime implicants: AD, CD, B'C, and AB' F = BD+B'D' +CD+ AD OR BD+B'D' +CD+ AB' OR BD+B'D' +B'C+ AD OR BD+B'D' + B'C Fuw-Yi Yang 21
22 Chap 3.5 Product-of-Sums Simplification Example 3.8 Simplify F(A, B, C, D) = Σ(0, 1, 2, 5, 8, 9, 10) into a. sum-of-products form, taking the procedures as described previously, i.e., group the squares marked by 1 s and combine them. b. product-of-sums form. Group the squares marked by 0 s and combine them, i.e., we obtain F ' in the form of sum-of-product. Because of the generalized DeMorgan s theorem, the product-of-sums form is also obtained. Procedures see next page Fuw-Yi Yang 22
23 F=B'C' + B'D' + A'C'D' F' = AB + CD + BD' Applying DeMorgan s theorem to F', F = (A' + B') + (C' + D') + (B' + D) Fuw-Yi Yang 23
24 F=B'C' + B'D' + A'C'D' F' = AB + CD + BD' Applying DeMorgan s theorem to F', F = (A' + B') + (C' + D') + (B' + D) Implementation see next pages Fuw-Yi Yang 24
25 Fuw-Yi Yang 25
26 Chap 3.5 Product-of-Sums Simplification a. sum-of-products form b. product-of-sums form These two forms can also obtain from truth table, see next page. Fuw-Yi Yang 26
27 Chap 3.5 Product-of-Sums Simplification Table 3.2 x y z F m 0, M m 1, M m 2, M m 3, M m 4, M m 5, M m 6, M m 7, M 7 F(x, y, z) = Σ(1, 3, 4, 6) F(x, y, z) = Π(0, 2, 5, 7) = (x' + z') (x + z) See next page, note that we express F directly in the POS form. Fuw-Yi Yang 27
28 F(x, y, z) = Σ(1, 3, 4, 6) F'(x, y, z) = Σ(0, 2, 5, 7) By DeMorgan s Theorem F(x, y, z) = Π(0, 2, 5, 7) = (x' + z') (x + z) Fuw-Yi Yang 28
29 Chap 3.6 Don t Care Conditions Functions that have unspecified outputs for some input combinations are called incompletely specified functions. In most applications, we simply don t care what value is assumed by the function for the unspecified minterms. For this reason, it is customary to call the unspecified minterms of a function don t care conditions. These don t care conditions can be used on a map to provide further simplification of a Boolean expression. Fuw-Yi Yang 29
30 Chap 3.6 Don t Care Conditions Example 3.9 Simplify the Boolean function F(w, x, y, z) = Σ(1, 3, 7, 11, 15) which has the don t care conditions d(w, x, y, z) = Σ(0, 2, 5). Fuw-Yi Yang 30
31 Fuw-Yi Yang 31
32 Chap 3.7 NAND and NOR Implementation Digital circuits are frequently constructed with NAND or NOR gates rather than with AND and OR gates. NAND and NOR gates are easier to fabricate with electronic components and are the basic gates used in all IC digital logic families. Because of the prominence of NAND and NOR gates in the design of digital circuits, rules and procedures have been developed for the conversion from Boolean functions given in terms of AND, OR, and NOT into equivalent NAND and NOR logic diagrams. Fuw-Yi Yang 32
33 Chap 3.7 NAND and NOR Implementation -- NAND Circuits The NAND gate is said to be a universal gate because any digital system can be implemented with it. Fuw-Yi Yang 33
34 Chap 3.7 NAND and NOR Implementation -- NAND Circuits A convenient way to implement a Boolean function with NAND gates is to obtain the simplified Boolean function in terms of Boolean operators and then convert the function to NAND logic. The conversion of an algebraic expression from AND, OR, and complement to NAND can be done by simple circuit manipulation technique that change AND-OR diagrams to NAND diagrams.(minterms) Fuw-Yi Yang 34
35 Chap 3.7 NAND and NOR Implementation -- NAND Circuits Two equivalent graphic symbols for the NAND gate are shown below. It is convenient to use them in converting AND, OR, and NOT expressions into NAND expressions. See next page. Fuw-Yi Yang 35
36 Chap 3.7 NAND and NOR Implementation -- Three ways to implement F = AB + CD (two-level) (x')' = x AND-OR Equivalent symbols of NAND Implemented with NAND gates Fuw-Yi Yang 36
37 Chap 3.7 NAND and NOR Implementation -- Example 3.10 Two-level Implement F(x, y, z) = Σ(1, 2, 3, 4, 5, 7) with NAND gates. After simplification, F(x, y, z) = xy' + x'y + z AND-OR (x')' = x Implemented with NAND gates Fuw-Yi Yang 37
38 Chap 3.7 NAND and NOR Implementation -- NAND Circuits--Multilevel There are occasions, however, when the design of digital systems results in gating structures with three or more levels. The most common procedure in the design of multilevel circuits is to express the Boolean function in terms of AND, OR, and complement operations. The function can then be implemented with AND and OR gares. After that, if necessary, it can be converted into an all-nand circuit. See next page. Fuw-Yi Yang 38
39 Chap 3.7 NAND and NOR Implementation -- NAND Circuits--Multilevel AND-OR (x')' = x Fuw-Yi Yang 39
40 NAND Circuits--Multilevel Fuw-Yi Yang 40
41 Chap 3.7 NAND and NOR Implementation -- NOR Circuits The NOR gate is said to be a universal gate because any digital system can be implemented with it. Fuw-Yi Yang 41
42 Chap 3.7 NAND and NOR Implementation -- NOR Circuits A convenient way to implement a Boolean function with NOR gates is to obtain the simplified Boolean function in terms of Boolean operators and then convert the function to NOR logic. The conversion of an algebraic expression from AND, OR, and complement to NOR can be done by simple circuit manipulation technique that change OR-AND diagrams to NOR diagrams. (maxterms) Fuw-Yi Yang 42
43 Chap 3.7 NAND and NOR Implementation -- NOR Circuits Two equivalent graphic symbols for the NOR gate are shown below. It is convenient to use them in converting AND, OR, and NOT expressions into NOR expressions. See next page. Fuw-Yi Yang 43
44 Chap 3.7 NAND and NOR Implementation -- NOR Circuits Implementing F = (A + B) (C + D) E with NOR gates Note that OR-AND Equivalent symbols of NOR Fuw-Yi Yang 44
45 Chap 3.7 NAND and NOR Implementation -- NOR Circuits Implementing F = (AB' + A'B) (C + D') with NOR gates Note that OR-AND Equivalent symbols of NOR Fuw-Yi Yang 45
46 Chap 3.8 Other Two-Level Implementations The types of gates most often found in integrated circuits are NAND and NOR gates. For this reason, NAND and NOR logic implementations are the most important from a practical point of view. Some NAND and NOR gates allow the possibility of a wire connection between the outputs of two gates to provide a specific logic function. This type of logic is called wired logic. See next pages Fuw-Yi Yang 46
47 Chap 3.8 Other Two-Level Implementations Wired logic Fuw-Yi Yang 47
48 Chap 3.8 Other Two-Level Implementations AND-OR-INVERT Fuw-Yi Yang 48
49 Chap 3.8 Other Two-Level Implementations OR-AND-INVERT Fuw-Yi Yang 49
50 Chap 3.8 Other Two-Level Implementations Fuw-Yi Yang 50
51 Chap 3.8 Other Two-Level Implementations Example 3.11 Implement the function of the following map with the four 2-level forms listed in Table 3.3. Fuw-Yi Yang 51
52 Chap 3.8 Other Two-Level Implementations Example 3.11 AND-NOR AND-OR-NOT F' = x'y + xy' + z combined squares of the 0 s. Thus F = (F')' output gate NOR = OR+NOT Fuw-Yi Yang 52
53 Chap 3.8 Other Two-Level Implementations Example 3.11 NAND-AND AND-OR-NOT F' = x'y + xy' + z combined squares of the 0 s. Thus F = (F')' = (x'y + xy' + z)' = (x'y)' (xy')'z' output gate AND Fuw-Yi Yang 53
54 Chap 3.8 Other Two-Level Implementations Example 3.11 OR-NAND OR-AND-NOT F = x'y'z' + xyz' combined squares of the 1 s. Thus F = (F')' = ((x + y + z) (x' + y' + z))', or-and-not. output gate NAND = AND + NOT Fuw-Yi Yang 54
55 Chap 3.8 Other Two-Level Implementations Example 3.11 NOR-OR OR-AND-NOT F = x'y'z' + xyz' combined squares of the 1 s. Thus F = (F')' = ((x + y + z) (x' + y' + z))' = (x + y + z)' + (x' + y' + z)', output gate OR. Fuw-Yi Yang 55
56 Chap 3.9 Exclusive-OR Function The exclusive-or (XOR), denoted by the symbol, is a logical operation that performs the following Boolean operation: x y = x'y + xy'. It can be shown that the exclusive-or operation is both commutative and associative; that is, x y = y x and (x y) z = x (y z) = x y z. For implementation, see next pages. Fuw-Yi Yang 56
57 Chap 3.9 Exclusive-OR Function AND-OR-NOT implementation Fuw-Yi Yang 57
58 Chap 3.9 Exclusive-OR Function -- NAND implementation Fuw-Yi Yang 58
59 Chap 3.9 Exclusive-OR Function -- ODD Function x y = x'y + xy' x y z = xy'z' + x'yz' + x'y'z + xyz The Boolean expression clearly indicates that the XOR functions are equal to 1 if and only if an odd number of variables equal to 1. Fuw-Yi Yang 59
60 Chap 3.9 Exclusive-OR Function --Parity Generation and Checking Fuw-Yi Yang 60
61 Chap 3.9 Exclusive-OR Function --Parity Generation and Checking x Y z P Four bits are transmitted Fuw-Yi Yang 61
62 Chap 3.9 Exclusive-OR Function --Parity Generation and Checking x y z P Four bits are transmitted Check four lines (x, y, z, P) See next page Fuw-Yi Yang 62
63 Fuw-Yi Yang 63
64 Chap 3.10 Hardware Description Language HDL Example 3.1 module Simple_Circuit(A, B, C, D, E); output D, E; input A, B, C; wire w1; and G1(w1, A, B); not G2(E, C); or G3(D, w1, E); endmodule Fuw-Yi Yang 64
Gate Level Minimization Map Method
Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically
More informationChapter 3. Gate-Level Minimization. Outlines
Chapter 3 Gate-Level Minimization Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level
More informationGate-Level Minimization
MEC520 디지털공학 Gate-Level Minimization Jee-Hwan Ryu School of Mechanical Engineering Gate-Level Minimization-The Map Method Truth table is unique Many different algebraic expression Boolean expressions may
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationGate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER
Gate-Level Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
More informationGate-Level Minimization
Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationGet Free notes at Module-I One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)
More informationGate Level Minimization
Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch- Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =
More informationGate-Level Minimization
Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationCombinational Logic Circuits
Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 2-1 Binary Logic and Gates 2-2 Boolean Algebra 2-3 Standard Forms 2-4 Two-Level Circuit Optimization
More informationChapter 2. Boolean Expressions:
Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard
More informationExperiment 3: Logic Simplification
Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed El-Saied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions
More informationCombinational Logic Circuits
Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical
More informationChapter 2 Boolean algebra and Logic Gates
Chapter 2 Boolean algebra and Logic Gates 2. Introduction In working with logic relations in digital form, we need a set of rules for symbolic manipulation which will enable us to simplify complex expressions
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationExperiment 4 Boolean Functions Implementation
Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.
More information2.1 Binary Logic and Gates
1 EED2003 Digital Design Presentation 2: Boolean Algebra Asst. Prof.Dr. Ahmet ÖZKURT Asst. Prof.Dr Hakkı T. YALAZAN Based on the Lecture Notes by Jaeyoung Choi choi@comp.ssu.ac.kr Fall 2000 2.1 Binary
More informationCSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map
CSCI 22: Computer Architecture I Instructor: Pranava K. Jha Simplification of Boolean Functions using a Karnaugh Map Q.. Plot the following Boolean function on a Karnaugh map: f(a, b, c, d) = m(, 2, 4,
More informationAssignment (3-6) Boolean Algebra and Logic Simplification - General Questions
Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make
More informationChapter 2 Combinational
Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization HOANG Trang 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits and Boolean Equations Binary Logic
More informationDigital Logic Design. Outline
Digital Logic Design Gate-Level Minimization CSE32 Fall 2 Outline The Map Method 2,3,4 variable maps 5 and 6 variable maps (very briefly) Product of sums simplification Don t Care conditions NAND and NOR
More informationA B AB CD Objectives:
Objectives:. Four variables maps. 2. Simplification using prime implicants. 3. "on t care" conditions. 4. Summary.. Four variables Karnaugh maps Minterms A A m m m3 m2 A B C m4 C A B C m2 m8 C C m5 C m3
More informationCS8803: Advanced Digital Design for Embedded Hardware
CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883
More informationGate-Level Minimization
Gate-Level Minimization Mano & Ciletti Chapter 3 By Suleyman TOSUN Ankara University Outline Intro to Gate-Level Minimization The Map Method 2-3-4-5 variable map methods Product-of-Sums Method Don t care
More informationIT 201 Digital System Design Module II Notes
IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.
More informationChapter 3 Simplification of Boolean functions
3.1 Introduction Chapter 3 Simplification of Boolean functions In this chapter, we are going to discuss several methods for simplifying the Boolean function. What is the need for simplifying the Boolean
More informationSimplification of Boolean Functions
Simplification of Boolean Functions Contents: Why simplification? The Map Method Two, Three, Four and Five variable Maps. Simplification of two, three, four and five variable Boolean function by Map method.
More informationCMPE223/CMSE222 Digital Logic
CMPE223/CMSE222 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Terminology For a given term, each
More informationDKT 122/3 DIGITAL SYSTEM 1
Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits
More informationDigital Logic Lecture 7 Gate Level Minimization
Digital Logic Lecture 7 Gate Level Minimization By Ghada Al-Mashaqbeh The Hashemite University Computer Engineering Department Outline Introduction. K-map principles. Simplification using K-maps. Don t-care
More informationUnit-IV Boolean Algebra
Unit-IV Boolean Algebra Boolean Algebra Chapter: 08 Truth table: Truth table is a table, which represents all the possible values of logical variables/statements along with all the possible results of
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationUNIT II. Circuit minimization
UNIT II Circuit minimization The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented.
More information2008 The McGraw-Hill Companies, Inc. All rights reserved.
28 The McGraw-Hill Companies, Inc. All rights reserved. 28 The McGraw-Hill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28
More informationENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C.
Digital Electronics Boolean Function QUESTION BANK. The Boolean equation Y = C + C + C can be simplified to (a) (c) A (B + C) (b) AC (d) C. The Boolean equation Y = (A + B) (A + B) can be simplified to
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationGate-Level Minimization. section instructor: Ufuk Çelikcan
Gate-Level Minimization section instructor: Ufuk Çelikcan Compleity of Digital Circuits Directly related to the compleity of the algebraic epression we use to build the circuit. Truth table may lead to
More information2.6 BOOLEAN FUNCTIONS
2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses
More informationPoints Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map
Points Addressed in this Lecture Lecture 4: Logic Simplication & Karnaugh Map Professor Peter Cheung Department of EEE, Imperial College London Standard form of Boolean Expressions Sum-of-Products (SOP),
More informationCombinational Logic & Circuits
Week-I Combinational Logic & Circuits Spring' 232 - Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other
More informationLiteral Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10
Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal approach to simplification that is performed using a specific procedure or algorithm
More information1. Mark the correct statement(s)
1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another
More informationBawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University
Logic Design First Stage Lecture No.6 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Outlines Boolean Operations Laws of Boolean Algebra Rules of
More informationLSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology
LSN 4 Boolean Algebra & Logic Simplification Department of Engineering Technology LSN 4 Key Terms Variable: a symbol used to represent a logic quantity Compliment: the inverse of a variable Literal: a
More informationSpecifying logic functions
CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last
More informationECE380 Digital Logic
ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8- Terminology For
More informationX Y Z F=X+Y+Z
This circuit is used to obtain the compliment of a value. If X = 0, then X = 1. The truth table for NOT gate is : X X 0 1 1 0 2. OR gate : The OR gate has two or more input signals but only one output
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationCode No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show
More informationUNIT-4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.
UNIT-4 BOOLEAN LOGIC Boolean algebra is an algebra that deals with Boolean values((true and FALSE). Everyday we have to make logic decisions: Should I carry the book or not?, Should I watch TV or not?
More informationCHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey
CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey 2. Introduction Logic gates are connected together to produce a specified output for certain specified combinations of input
More informationSWITCHING THEORY AND LOGIC CIRCUITS
SWITCHING THEORY AND LOGIC CIRCUITS COURSE OBJECTIVES. To understand the concepts and techniques associated with the number systems and codes 2. To understand the simplification methods (Boolean algebra
More informationLecture 4: Implementation AND, OR, NOT Gates and Complement
EE210: Switching Systems Lecture 4: Implementation AND, OR, NOT Gates and Complement Prof. YingLi Tian Feb. 13, 2018 Department of Electrical Engineering The City College of New York The City University
More informationBoolean Algebra and Logic Gates
Boolean Algebra and Logic Gates Binary logic is used in all of today's digital computers and devices Cost of the circuits is an important factor Finding simpler and cheaper but equivalent circuits can
More informationVariable, Complement, and Literal are terms used in Boolean Algebra.
We have met gate logic and combination of gates. Another way of representing gate logic is through Boolean algebra, a way of algebraically representing logic gates. You should have already covered the
More informationStandard Forms of Expression. Minterms and Maxterms
Standard Forms of Expression Minterms and Maxterms Standard forms of expressions We can write expressions in many ways, but some ways are more useful than others A sum of products (SOP) expression contains:
More informationBoolean Algebra. BME208 Logic Circuits Yalçın İŞLER
Boolean Algebra BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com 5 Boolean Algebra /2 A set of elements B There exist at least two elements x, y B s. t. x y Binary operators: +
More informationBOOLEAN ALGEBRA. Logic circuit: 1. From logic circuit to Boolean expression. Derive the Boolean expression for the following circuits.
COURSE / CODE DIGITAL SYSTEMS FUNDAMENTAL (ECE 421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE 422) BOOLEAN ALGEBRA Boolean Logic Boolean logic is a complete system for logical operations. It is used in countless
More informationChapter 2: Combinational Systems
Uchechukwu Ofoegbu Chapter 2: Combinational Systems Temple University Adapted from Alan Marcovitz s Introduction to Logic and Computer Design Riddle Four switches can be turned on or off. One is the switch
More informationCombinational Logic Circuits Part III -Theoretical Foundations
Combinational Logic Circuits Part III -Theoretical Foundations Overview Simplifying Boolean Functions Algebraic Manipulation Karnaugh Map Manipulation (simplifying functions of 2, 3, 4 variables) Systematic
More informationDIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (K-MAPS)
DIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (K-MAPS) 1 Learning Objectives 1. Given a function (completely or incompletely specified) of three to five variables, plot it on a Karnaugh map. The function
More informationPhiladelphia University Faculty of Information Technology Department of Computer Science. Computer Logic Design. By Dareen Hamoudeh.
Philadelphia University Faculty of Information Technology Department of Computer Science Computer Logic Design By Dareen Hamoudeh Dareen Hamoudeh 1 Canonical Forms (Standard Forms of Expression) Minterms
More informationSummary. Boolean Addition
Summary Boolean Addition In Boolean algebra, a variable is a symbol used to represent an action, a condition, or data. A single variable can only have a value of or 0. The complement represents the inverse
More informationSimplification of Boolean Functions
COM111 Introduction to Computer Engineering (Fall 2006-2007) NOTES 5 -- page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean
More informationDigital Design. Chapter 4. Principles Of. Simplification of Boolean Functions
Principles Of Digital Design Chapter 4 Simplification of Boolean Functions Karnaugh Maps Don t Care Conditions Technology Mapping Optimization, Conversions, Decomposing, Retiming Boolean Cubes for n =,
More informationLecture (05) Boolean Algebra and Logic Gates
Lecture (05) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee ١ Minterms and Maxterms consider two binary variables x and y combined with an AND operation. Since eachv ariable may appear in either
More informationBawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University
Logic Design First Stage Lecture No.5 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Boolean Operations Laws of Boolean Algebra Rules of Boolean Algebra
More informationB.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don
More informationModule -7. Karnaugh Maps
1 Module -7 Karnaugh Maps 1. Introduction 2. Canonical and Standard forms 2.1 Minterms 2.2 Maxterms 2.3 Canonical Sum of Product or Sum-of-Minterms (SOM) 2.4 Canonical product of sum or Product-of-Maxterms(POM)
More informationCh. 5 : Boolean Algebra &
Ch. 5 : Boolean Algebra & Reduction elektronik@fisika.ui.ac.id Objectives Should able to: Write Boolean equations for combinational logic applications. Utilize Boolean algebra laws and rules for simplifying
More informationDigital Logic Design (CEN-120) (3+1)
Digital Logic Design (CEN-120) (3+1) ASSISTANT PROFESSOR Engr. Syed Rizwan Ali, MS(CAAD)UK, PDG(CS)UK, PGD(PM)IR, BS(CE)PK HEC Certified Master Trainer (MT-FPDP) PEC Certified Professional Engineer (COM/2531)
More informationBOOLEAN ALGEBRA. 1. State & Verify Laws by using :
BOOLEAN ALGEBRA. State & Verify Laws by using :. State and algebraically verify Absorption Laws. (2) Absorption law states that (i) X + XY = X and (ii) X(X + Y) = X (i) X + XY = X LHS = X + XY = X( + Y)
More informationVALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD
More informationDepartment of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic
Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic Question 1: Due October 19 th, 2009 A convenient shorthand for specifying
More informationSwitching Circuits & Logic Design
Switching Circuits & Logic Design Jie-Hong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 23 5 Karnaugh Maps K-map Walks and Gray Codes http://asicdigitaldesign.wordpress.com/28/9/26/k-maps-walks-and-gray-codes/
More informationBoolean Function Simplification
Universit of Wisconsin - Madison ECE/Comp Sci 352 Digital Sstems Fundamentals Charles R. Kime Section Fall 200 Chapter 2 Combinational Logic Circuits Part 5 Charles Kime & Thomas Kaminski Boolean Function
More informationR.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai
L T P C R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai- 601206 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC8392 UNIT - I 3 0 0 3 OBJECTIVES: To present the Digital fundamentals, Boolean
More informationLecture 5. Chapter 2: Sections 4-7
Lecture 5 Chapter 2: Sections 4-7 Outline Boolean Functions What are Canonical Forms? Minterms and Maxterms Index Representation of Minterms and Maxterms Sum-of-Minterm (SOM) Representations Product-of-Maxterm
More informationwww.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012--DIGITAL
More informationDate Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 04. Boolean Expression Simplification and Implementation
Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 04 Boolean Expression Simplification and Implementation OBJECTIVES: To understand the utilization
More informationCombinational Circuits Digital Logic (Materials taken primarily from:
Combinational Circuits Digital Logic (Materials taken primarily from: http://www.facstaff.bucknell.edu/mastascu/elessonshtml/eeindex.html http://www.cs.princeton.edu/~cos126 ) Digital Systems What is a
More informationEEE130 Digital Electronics I Lecture #4_1
EEE130 Digital Electronics I Lecture #4_1 - Boolean Algebra and Logic Simplification - By Dr. Shahrel A. Suandi 4-6 Standard Forms of Boolean Expressions There are two standard forms: Sum-of-products form
More informationChapter 6. Logic Design Optimization Chapter 6
Chapter 6 Logic Design Optimization Chapter 6 Optimization The second part of our design process. Optimization criteria: Performance Size Power Two-level Optimization Manipulating a function until it is
More informationIncompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples
Lecture B: Logic Minimization Incompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples Incompletely specified functions
More informationDIGITAL CIRCUIT LOGIC UNIT 7: MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES
DIGITAL CIRCUIT LOGIC UNIT 7: MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES 1 iclicker Question 13 Considering the K-Map, f can be simplified as (2 minutes): A) f = b c + a b c B) f = ab d + a b d AB CD
More informationChapter 3. Boolean Algebra and Digital Logic
Chapter 3 Boolean Algebra and Digital Logic Chapter 3 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn how to design simple logic circuits. Understand how
More informationNH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 1 BOOLEAN ALGEBRA AND LOGIC GATES Review of binary
More informationBinary logic. Dr.Abu-Arqoub
Binary logic Binary logic deals with variables like (a, b, c,, x, y) that take on two discrete values (, ) and with operations that assume logic meaning ( AND, OR, NOT) Truth table is a table of all possible
More informationTo write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using Karnaugh Map.
3.1 Objectives To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using. 3.2 Sum of Products & Product of Sums Any Boolean expression can be simplified
More informationComputer Science. Unit-4: Introduction to Boolean Algebra
Unit-4: Introduction to Boolean Algebra Learning Objective At the end of the chapter students will: Learn Fundamental concepts and basic laws of Boolean algebra. Learn about Boolean expression and will
More informationUNIT 2 BOOLEAN ALGEBRA
UNIT 2 BOOLEN LGEBR Spring 2 2 Contents Introduction Basic operations Boolean expressions and truth tables Theorems and laws Basic theorems Commutative, associative, and distributive laws Simplification
More informationSlide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide
More informationBoolean Analysis of Logic Circuits
Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 7 Lecture Title:
More informationENEL 353: Digital Circuits Midterm Examination
NAME: SECTION: L01: Norm Bartley, ST 143 L02: Steve Norman, ST 145 When you start the test, please repeat your name and section, and add your U of C ID number at the bottom of the last page. Instructions:
More informationEND-TERM EXAMINATION
(Please Write your Exam Roll No. immediately) END-TERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA-103 Subject: Digital Electronics Time: 3 Hours Maximum
More informationPresented By :- Alok Kumar Lecturer in ECE C.R.Polytechnic, Rohtak
Presented By :- Alok Kumar Lecturer in ECE C.R.Polytechnic, Rohtak Content - Introduction -2 Feature -3 Feature of BJT -4 TTL -5 MOS -6 CMOS -7 K- Map - Introduction Logic IC ASIC: Application Specific
More informationADAPTIVE MAP FOR SIMPLIFYING BOOLEAN EXPRESSIONS
ABSTRACT ADAPTIVE MAP FOR SIMPLIFYING BOOLEAN EXPRESSIONS Dr. Mohammed H. AL-Jammas Department of Computer and Information Engineering, College of Electronics Engineering, University of Mosul, Mosul -
More information