2. Define Instruction Set Architecture. What are its two main characteristics? Be precise!

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1 Chapter 1: Computer Abstractions and Technology 1. Assume two processors, a CISC processor and a RISC processor. In order to run a particular program, the CISC processor must execute 10 million instructions and requires an average of 12 ns per instruction. To run the same program, the RISC processor must execute 25 million instructions. How much faster must the RISC processor execute each instruction, on average, to execute the program in the same amount of time as the CISC processor? 2. Define Instruction Set Architecture. What are its two main characteristics? Be precise! 3. Provide four types (categories/classes) of instructions, as defined in class. 4. Fill-in questions: a. Software that translates assembly code into machine code: b. Software that translates high-level code into machine code: c. Of these two pieces of software, which is more computationally complex and why? d. Software that executes (interprets) MIPS instructions on a non-mips processor (SPIM) is a: 5. Fill-in questions: a. For the MIPS R2000/R3000 architecture, what is the bit width of a word? b. Provide three types of data that the computer represents as words. 6. Fill-in questions: a. What electrical devices form the basic digital-logic gates that are physically manufactured on the surface of a processor? b. What is the silicon disc called that is created early on during a processor manufacturing process? c. After it is diced into smaller silicon squares/rectangles, what are these called? 7. If, during the run of a manufacturing process, 1200 of the 2000 dies that are manufactured test OK, what is the effective yield? 1/7

2 Chapter 2: MIPS Instructions 1. Complete the following table by filling in the empty cells to connect MIPS instruction types with their corresponding encoding format. Instruction type Load and store instructions Branch instructions Arithmetic instructions having 2 register input operands Shift instructions Encoding format J-type 2. When executing the ADDI instruction, the MIPS architecture sign-extends its 16-bit immediate field before adding it to the contents of register rs. Assume for this question that the hardware designers saved costs by always zero-extending the immediate value instead. As a result, any ADDI instruction with a negative immediate value is treated as a pseudoinstruction by the assembler. When the pseudoinstruction is assembled, it is converted into a series of instructions that perform a software-based sign extension of the immediate. Assuming there have been no other architectural changes, how is the following pseudoinstruction translated: ADDI $s0, $s1, -12 Hint: the first instruction in the translation moves the 16-bit immediate into temporary register $1, which (in this case) results in register $1 having value 0000 FFF4. Three more instructions are needed: 1. ADDI $1, $0, Write a sequence of MIPS assembly code that will detect overflow for unsigned subtraction. Hint: overflow occurs when the operation s result falls outside the valid range. 4. Write a MIPS assembly-language subroutine having the following requirements. The subroutine takes two arguments, in $a0 and $a1, which hold the base memory addresses of two equal-sized arrays, and a third argument in $a2 that holds the arrays lengths. The subroutine s function is to copy the contents of the first array into the second array but in reverse order. This subroutine also must preserve the values of all the caller s registers. 2/7

3 5. Translate the following high-level code to MIPS assembly: for (i=0;i<n;i++) a[i]=i; Before your translation begins, assume variable n is stored in register $s0 and that array a is an array of half-words. 6. Describe three different functions of the immediate field in the MIPS instruction set. 7. Assume there is a MIPS pseudoinstruction named ADD64 rd, rs, rt that performs a 64-bit integer addition. The instruction ADD64 $2, $4, $6 combines registers $4 and $5 to form one 64-bit operand (i.e. $4 is high-order 32 bits and $5 is low-order 32 bits) and combines registers $6 and $7 as the other 64-bit operand. The result would be stored in a 64-bit register spanning register $2 and $3. Translate this pseudocode instruction. Hint: Think of how you perform binary addition on paper. 8. Describe the difference between a subroutine call and a system call. 9. Many CISC instruction set architectures, such as Intel IA-32 (x86) and IBM 360, include a set of instructions that do computation using a datatype called binary-coded decimal (BCD). BCD stores integer values by assigning binary-encoded decimal values (0-9) into 4-bit fields. Eight of these 4-bit fields can be packed into a 32-bit word, representing a value between 0 and 99,999,999. For example, the (16-bit) value represents 3,915 (instead of 14,613 as it would as a regular base-2 integer). Assume we have a pseudoinstruction called CBCD rd, rs that converts the binary value in register rs to an 8-digit packed BCD value written to register rd. Show (for full credit) or describe (for partial credit) how CBCD $2, $3 could be translated into MIPS instructions. Hint: how would you perform this base conversion yourself? 10. Write a sequence of MIPS assembly instructions that will swap the values of registers $s0 and $s1 without using any additional registers or any loads and stores. Hint: this requires that you use the XOR instruction. 11. List 3 different memory addressing modes available for load and stores for standard MIPS assembly language. 12. List all the memory addressing modes available for loads and stores for MIPS machine language. 3/7

4 13. Note: for the next three questions, assume the instruction word is INST a. Provide an equation for computing the effective address of a load/store target using the data provided in an encoded load/store instruction. What is this addressing mode called? b. Provide an equation for computing the effective address of a branch target using the data provided in an encoded branch instruction. What is this addressing mode called? c. Provide an equation for computing the effective address for a jump using the data provided in an encoded jump instruction (assuming the jump instruction is j or jal). What is this addressing mode called? 14. Convert the following assembly-language instruction to machine instruction(s) represented in hexadecimal. Assume the data segment of the program starts at and that INPUT is offset from the beginning of the data segment by 24 bytes. Also assume that register $1 is the only register you may use for resolving pseudoinstructions. lb $2,INPUT+2($3) Note: the opcode for lb is There are only 3 different MIPS instruction formats. List them and show their encoding. Provide the bit widths and purpose of each field word (in the common-most cases) in the instruction. 15. MIPS has the following pseudoinstruction defined, as part of its interface spec: ror rdest, rsrc1, rsrc2 This instruction performs a rotate. That is, it is a right shift but the bits that are shifted in from the left are the same bits that are shifted out from the right. The source register is defined by rsrc1 and the rotate distance is defined in rsrc2. How would the following instruction be translated into nonpseudo-mips assembly language? Remember, pseudoinstruction translation uses register 1 as a temporary register. ror $2, $3, $4 16. Describe the difference between shift right logical and shift right arithmetic. 17. Give a reason why someone would want to use a shift left operation. 4/7

5 18. Write a recursive assembly language routine called printover that takes the address of a 50-element halfword array and an integer as arguments. The routine iterates through the array, calling another routine called over for every element that is greater than the integer sent in as printover s second argument. over s arguments are the index of an element and its value. over has no return value, but printover returns the number of elements found. You only have to write printover. You may assume that over will not destroy any $a or $s registers. printover must save any registers that it destroys on the MIPS stack before doing anything else. Provide reasonable commentting for your code. 19. Compile the following C statement into MIPS assembly language. for (i=a ; (i<b[c]) (i<j) ; i+=2) b[i]=c; 5/7

6 Chapter 3: Arithmetic for Computers 1. Convert 8762 from base 10 to base Convert to IEEE 754 single-precision floating point. Represent your answer in hexadecimal. 3. Describe what computation the following segment of assembly code is performing. loop: mtc1 $0, $0 lwc1 $f1, 0($a0) lwc1 $f2, 0($a1) mul.s $f3, $f1, $f2 add.s $f0, $f0, $f3 addi $a0, $a0, 4 addi $a2, $a2, -1 bnez $a2, loop 4. Assume the following divider design: Assume the divisor and remainder registers are 12 bits and the quotient register is 6 bits. Give the values of each register for each step of the divide operation. Use decimal or binary representation. Assume the divider is dividing 40 by 12 (all register values are unsigned). Remainder Register Divisor Register Quotient Register 6/7

7 5. Would the following operation cause an overflow, assuming the result is stored in a 11-bit signed integer register? Why or why not? (-458) 6. Convert 76 to hexadecimal for a 12-bit register. 7. Convert 6FA 16 to decimal. 8. Convert to IEEE 754 binary single-precision floating point representation. Next, compute the rounding error. 9. Write a sequence of MIPS assembly code that will detect overflow for unsigned addition. 10. What does it mean to de-normalize a floating-point value? When and why is this performed? 11. What is the difference between accuracy and precision? 12. What is the tradeoff as the number of significand bits are increased while the number of exponent bits are decreased? 13. How can I guarantee that my floating-point arithmetic is accurate within.25 ulp? 7/7