Unit 15. Building Wide Muxes. Building Wide Muxes. Common Hardware Components WIDE MUXES

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1 Unit 5 Common Harware Components WIE MUXE Builing Wie Muxes Builing Wie Muxes o far muxesonly have single bit inputs I is only -bit I is only -bit What if we still want to select between 2 inputs but now each input is a 4- A B bit number A I Use a 4-bit wie 2-to- Pass all 4 bits mux B I A I I -bit wie 2-to- mux When we select I of I or I or I we want all 4-bits of that input to be passe B 4-bit wie 2-to- mux Use one mux per To buil a 4-bit wie 2-to- mux, use separate 2-to- muxes Operation: When =, all muxespass their I inputs which means all the A bits get through When =, all muxespass their I inputs which means all the B bits get through In general, to buil an m-bit wie (i.e. m-lane) n-to- mux, use iniviual muxes A A A2 A3 B B B2 B3 I I I I I I I I 2 3

2 Wie Multiplexer Example Wie Multiplexer Example 2 This 2-to-, 32-bit wie mux is really: 32 iniviual 2-to- muxes, each hanling "lane" of the 32-bit highway merger This 4-to-, 8-bit wie mux is really: 8 iniviual 4-to- muxes, each hanling "lane" of the 8-bit highway merger 2-to- Mux, 32-bit wie mux 4-to- Mux, 8-bit wie mux 2 Thus, input = B[3:] is selecte an passe to the output A[3:] B[3:] i i s y B[3:] 2 Thus, input = A[7:] is selecte an passe to the output A[7:] B[7:] C[7:] [7:] i i i2 i3 s y A[7:] elect bits = 2 =. elect bits = 2 =. Exercise How many -bit wie muxesan of what size woul you nee to buil a 4-to-, 6-bit wie mux (i.e. there are 4 numbers: W[5:], X[5:], [5:] an Z[5:]an you must select one) How many -bit wie muxesan of what size woul you nee to buil a 8-to-, 2-bit wie mux? Using muxes to control when register save ata REGITER WITH ABLE

3 Register Resets/Clears Register Problem When the power turns on the bit store in a flip-flop will initialize to a ranom value Better to initialize it to a known value (usually 's) Use a special signal calle "reset" to force the flip-flops to 's 2 2 The value on the input is sample at the clock ege an passe to the output an hols until the next clock ege Problem: Register will save ata on EVER ege Often we want the ability to save on one ege an then keep that value for many more cycles RT i i * 3 3 RT, X X i X RT 4-bit Register [3:] [3:]? 4-bit Register On clock ege, is passe to olution Registers w/ Enables Registers (-FF s) will sample the bit every clock ege an pass it to ometimes we may want to hol the value of an ignore even at a clock ege We can a an enable input an some logic in front of the -FF to accomplish this RT i i *, X X X i X X X i RT FF with ata Enable (Always clocks, but selectively chooses ol value,, or new value ) When =, value is passe back to the input an thus will maintain its value at the next clock ege When =, value is passe to the input an thus can change at the ege base on RT RT When =, is recycle back to the input When =, input is passe to FF input

4 bit Register w/ ata (Loa) Enable Registers w/ Enables Registers (-FF s) will sample the bit every clock ege an pass it to ometimes we may want to hol the value of an ignore even at a clock ege We can a an enable input an some logic in front of the -FF to accomplish this RT i i *, X X X i X X X i 2 3 RT 4-bit register with 4-bit wie 2-to- mux in front of the inputs 2 3 The value is sample at the clock ege only if the enable is active Otherwise the current value is maintaine RT [3:] [3:] COUNTER Counters Count (A to ) at each clock ege Up Counter: * = + Can also buil a own counter as well (* = ) tanar counter components inclue other features Resets: Reset count to Enables: Will not count at ege if = Parallel Loa Inputs: Can initialize count to a value P (i.e. * = P rather than +) REET Aer (+) Register

5 ample 4-bit Counter Counter esign 4-bit Up Counter RT: a synchronous reset input PE an P i inputs: loas with P when PE is active CE: Count Enable Must be active for the counter to count up TC (Terminal Count) output Active when = AN counter is enable TC = 3 2 Inicates that on the next ege it will roll over to Use to create 8-, 2-, 6- bit, etc. counters from these 4-bit builing blocks CE P P P2 P3 PE RT 4-bit CNTR 2 3 TC RT PE CE *, X X X X X X P + ketch the esign of the 4-bit counter presente on the previous slies CE P[3:] PE RT + [3:] Reg [3:] [3:] TC Counters Counter Exercise RT CE PE P3-P RT PE CE 3- P[3:] TC [3:] R=active at clock ege, thus = *=+ Enable = off, thus hols *=+ *=+ PE = active, thus *=+ *=+ =P Mealy TC output: 3 2

6 5.2 Arithmetic an Logic Units 5.22 Arithmetic an Logic Units (ALUs) can perform of many potential arithmetic or logic operations Let's efine an esign an ALU that will perform various operations ALU We will esign what is insie this block. X X 2 3 F2 F F EE9 ALU R R R2 R3 We just mae up these coe assignments an the various operations. Remember, we efinitely nee to support A, UB, AN, an (R=). F[2:] Op./Result R = X + R = X - R = X R = -X R = X & Unuse R = Unuse X X 2 3 F F F2 I I = Blank ALU To Complete 2-to-, 4-bit wie mux I I = 2-to-, 4-bit wie mux 2-to-, 4-bit wie mux I I 2 = A A A2 A3 B B B2 B3 Ci= X X C 4-bit Binary Aer C4 2 3 F[2:] Op. F[2:] Op. R = X + R = X & R = X - Unuse R = X R = R = -X EE9 ALU Unuse 2-to-, 4-bit wie mux I I 3 = EE9 ALU R R R2 R3 = = 2 = Ci = 3 = Control Logic R F[2:] 2 Ci 3 X+ X- X -X X & unuse unuse F F2F F F2F F F2F 2 F F2F F F2F Ci 3

7 X X 2 3 F F F2 I I = F F' 2-to-, 4-bit wie mux I I = F F 2-to-, 4-bit wie mux Complete ALU 2-to-, 4-bit wie mux I I 2 = F' F A A A2 A3 B B B2 B3 X X Ci=F C 4-bit Binary Aer C4 2 3 F[2:] Op. F[2:] Op. R = X + R = X & R = X - Unuse R = X R = EE9 ALU R = -X Unuse 2-to-, 4-bit wie mux I I 3 = F2 EE9 ALU R R R2 R3 Asie: Impacts of Coing () What if we change the coes use for each operation? We just mae up these coe assignments an the various operations. Remember, we efinitely nee to support A, UB, AN, an (R=). F[2:] Op./Result R = X + R = X - R = X R = -X R = X & Unuse R = Unuse F[2:] Op./Result R = X + R = -X R = X - R = R = X R = X& Unuse Unuse Asie: Impacts of Coing (2) R F[2:] 2 Ci 3 X + -X X - X X& Unuse Unuse = F2'F = F2F' + FF 2 = F2F' + F2'F'F Ci = F+F 3 = FF + F2F Notice how much more logic this coing yiels. F F2F F F2F F F2F F F2F F F2F MULTIPLIER

8 Unsigne Multiplication Review Unsigne Multiplication Review ame rules as ecimal multiplication Multiply each bit of by M shifting as you go An m-bit * n-bit mult. prouces an m+n bit result (i.e. n-bit * n-bit prouces 2*n bit result) Notice each partial prouct is a shifte copy of M or (zero) ame rules as ecimal multiplication Multiply each bit of by M shifting as you go An m-bit * n-bit mult. prouces an m+n bit result (i.e. n-bit * n-bit prouces 2*n bit result) Notice each partial prouct is a shifte copy of M or (zero) * M (Multiplican) (Multiplier) * + M (Multiplican) (Multiplier) PP(Partial Proucts) P (Prouct) Combinational Multiplier Combinational Multiplier Partial Prouct (PP i ) Generation Multiply [i] * M if [i]= => PP i = if [i]= => PP i = M * + M (Multiplican) (Multiplier) PP(Partial Proucts) P (Prouct) Partial Prouct (PP i ) Generation Multiply [i] * M if [i]= => PP i = if [i]= => PP i = gates can be use to generate each partial prouct M[3] M[2] M[] M[] if [ i]= M[3] M[2] M[] M[] if [ i]=

9 Combinational Multiplier Partial Proucts must be ae together Combinational multipliers require long propagation elay through the aers propagation elay is proportional to the number of partial proucts (i.e. number of bits of input) an the with of each aer Multiplication Overview Combinational: Array multiplier uses an array of aers Can be as simple as N- ripple-carry aers for an NxN multiplication m3 m2 m m x q3 q2 q q m3q m2q mq mq m3q m2q mq mq - m3q2 m2q2 mq2 mq m3q3 m2q3 mq3 mq p7 p6 p5 p4 p3 p2 p p AN Gate Array prouces partial prouct terms 5.35 Array Multiplier Can this be a HA? Maximum n-bit * n-bit elay is proportional to