CISC 662 Graduate Computer Architecture Lecture 5 - Pipeline. Pipelining. Pipelining the Idea. Similar to assembly line in a factory:

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1 CISC 662 Graduate Computer rchitecture Lecture 5 - Pipeline ichela Taufer Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer rchitecture, th edition ---- dditional teaching material from: Jelena irkovic ( Del) and John Kubiatowicz (C erkeley) Pipelining Pipelining the Idea Similar to assembly line in a factory: Divide instruction into smaller tasks Each task is performed on subset of resources Overlap the execution of multiple instructions by completing different tasks from different instructions in parallel Ideally this should lead to throughput of one instruction per clock cycle 1

2 npipelined achine 2 instructions completed in 6 cycles t t+1 t+2 t+3 t+ t+5 t+6 Pipelined achine 2 instructions completed in cycles t t+1 t+2 t+3 t+ t+5 t+6 Pipelining Overview Each task is called pipe stage or pipe segment ll stages must be able to proceed at the same time: Stage duration is called the processor cycle It is determined by the slowest stage Stages should use disjoint resources if possible Goal of pipelining is to increase throughput number of instructions completed per clock cycle In ideally balanced pipeline with n stages: Tinstruction _ unpipelined Tinstruction = Speedup = n n 2

3 Pipelining Overview Pipelining increases throughput, reduces the average execution time per instruction It does not reduce the time needed to execute each instruction Frequently this time is slightly increased due to overhead involved in passing between stages 5 Steps of IPS Datapath Figure.2, Page -8 Instruction Fetch Instr. Decode. Fetch Execute ddr. Calc ccess Write ack Next dder RS1 ddress Ins t RS2 RD File Data L D <= mem[]; <= + Imm Extend [ rd ] <= [ rs ] op op [ rt ] W Data npipelined IPS E E W Fetch instruction from em[] =+ In parallel: Decode the instruction Read source registers; compare registers for possible branch -extend the offset field if needed; compute possible branch target address by adding sign-extended offset to + (branch can now be completed) Note: we have two options for branch target calculation: in or in E stage! Write data into register file either for LOD or for instruction If instruction is: Load: load data from memory Store: store data from register to memory If instruction is: reference: add base register and offset to form memory address : perform the operation; for immediate sign-extend the second operand 3

4 stage Fetch instruction from em[] =+ I D LD stage In parallel: Decode the instruction Read source registers; compare registers for possible branch -extend the offset field if needed; compute branch target address by adding sign-extended offset to + I D LD E stage For memory reference: add base register and offset to form memory address For : perform the operation; for immediate sign-extend the second operand. Compute branch target by adding sign-extended offset to + I E E D E LD E E E

5 E stage If instruction is: Load: load data from memory Store: store data from register to memory I E E E D E E LD E E E W stage Write data into register file either for LOD or for instruction I W E E E E D E E LD W E E npipelined IPS I W E E E E D E E LD W E E 5

6 Pipelined IPS - Resources Separate instruction and data memory must deliver 5 times the bandwidth ister file must support two reads and one write We will perform them in half-cycles, first write and then read We need adder to increment and to perform branch target calculation, if we are doing this in stage If we do branch target calculation in E stage, we just need a simple adder in stage to increment Pipeline Data Path / /E E/E E/W I D Pipeline overhead= register delay+ clock skew E E W Instruction Fetch 5 Steps of IPS Datapath Figure.3, Page -9 Instr. Decode. Fetch Execute ddr. Calc ccess Write ack Next dder RS1 ddress <= mem[]; <= + <= [ rs ]; / RS2 Imm File Extend /E E/E RD RD RD Data E/W W Data <= [ rt ] rslt <= op op W <= rslt [ rd ] <= W 6

7 Inst. Set Processor Controller <= mem[]; <= + JSR JR <= [ rs ]; <= [ rt ] opfetch-dcd ST br jmp RR RI LD if bop(,b) <= jaddr r <= op op r <= op op im r <= + im <= + im W <= r W <= r W <= em[r] [ rd ] <= W [ rd ] <= W [ rd ] <= W Instruction Fetch 5 Steps of IPS Datapath Figure.3, Page -9 Instr. Decode. Fetch Execute ddr. Calc ccess Write ack Next dder RS1 ddress / RS2 File /E E/E Data E/W Extend Imm RD RD RD W Data Data stationary control local decode for each instruction phase / pipeline stage Visualizing Pipelining Figure.2, Page -8 Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle Cycle 5 Cycle 6 Cycle 7 I n s t r. Dem Dem O r d e r Dem Dem 7

8 Pipelining is not quite that easy! Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle Structural hazards: HW cannot support this combination of instructions (single person to fold and put clothes away) Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock) Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps). Work in Group Work in Group (I) Given the code: dd $t1, $t0, $t0 ddi $t2, $t0, #5 ddi $t, $t1, #5 1. Represent the 5-stage pipeline execution of the code (do not consider forwarding or bubble) 2. State whether (chose only one of the three possibilities): a. It must stall b. Can avoid stalls using only forwarding c. Can executing without stalling or forwarding 3. In case it cannot execute without stalling or forward, represent the 5-stage pipeline with the proper solution (forwarding or bubble) 8

9 Work in Group (II) Given the code: dd $5, $6, $7 Lw $6, 100($7) Sub $7, $6, $8 1. Represent the 5-stage pipeline execution of the code (do not consider forwarding or bubble) 2. State whether (chose only one of the three possibilities): a. It must stall b. It can avoid stalls using only forwarding c. It can executing without stalling or forwarding 3. In case it cannot execute without stalling or forward, represent the 5- stage pipeline with the proper solution (forwarding or bubble) Next Deadlines Week Date Topics Reading assigned Quiz 1 Sep Lec01 - Introduction Chap 1; pp 2 Sep 9 Lec02 Performance and ISs Q1 2 Sep 11 Lec03 ISs and Role of Compilers pp Sep 16 Lec0 - IPS Overview 3 Sep 18 Lec05 Pipeline Q2 Sep 23 Lec06 - Hazards Sep 25 Lec07 ulti-cycles pp.7; Chap 2 Sep 29 Homework 1 due 5 Sep 30 Homework review Q3 9