Lecture 16: Pipeline Controls. Spring 2018 Jason Tang

Transcription

1 Lecture 16: Pipeline Controls Spring 2018 Jason Tang 1

2 Topics Designing pipelined path Controlling pipeline operations 2

3 Pipelining Fetch Decode Execute Write ack Time Fetch Decode Execute Write ack Fetch Decode Execute Write ack Fetch Decode Execute Write ack Program Flow Fetch Decode Execute Write ack Goal is to start executing next instruction on every clock cycle Pipelining only works when there is no contention of resources If so, then either intentionally stall pipeline or duplicate those resources 3

4 Multicycle path IF: Fetch ID: Decode / Register File Read EX: Execute / ddress Calculation : Mem ccess : Write ack PC Sel Sel LU

5 Pipelined path IF: Fetch ID: Decode / Register File Read EX: Execute / ddress Calculation : Mem ccess : Write ack PC IF / ID Sel Sel ID / EX LU EX / / 5

6 Pipeline Registers IF: Fetch ID: Decode / Register File Read EX: Execute / ddress Calculation : Mem ccess : Write ack PC PC PC IR Sel Sel LU M Ext 6

7 Pipeline Controls IF: Fetch ID: Instr Decode EX: Execute : Mem ccess : Write PC PC PC IR Sel Sel LU M Ext ID Controls Decoder EX EX Controls Controls Controls 7

8 Controls and path IR Mem[PC] LU PC + IF Controls R[n] R[m] Imm* (*) PC LU ID Controls LU op LU + Imm9 LU + 0 EX Controls MDR Mem[LU] Mem[LU] LU PrevPC + Imm19 Controls R[d] LU R[d] MDR PC LU Controls 8

9 Pipeline Control Generation In single and multicycle paths, a single instruction decoder takes instruction register and generates control signals In pipelined paths, either: Single instruction decoder decodes upfront, then s controls into stationary registers to be used on subsequent cycles, or register value itself is copied into stationary registers, and then a local decoder generates signals for that portion of the path 9

10 Pipelining s Clk Cycle 1 Cycle 2 Cycle 3 Cycle Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 IF ID IF EX ID IF EX ID IF EX ID IF Ctrl EX ID EX Pipeline conflict (specifically, a structural hazard) when two instructions try to to register file on same clock cycle Only one port to register file Caused by uneven pipeline stages 10

11 Solution 1: Insert ubble into Pipeline Clk Cycle 1 Cycle 2 Cycle 3 Cycle Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 IF ID IF EX ID IF EX ID IF EX ID IF Ctrl EX ID IF Insert bubble into pipeline to prevent simultaneous s bubble bubble bubble EX ID IF EX ID bubble bubble bubble bubble EX Control logic can be complex No instruction started on Cycle 7 11

12 Solution 2: Delay Write by One Cycle Clk Cycle 1 Cycle 2 Cycle 3 Cycle Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 IF ID IF EX ID IF Ctrl EX ID IF Ctrl EX ID IF Ctrl EX ID IF Ctrl EX ID IF Ctrl EX ID Ctrl EX Ctrl Delay s by one cycle Ctrl is a no-op; it generates no controls Now pipeline has same length for all instruction types 12

13 Pipelined Operations ldur X10, [X10, #0] IM Reg LU DM Reg Time sub X11, X2, X3 IM Reg LU DM Reg add X12, X3, X IM Reg LU DM Reg stur X13, [X1, #8] IM Reg LU DM Reg Program Flow add X1, X5, X6 IM Reg LU DM Reg IM =, Reg =, DM = Shade on right =, Shade on left = 13

14 Pipeline Controls RegWrite LUSrc LUOp PC Sel Sel LU MemToReg LUSrc MemRead MemWrite PC is updated every cycle, so no need for PCWrite signal Pipeline registers (green boxes) also updated every cycle 1

15 Setting Pipeline Controls EX LUSrc LUSrc LUOp MemRead MemWrite MemToReg RegWrite add add sub sub ldur Ext (imm9) add 1 0 M 1 stur Ext (imm9) add 0 1 X 0 decoder calculates control signal values given instruction register Writes those values to pipeline registers, to be used by later cycles 15

16 Example of Pipeline: Cycle 0 00: ldur PC 00 PC IR RegWrite Sel Sel PC Ext LUSrc LUOp LU M 0: sub 08: add 0C: stur 10: add MemToReg Decoder EX LUSrc MemRead MemWrite Initial state (Cycle 0): PC = 00 16

17 Example of Pipeline: fter Cycle 1 IF 00: ldur PC 0 PC 00 ldur IR RegWrite Sel Sel PC Ext LUSrc LUOp LU M 0: sub 08: add 0C: stur 10: add MemToReg Decoder EX LUSrc MemRead MemWrite Fetch from 00h, then increment PC 17

18 Example of Pipeline: fter Cycle 2 ID 00: ldur PC 08 PC 0 sub IR RegWrite Sel Sel PC 00 X10 X #0 Ext LUSrc LUOp LU IF M 0: sub 08: add 0C: stur 10: add MemToReg, EX Ext, add LUSrc MemRead MemWrite Decoder 1, 0 M, 1, X10 Fetch from 0h; decode ldur X10, [X10, #0] and generate controls 18

19 Example of Pipeline: fter Cycle 3 EX 00: ldur PC 0C PC 08 add IR RegWrite Sel Sel PC 0 X2 X3 Ext X LUSrc Ext LUOp add LU sum X ID IF M 0: sub 08: add 0C: stur 10: add MemToReg, EX, sub LUSrc MemRead Decoder 0, 0 1, 0, 1, M, 1, X11 X10 Fetch from 08h; decode sub X11, X2, X3; execute ldur MemWrite 19

20 Example of Pipeline: fter Cycle PC 10 PC 0C stur IR Sel Sel Decoder RegWrite PC 08 X3 X Ext X, EX, add 0, 0, 1, X12 LUSrc LUSrc LUOp sub LU diff X3 0, 0, 1, X11 MemRead 1 0 Fetch 0h; decode add X12, X3, X; execute sub; access ldur sum MD MemWrite 00: ldur EX ID IF M, 1, X10 0: sub 08: add 0C: stur 10: add MemToReg 20

21 Example of Pipeline: fter Cycle 5 00: ldur PC 1 PC 10 add IR RegWrite 1 Sel Sel X10 PC 0C X1 X13 #8 Ext LUSrc LUOp add LU sum X 0 0 0: sub EX ID IF diff MX 08: add 0C: stur 10: add M MemToReg Decoder, EX Ext, add 0, 1 X, 0, X LUSrc 0, 0, 1, X12 MemRead MemWrite, 1, X11 Fetch 10h; decode stur X13, [X1, #8]; execute add; access sub (noop); ldur 21

22 Example of Pipeline: fter Cycle 6 PC 18 1 PC 1 PC 10 IR Sel Sel Decoder RegWrite X11 X5 X6 Ext X, EX, add 0,0, 1, X1 LUSrc Ext LUSrc LUOp add LU sum X13 0, 1 X, 0, X MemRead 0 0 diff MX X MemWrite, 1, X12 Decode add X1, X5, X6; execute stur; access add (noop); sub 00: ldur 0: sub 08: add EX ID 0C: stur 10: add MemToReg 22

23 Example of Pipeline: fter Cycle 7 PC 1C 1 PC 18 PC 1 IR Sel Sel Decoder RegWrite X12 Ext EX Execute add; access stur; add LUSrc LUSrc LUOp add LU sum X6 0, 0, 1, X1 MemRead 0 1 sum MX X MemWrite X, 0, X 00: ldur 0: sub 08: add 0C: stur EX 10: add MemToReg 23

24 Example of Pipeline: fter Cycle 8 PC 20 0 PC 1C PC 18 IR Sel Sel Decoder RegWrite Ext EX ccess add (noop); stur (noop) X LUSrc LUSrc LUOp LU MemRead 0 0 sum MX X MemWrite, 1, X1 00: ldur 0: sub 08: add 0C: stur 10: add X MemToReg 2

25 Example of Pipeline: fter Cycle 9 00: ldur PC 2 RegWrite PC 20 1 PC 1C IR Sel Sel X1 Ext LUSrc LUOp LU M 0: sub 08: add 0C: stur 10: add MemToReg Decoder EX LUSrc MemRead MemWrite Write add 25