Implementing an ISA, part II - Control
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1 Implementing an IS, part II - Control David E. Culler CS61CL Nov 4, 2009 Lecture 10 11/4/09 UCB CS61CL F09 Lec 10 1
2 Review: TinyMIPS Reg-Reg instructions (op == 0) addu R[rd] := R[rs] + R[rt]; pc:=pc+4 subu R[rd] := R[rs] - R[rt]; pc:=pc+4 Reg-Immed (op!= 0) lw R[rt] := Mem[ R[ rs ] + signex(im16) ] sw Mem[ R[ rs ] + signex(im16) ] := R[rt] Jumps j PC := PC addr 00 jr PC := R[rs] Branches BEQ PC := (R[rs] == R[rt])? PC + signex(im16) : PC+4 BLTZ PC := (R[rs] < 0)? PC + signex(im16) : PC+4 11/4/09 UCB CS61CL F09 Lec 10 2
3 Review: DataPath + Control RM D +4 PC IR ~ B Ci + sel Bsel Dsel ld xt rs rt rd npc_sel ld_pc pc2 ld_ir i2d wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d 11/4/09 UCB CS61CL F09 Lec 10 3
4 Control State Machine (abstract) ddu R[rd]:=R[rs]+R[rt]; I-Fetch IR := Mem[pc] reset ~reset&op==lw SubU R[rd] := R[rs]-R[rt]; LW R[rt] := mem[r[rs]+sx16]; SW mem[r[rs]+sx16] := R[rt]; J pc := pc addr 00 JR pc := R[rs] BR-taken pc := pc + sx16 00 BR-not taken pc := pc /4/09 UCB CS61CL F09 Lec 10 4
5 Ifetch: IR := mem[pc] RM D +4 PC IR ~ B Ci + sel Bsel Dsel ld xt rs rt rd npc_sel ld_pc pc2 ld_ir i2d wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d RM_addr <- <- PC; (pc2, ~s2) IR_in <- D <- RM_data; (~i2d,m2d,~b2d,~s2d) IR := IR_in; (ld_ir,~ld_pc,~ld_reg, ~wrt) 11/4/09 UCB CS61CL F09 Lec 10 5
6 Control State Machine I-Fetch IR := Mem[pc] pc2,~s2,~ir2d, m2d,~b2d,~s2d,ld _ir,~ld_pc, ~ld_reg, ~wrt reset ~reset&op==lw ddu R[rd]:=R[rs]+R[rt]; SubU R[rd] := R[rs]-R[rt]; LW R[rt] := mem[r[rs]+sx16]; SW mem[r[rs]+sx16] := R[rt]; J pc := pc addr 00 JR pc := R[rs] BR-taken pc := pc + sx16 00 BR-not taken pc := pc /4/09 UCB CS61CL F09 Lec 10 6
7 Exec: R[rd]:=R[rs]+R[rt]; pc:=pc+4; RM D +4 PC IR ~ B Ci + sel Bsel Dsel ld xt rs rt rd npc_sel ld_pc pc2 ld_ir i2d wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d npc_sel=0,ld_pc,~pc2,~ld_ir,~i2d,~wrt,~m2d,~rt_sel,ld_reg, ~b2d,~sx_sel,~comp,~s2,s2d 11/4/09 UCB CS61CL F09 Lec 10 7
8 Control State Machine ddu R[rd]:=R[rs]+R[rt]; npc_sel=0,ld_pc,~pc2,~ld_ir,~i2d,~wrt,~m2d, ~rt_sel,ld_reg,~b2d,~sx_sel,~comp,~s2,s2d SubU R[rd] := R[rs]-R[rt]; LW R[rt] := mem[r[rs]+sx16]; I-Fetch IR := Mem[pc] pc2,~s2,~ir2d, m2d,~b2d,~s2d,ld _ir,~ld_pc, ~ld_reg, ~wrt reset SW mem[r[rs]+sx16] := R[rt]; J pc := pc addr 00 JR pc := R[rs] BR-taken pc := pc + sx16 00 BR-not taken pc := pc /4/09 UCB CS61CL F09 Lec 10 8
9 Exec: R[rd]:=R[rs]-R[rt]; pc:=pc+4; RM D +4 PC IR ~ B Ci + sel Bsel Dsel ld xt rs rt rd npc_sel ld_pc pc2 ld_ir i2d wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d npc_sel=0,ld_pc,~pc2,~ld_ir,~i2d,~wrt,~m2d,~rt_sel,ld_reg, ~b2d,~sx_sel,comp,~s2,s2d 11/4/09 UCB CS61CL F09 Lec 10 9
10 Exec LW: R[rt]:= Mem[R[rs]+SXim16]; RM D +4 PC IR ~ B Ci + sel Bsel Dsel ld xt rs rt rd npc_sel ld_pc pc2 ld_ir i2d wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d npc_sel=0, ld_pc, m2d, rt_sel, ld_reg, sx_sel, s2 11/4/09 UCB CS61CL F09 Lec 10 10
11 Exec SW: Mem[R[rs]+SXim16] := R[rt] RM D +4 PC IR ~ B Ci + sel Bsel Dsel ld xt rs rt rd npc_sel ld_pc pc2 ld_ir i2d wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d 11/4/09 UCB CS61CL F09 Lec 10 11
12 Exec J: PC := PC addr 00 RM D +4 PC IR ~ B Ci + sel Bsel Dsel ld xt rs rt rd npc_sel ld_pc pc2 ld_ir i2d wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d npc_sel=1, ld_pc, i2d 11/4/09 UCB CS61CL F09 Lec 10 12
13 Exec JR: PC := R[rs] RM D +4 PC IR ~ B Ci + sel Bsel Dsel ld xt rs rt rd npc_sel ld_pc pc2 ld_ir i2d wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d npc_sel=2, ld_pc, s2d, sx_sel=2 11/4/09 UCB CS61CL F09 Lec 10 13
14 Exec Br Taken: PC := PC + SX16 RM D +4 PC IR ~ B Ci + sel Bsel Dsel ld xt rs rt rd npc_sel ld_pc pc2 ld_ir i2d wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d npc_sel=3, ld_pc, i2d 11/4/09 UCB CS61CL F09 Lec 10 14
15 Controller Specification 11/4/09 UCB CS61CL F09 Lec 10 15
16 dminstration HW7 due midnight Mid Term 2 Monday 11/9 5:30 7:30 RM: 145 Dwinelle alternate Friday 11/4 3:00-5:00 rm TB Review session Thurs Project 3 incremental lab check offs Flex lab mon (9-5) and tues (9-1) midterm final prep project 3 help 11/4/09 UCB CS61CL F09 Lec 10 16
17 Controller Implementation exec npc_sel clk reset op eq n s2d 11/4/09 UCB CS61CL F09 Lec 10 17
18 Combinational Logic per Ctrl Point exec exec pc2 ldpc exec op wrt 11/4/09 UCB CS61CL F09 Lec 10 18
19 Multiplexor Control I I I x 0 0 x x 0 0 op 11/4/09 UCB CS61CL F09 Lec 10 19
20 Faster Clock RM D ddr +4 PC IR B ~ B Ci S + sel Bsel Dsel ld xt rs rt rd npc_sel ld_pc pc2 ld_ir i2d wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d Clock Period > Longest path from reg out to input + reg delay 11/4/09 UCB CS61CL F09 Lec 10 20
21 Multi-Cycle Controller State Machine ddu S:=+B; SubU S := B; LW S=+sx16; R[rd]:=S; R[rd]:=S; read MR:=S; R[rd]:=D I-Fetch IR := Mem[pc] Op / Dcd := R[rs], B := R[rt] SW S=+sx16; J pc := pc addr 00 JR pc := R[rs] BR-taken pc := pc + sx16 00 wrt MR:=S; MDR:=B BR-not taken pc := pc /4/09 UCB CS61CL F09 Lec 10 21
22 Time State control mem B Ci PC IR IR_ex mem IR_mem IR_wb Move control word through the stages Decode per stage ctive stage moves around the ring 11/4/09 UCB CS61CL F09 Lec 10 22
23 Time State Control RM D ddr +4 PC IR B ~ B Ci S + sel Bsel Dsel ld xt rs rt rd npc_sel ld_pc pc2 ld_ir i2d wrt m2d rt_sel ld_reg b2d sx_sel comp s2 s2d ifetch decode exec mem wb 11/4/09 UCB CS61CL F09 Lec 10 23
24 More regular multi-cycle execution ddu S:=+B; SubU S := B; LW S=+sx16; S :=S; S :=S; read MR:=S; R[rd]:=S; R[rd]:=S ; R[rd]:=D I-Fetch IR := Mem[pc] Op / Dcd := R[rs], B := R[rt] SW S=+sx16; J pc := pc addr 00 JR pc := R[rs] BR-taken pc := pc + sx16 00 wrt MR:=S; MDR:=B BR-not taken pc := pc /4/09 UCB CS61CL F09 Lec 10 24
25 Sequence of Multi-step Operations Operation implemented as sequence of step on distinct resources wash => dry => fold Multiple independent Operations IF DCD Ex Mem WB 11/4/09 UCB CS61CL F09 Lec 10 25
26 Technology Trends Clock Rate: Transistor Density: ~35% Chip rea: ~15% ~30% per year Transistors per chip: ~55% Total Performance Capability: ~100% by the time you graduate... 3x clock rate (>10 GHz) 10x transistor count (100 Billion transistors) 30x raw capability plus 16x dram density, 32x disk density (60% per year) Network bandwidth, 11/4/09 cs61cl f09 lec 5 26
27 Pipelining Overlap consecutive operations 11/4/09 UCB CS61CL F09 Lec 10 27
28 Definition: Performance Performance is in units of things per sec bigger is better If we are primarily concerned with response time performance(x) = 1 execution_time(x) " X is n times faster than Y" means Performance(X) Execution_time(Y) n = = Performance(Y) Execution_time(Y) 11/4/09 cs61cl f09 lec 5 28
29 Pipeline Performance N operations performed in k steps each Sequential Time: N*k Lower bound: N (1 every cycle) Pipeline Time: k 1 + N Bound on Speedup on k-stage pipeline < k Speedup(k,N) StartUp Cost: k-1 Peak Rate Half Power point = Time(1,N)/Time(k,N) = N*k / (N+k-1) N / (1+k/N) 11/4/09 UCB CS61CL F09 Lec 10 29
30 Performance Trends MIPS R /4/09 cs61cl f09 lec 5 30
31 Processor Performance (1.35X before, 1.55X now) 1.54X/yr 11/4/09 cs61cl f09 lec 5 31
32 Pipelined control imem B Ci Dmem PC IR IR_ex IR_mem IR_wb 11/4/09 UCB CS61CL F09 Lec 10 32
33 Pipelined Instruction Execution Fetch Instruction Every cycle Launch into a pipeline What if they are not independent? structural hazards» two operations need to use same resource data dependence» later instruction needs to use the value produce by an earlier on Detect Wait till hazard clears 11/4/09 UCB CS61CL F09 Lec 10 33
34 Pipelined Bubble imem B Ci Dmem PC IR IR_ex IR_mem IR_wb 11/4/09 UCB CS61CL F09 Lec 10 34
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