# Machine Organization & Assembly Language

Save this PDF as:

Size: px
Start display at page:

## Transcription

1 Name: CSE 378 Winter 29 Machine Organization & Assembly Language Midterm Exam Solution your answers on these pages. itional pages may be attached (with staple) if necessary. Please ensure that your answers are legible. Please show your work. your name at the top of each page. Total points:. [ Points] The Stack. (a) Why is the stack a convenient structure for function calls? The stack is convenient because it models the process of control exchange well. When a processes calls another processes the callee process (and all subsequent calls) must fully finish before the calling process can resume. This closely resembles the stack s first-in-last-out design. Also the local variables of individual functions can be safely preserved in this manner, as the local stack frame of subsequent function calls will be placed after that of the current. (b) What is normally stored on the stack? As a function is called, it places all of its local variables at a particular place on the stack. If it calls another function, then that function would place its local variables directly below that and so on, corresponding to pushing things onto a stack. Once the function returns, the space it used is freed, and the stack pointer points to the function directly before it, resuming that function. This corresponds to popping something off of a stack. (c) What is the stack pointer? Points to top of the stack (d) How do you push onto the stack? Move the stack pointer and put the on the stack. (e) How do you pop off of the stack? Move the stack pointer

2 Name: 2 2. [3 points] MIPS Programming The strstr() function finds the position of the first occurrence of a substring within a bigger string. For example, if a program calls strstr( stack, ack ) the function should return 2 (the the beginning position of ack within stack ). Should a program call strstr( stack, acc ) the function should return -, since acc is not a substring within the source string. Here are some examples: strstr( cse378, 37 ) returns 3 strstr( cse378, cs ) returns strstr( cse378, bob ) returns - Translate this C code into MIPS assembly using the template on the next page. Your solution will not be graded for syntax, but you must use the proper opcode and register names. You should make use of the following assumptions: \$a contains the of the first char of string \$a contains the of the first char of string2 \$v should be used to hold the return value your function will be called by some other function. you are allowed to use pseudo-instructions. C version int strstr(char* haystack, char* needle) { int i, j; // outer loop for(i=; haystack[i]!= \ ; i++) { // inner loop for(j=; needle[j]!= \ && needle[j] == haystack[i+j]; j++) { // just move to next character } if (needle[j] == \ ) { // if needle is exhausted, return i; // needle found at this position } } return -; // no match } MIPS assembly version (next page)

3 Name: 3 MIPS assembly version strstr: addiu \$sp, \$sp, -4 sw \$ra, (\$sp) add \$s, \$a, \$zero add \$s, \$a, \$zero addi \$t, \$zero, addi \$t, \$zero, # base pointer for string # base pointer for string2 # i # j outer_loop: inner_loop: end: lw \$ra, (\$sp) addiu \$sp, \$sp, 4 jr \$ra

5 Name: 5 3. [2 Points] Datapath. Let s add a Jump Indirect instruction to the single-cycle processor developed in class. This I-format instruction jin imm6(rs) will cause the processor to jump to the stored in the word at location imm6 + R[rs] (the same computed by lw and sw). PC 4 Shift left 2 [3 ] Reg I [25 2] I [2 6] register register 2 I [5 ] 2 register Registers 3 2 RegDst ALUSrc PCSrc ALU Zero Result ALUOp Mem Data Mem MemToReg 2 I [5 ] Sign extend (a) Draw the necessary modifications to implement the jin instruction on the figure of the single-cycle path provided above. The new logic for jin is drawn in red on the next page. (b) What is/are the new control signal(s) required to implement jin? Why is/are the control signal(s) necessary? We introduced one new mux, and that mux needs a -bit control signal, JIN.

6 Name: 6 JIN PC 4 Shift left 2 [3-] I [25-2] I [2-6] I [5 - ] 3 register register 2 register Reg 2 2 Registers PCSrc ALU Zero Result ALUOp Mem Data MemToReg 2 RegDst ALUSrc Mem I [5 - ] Sign extend

7 Name: 7 4. [ Points] Control Unit. PC 4 Shift left 2 [3 ] Reg I [25 2] I [2 6] register register 2 I [5 ] 2 register Registers 3 2 RegDst ALUSrc PCSrc ALU Zero Result ALUOp Mem Data Mem MemToReg 2 I [5 ] Sign extend A new I-format instruction swu has been added to the MIPS instruction set. Its format is swu rt, I(rs). It takes as arguments register rt, register rs, and immediate I, and it stores the contents of R[rt] at the (R[rs] + I) and then increments R[rs] by I. Given the single-cycle path above (control signals are marked with dashed lines), fill in the blanks in the table below for this new instruction. You must give the control signals (,, 2, X) for the MIPS instruction. Each control signal must be specified as,, 2 or X (don t care). Writing a or when an X is more accurate is not correct. Opcode RegDst Reg ALUSrc ALUOp Mem Mem MemToReg PCSrc swu add The answers appear in the table above.

8 Name: 8 5. [5 Points] Pipeline Hazards. Consider the sequence of MIPS instructions below: add \$8, \$4, \$ lw \$2, 8(\$5) sllv \$2, \$2, \$4 andi \$5, \$5, x3 sw \$5, (\$6) (a) Draw arrows from producer to consumer on the instructions above indicating all the dependences. There is a dependence between the lw and the sllv instruction via \$2, and another between the andi and the sw via \$5. (b) Reorder the instructions into a new schedule that will execute without any stalls on a 5-stage pipelined processor with forwarding. For reference, you may refer to the pipeline diagram below. We need to avoid the -cycle load-use stall between the lw and the sllv. We can simply put the add in between. lw \$2, 8(\$5) add \$8, \$4, \$ sllv \$2, \$2, \$4 andi \$5, \$5, x3 sw \$5, (\$6) (c) Reorder the instructions into a new schedule that will execute without any stalls on a 5-stage pipelined processor without forwarding. For reference, you may refer to the pipeline diagram below. The sllv has a dependence on the lw, and the sw on the andi. Since we have no forwarding, we need to allow 2 cycles between the dependent instructions, so that the producer can reach WB when the consumer is in ID. lw \$2, 8(\$5) andi \$5, \$5, x3 IF ID EX MEM WB IM ALU Reg DM Reg

9 Name: 9 add \$8, \$4, \$ sllv \$2, \$2, \$4 sw \$5, (\$6)

10 Name: 6. [5 Points] Pipelining. (a) Suppose you have a 5 stage pipeline in which the IF, ID, EX, MEM, WB stages took 3ns, 2ns, 2ns, 3ns and 2ns respectively. Explain performance impact in comparison with a single cycle implementation in each of the following scenarios. i. How long does a single instruction take in the a single-cycle implementation? ( ) = 2ns ii. How long does it take N instructions to complete in pipelining, where N is some arbitrary large number? 3*N + 2 iii. What is the speedup of pipelining? 4x speedup iv. Is that the max speedup? Why or why not? No, this is not the ideal speed-up, as the pipeline stages are not balanced. In otherwords, since the IF and MEM stages take 3ns, that will be the lenght of each stage, regardless of the fact that the other 3 stages take less time. (b) Why do pipelined machines in general offer improved performance? Pipelined machines offer better throughput because when pipeline multiple stages are utilized at the same time, pipelined machines complete one instruction in the time it takes a single stage to complete. This is faster than the time it takes for the entire processor to complete every stage before fetching a new instruction.

### CSE 378 Midterm 2/12/10 Sample Solution

Question 1. (6 points) (a) Rewrite the instruction sub \$v0,\$t8,\$a2 using absolute register numbers instead of symbolic names (i.e., if the instruction contained \$at, you would rewrite that as \$1.) sub

### CS 351 Exam 2 Mon. 11/2/2015

CS 351 Exam 2 Mon. 11/2/2015 Name: Rules and Hints The MIPS cheat sheet and datapath diagram are attached at the end of this exam for your reference. You may use one handwritten 8.5 11 cheat sheet (front

### CS 61C Fall 2016 Guerrilla Section 4: MIPS CPU (Datapath & Control)

CS 61C Fall 2016 Guerrilla Section 4: MIPS CPU (Datapath & Control) 1) If this exam were a CPU, you d be halfway through the pipeline (Sp15 Final) We found that the instruction fetch and memory stages

### CS 61C Summer 2016 Guerrilla Section 4: MIPS CPU (Datapath & Control)

CS 61C Summer 2016 Guerrilla Section 4: MIPS CPU (Datapath & Control) 1) If this exam were a CPU, you d be halfway through the pipeline (Sp15 Final) We found that the instruction fetch and memory stages

### Machine Organization & Assembly Language

Name: 1 CSE 378 Fall 2010 Machine Organization & Assembly Language Final Exam Solution Write your answers on these pages. Additional pages may be attached (with staple) if necessary. Please ensure that

### CSEN 601: Computer System Architecture Summer 2014

CSEN 601: Computer System Architecture Summer 2014 Practice Assignment 5 Solutions Exercise 5-1: (Midterm Spring 2013) a. What are the values of the control signals (except ALUOp) for each of the following

### Computer Organization and Structure

Computer Organization and Structure 1. Assuming the following repeating pattern (e.g., in a loop) of branch outcomes: Branch outcomes a. T, T, NT, T b. T, T, T, NT, NT Homework #4 Due: 2014/12/9 a. What

### CS3350B Computer Architecture Quiz 3 March 15, 2018

CS3350B Computer Architecture Quiz 3 March 15, 2018 Student ID number: Student Last Name: Question 1.1 1.2 1.3 2.1 2.2 2.3 Total Marks The quiz consists of two exercises. The expected duration is 30 minutes.

### Adding Support for jal to Single Cycle Datapath (For More Practice Exercise 5.20)

Adding Support for jal to Single Cycle Datapath (For More Practice Exercise 5.20) The MIPS jump and link instruction, jal is used to support procedure calls by jumping to jump address (similar to j ) and

### Final Exam Spring 2017

COE 3 / ICS 233 Computer Organization Final Exam Spring 27 Friday, May 9, 27 7:3 AM Computer Engineering Department College of Computer Sciences & Engineering King Fahd University of Petroleum & Minerals

### Chapter 4. The Processor. Computer Architecture and IC Design Lab

Chapter 4 The Processor Introduction CPU performance factors CPI Clock Cycle Time Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS

### Chapter 4. The Processor

Chapter 4 The Processor Introduction CPU performance factors CPI Clock Cycle Time Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS

### CS 351 Exam 2, Fall 2012

CS 351 Exam 2, Fall 2012 Your name: Rules You may use one handwritten 8.5 x 11 cheat sheet (front and back). This is the only resource you may consult during this exam. Include explanations and comments

### Full Datapath. CSCI 402: Computer Architectures. The Processor (2) 3/21/19. Fengguang Song Department of Computer & Information Science IUPUI

CSCI 42: Computer Architectures The Processor (2) Fengguang Song Department of Computer & Information Science IUPUI Full Datapath Branch Target Instruction Fetch Immediate 4 Today s Contents We have looked

### The Processor. Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut. CSE3666: Introduction to Computer Architecture

The Processor Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut CSE3666: Introduction to Computer Architecture Introduction CPU performance factors Instruction count

### ECS 154B Computer Architecture II Spring 2009

ECS 154B Computer Architecture II Spring 2009 Pipelining Datapath and Control 6.2-6.3 Partially adapted from slides by Mary Jane Irwin, Penn State And Kurtis Kredo, UCD Pipelined CPU Break execution into

### CSE 378 Midterm Sample Solution 2/11/11

Question 1. (9 points). Suppose we have the following MIPS instructions stored in memory starting at location 0x2400. 2400: add \$v0,\$t1,\$t3 2404: loop: sll \$t3,\$a2,12 2408: or \$s2,\$t3,\$a1 240c: bne \$s2,\$t8,loop

### CENG 3531 Computer Architecture Spring a. T / F A processor can have different CPIs for different programs.

Exam 2 April 12, 2012 You have 80 minutes to complete the exam. Please write your answers clearly and legibly on this exam paper. GRADE: Name. Class ID. 1. (22 pts) Circle the selected answer for T/F and

### CSCI 402: Computer Architectures. Fengguang Song Department of Computer & Information Science IUPUI. Today s Content

3/6/8 CSCI 42: Computer Architectures The Processor (2) Fengguang Song Department of Computer & Information Science IUPUI Today s Content We have looked at how to design a Data Path. 4.4, 4.5 We will design

### ECE Exam I February 19 th, :00 pm 4:25pm

ECE 3056 Exam I February 19 th, 2015 3:00 pm 4:25pm 1. The exam is closed, notes, closed text, and no calculators. 2. The Georgia Tech Honor Code governs this examination. 3. There are 4 questions and

### Lecture 4: Review of MIPS. Instruction formats, impl. of control and datapath, pipelined impl.

Lecture 4: Review of MIPS Instruction formats, impl. of control and datapath, pipelined impl. 1 MIPS Instruction Types Data transfer: Load and store Integer arithmetic/logic Floating point arithmetic Control

### EE557--FALL 1999 MAKE-UP MIDTERM 1. Closed books, closed notes

NAME: STUDENT NUMBER: EE557--FALL 1999 MAKE-UP MIDTERM 1 Closed books, closed notes Q1: /1 Q2: /1 Q3: /1 Q4: /1 Q5: /15 Q6: /1 TOTAL: /65 Grade: /25 1 QUESTION 1(Performance evaluation) 1 points We are

### CS 61C: Great Ideas in Computer Architecture. MIPS CPU Datapath, Control Introduction

CS 61C: Great Ideas in Computer Architecture MIPS CPU Datapath, Control Introduction Instructor: Alan Christopher 7/28/214 Summer 214 -- Lecture #2 1 Review of Last Lecture Critical path constrains clock

### ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 \$zero all bits are zero 16 \$s0 local variable 1 \$at assembler temporary 17 \$s1 local

### EECS150 - Digital Design Lecture 10- CPU Microarchitecture. Processor Microarchitecture Introduction

EECS150 - Digital Design Lecture 10- CPU Microarchitecture Feb 18, 2010 John Wawrzynek Spring 2010 EECS150 - Lec10-cpu Page 1 Processor Microarchitecture Introduction Microarchitecture: how to implement

### Pipeline design. Mehran Rezaei

Pipeline design Mehran Rezaei How Can We Improve the Performance? Exec Time = IC * CPI * CCT Optimization IC CPI CCT Source Level * Compiler * * ISA * * Organization * * Technology * With Pipelining We

### Department of Electrical Engineering and Computer Sciences Fall 2003 Instructor: Dave Patterson CS 152 Exam #1. Personal Information

University of California, Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences Fall 2003 Instructor: Dave Patterson 2003-10-8 CS 152 Exam #1 Personal Information First

### 4. What is the average CPI of a 1.4 GHz machine that executes 12.5 million instructions in 12 seconds?

Chapter 4: Assessing and Understanding Performance 1. Define response (execution) time. 2. Define throughput. 3. Describe why using the clock rate of a processor is a bad way to measure performance. Provide

### University of California College of Engineering Computer Science Division -EECS. CS 152 Midterm I

Name: University of California College of Engineering Computer Science Division -EECS Fall 996 D.E. Culler CS 52 Midterm I Your Name: ID Number: Discussion Section: You may bring one double-sided pages

### ELEC 5200/6200 Computer Architecture and Design Spring 2017 Lecture 4: Datapath and Control

ELEC 52/62 Computer Architecture and Design Spring 217 Lecture 4: Datapath and Control Ujjwal Guin, Assistant Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849

### CPU Organization (Design)

ISA Requirements CPU Organization (Design) Datapath Design: Capabilities & performance characteristics of principal Functional Units (FUs) needed by ISA instructions (e.g., Registers, ALU, Shifters, Logic

### Lecture 7 Pipelining. Peng Liu.

Lecture 7 Pipelining Peng Liu liupeng@zju.edu.cn 1 Review: The Single Cycle Processor 2 Review: Given Datapath,RTL -> Control Instruction Inst Memory Adr Op Fun Rt

### THE HONG KONG UNIVERSITY OF SCIENCE & TECHNOLOGY Computer Organization (COMP 2611) Spring Semester, 2014 Final Examination

THE HONG KONG UNIVERSITY OF SCIENCE & TECHNOLOGY Computer Organization (COMP 2611) Spring Semester, 2014 Final Examination May 23, 2014 Name: Email: Student ID: Lab Section Number: Instructions: 1. This

### LECTURE 5. Single-Cycle Datapath and Control

LECTURE 5 Single-Cycle Datapath and Control PROCESSORS In lecture 1, we reminded ourselves that the datapath and control are the two components that come together to be collectively known as the processor.

### COMP303 - Computer Architecture Lecture 8. Designing a Single Cycle Datapath

COMP33 - Computer Architecture Lecture 8 Designing a Single Cycle Datapath The Big Picture The Five Classic Components of a Computer Processor Input Control Memory Datapath Output The Big Picture: The

### CS2100 Computer Organisation Tutorial #10: Pipelining Answers to Selected Questions

CS2100 Computer Organisation Tutorial #10: Pipelining Answers to Selected Questions Tutorial Questions 2. [AY2014/5 Semester 2 Exam] Refer to the following MIPS program: # register \$s0 contains a 32-bit

### King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

Page 1 of 13 King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department COE 301 COMPUTER ORGANIZATION ICS 233: COMPUTER ARCHITECTURE & ASSEMBLY

### King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

Page 1 of 13 King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department COE 301 COMPUTER ORGANIZATION ICS 233: COMPUTER ARCHITECTURE & ASSEMBLY

### EECS150 - Digital Design Lecture 9- CPU Microarchitecture. Watson: Jeopardy-playing Computer

EECS150 - Digital Design Lecture 9- CPU Microarchitecture Feb 15, 2011 John Wawrzynek Spring 2011 EECS150 - Lec09-cpu Page 1 Watson: Jeopardy-playing Computer Watson is made up of a cluster of ninety IBM

### ECE 313 Computer Organization FINAL EXAM December 14, This exam is open book and open notes. You have 2 hours.

This exam is open book and open notes. You have 2 hours. Problems 1-4 refer to a proposed MIPS instruction lwu (load word - update) which implements update addressing an addressing mode that is used in

### Major CPU Design Steps

Datapath Major CPU Design Steps. Analyze instruction set operations using independent RTN ISA => RTN => datapath requirements. This provides the the required datapath components and how they are connected

### COMP2611: Computer Organization. The Pipelined Processor

COMP2611: Computer Organization The 1 2 Background 2 High-Performance Processors 3 Two techniques for designing high-performance processors by exploiting parallelism: Multiprocessing: parallelism among

### Working on the Pipeline

Computer Science 6C Spring 27 Working on the Pipeline Datapath Control Signals Computer Science 6C Spring 27 MemWr: write memory MemtoReg: ALU; Mem RegDst: rt ; rd RegWr: write register 4 PC Ext Imm6 Adder

### EE 457 Unit 6a. Basic Pipelining Techniques

EE 47 Unit 6a Basic Pipelining Techniques 2 Pipelining Introduction Consider a drink bottling plant Filling the bottle = 3 sec. Placing the cap = 3 sec. Labeling = 3 sec. Would you want Machine = Does

### CPU Design Steps. EECC550 - Shaaban

CPU Design Steps 1. Analyze instruction set operations using independent RTN => datapath requirements. 2. Select set of datapath components & establish clock methodology. 3. Assemble datapath meeting the

### Lecture 8: Control COS / ELE 375. Computer Architecture and Organization. Princeton University Fall Prof. David August

Lecture 8: Control COS / ELE 375 Computer Architecture and Organization Princeton University Fall 2015 Prof. David August 1 Datapath and Control Datapath The collection of state elements, computation elements,

### COMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor

COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle

### Single Cycle CPU Design. Mehran Rezaei

Single Cycle CPU Design Mehran Rezaei What does it mean? Instruction Fetch Instruction Memory clk pc 32 32 address add \$t,\$t,\$t2 instruction Next Logic to generate the address of next instruction The Branch

### CS 61C: Great Ideas in Computer Architecture Control and Pipelining

CS 6C: Great Ideas in Computer Architecture Control and Pipelining Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs6c/sp6 Datapath Control Signals ExtOp: zero, sign

### CS232 Final Exam May 5, 2001

CS232 Final Exam May 5, 2 Name: This exam has 4 pages, including this cover. There are six questions, worth a total of 5 points. You have 3 hours. Budget your time! Write clearly and show your work. State

### CISC 662 Graduate Computer Architecture. Lecture 4 - ISA

CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

### COMPUTER ORGANIZATION AND DESIGN. The Hardware/Software Interface. Chapter 4. The Processor: A Based on P&H

COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface Chapter 4 The Processor: A Based on P&H Introduction We will examine two MIPS implementations A simplified version A more realistic pipelined

University of California, Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences Fall 2003 Instructor: Dave Patterson 2003-10-8 CS 152 Exam #1 Personal Information First

### The Evolution of Microprocessors. Per Stenström

The Evolution of Microprocessors Per Stenström Processor (Core) Processor (Core) Processor (Core) L1 Cache L1 Cache L1 Cache L2 Cache Microprocessor Chip Memory Evolution of Microprocessors Multicycle

### Final Exam Fall 2007

ICS 233 - Computer Architecture & Assembly Language Final Exam Fall 2007 Wednesday, January 23, 2007 7:30 am 10:00 am Computer Engineering Department College of Computer Sciences & Engineering King Fahd

### CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization

CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

### Computer Organization MIPS Architecture. Department of Computer Science Missouri University of Science & Technology

Computer Organization MIPS Architecture Department of Computer Science Missouri University of Science & Technology hurson@mst.edu Computer Organization Note, this unit will be covered in three lectures.

### MIPS-Lite Single-Cycle Control

MIPS-Lite Single-Cycle Control COE68: Computer Organization and Architecture Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University Overview Single cycle

### Midterm I October 6, 1999 CS152 Computer Architecture and Engineering

University of California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz Midterm I October 6, 1999 CS152 Computer Architecture and Engineering Your Name: SID

### CS232 Final Exam May 5, 2001

CS232 Final Exam May 5, 2 Name: Spiderman This exam has 4 pages, including this cover. There are six questions, worth a total of 5 points. You have 3 hours. Budget your time! Write clearly and show your

### Laboratory Exercise 6 Pipelined Processors 0.0

Laboratory Exercise 6 Pipelined Processors 0.0 Goals After this laboratory exercise, you should understand the basic principles of how pipelining works, including the problems of data and branch hazards

### Computer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#:

Computer Science and Engineering 331 Midterm Examination #1 Fall 2000 Name: Solutions S.S.#: 1 41 2 13 3 18 4 28 Total 100 Instructions: This exam contains 4 questions. It is closed book and notes. Calculators

### The Processor: Datapath & Control

Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Processor: Datapath & Control Processor Design Step 3 Assemble Datapath Meeting Requirements Build the

### COMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor

COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition The Processor - Introduction

### MIPS%Assembly% E155%

MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage \$0 0 the constant value 0 \$at 1 assembler temporary

### The Processor Pipeline. Chapter 4, Patterson and Hennessy, 4ed. Section 5.3, 5.4: J P Hayes.

The Processor Pipeline Chapter 4, Patterson and Hennessy, 4ed. Section 5.3, 5.4: J P Hayes. Pipeline A Basic MIPS Implementation Memory-reference instructions Load Word (lw) and Store Word (sw) ALU instructions

### Chapter 4. Instruction Execution. Introduction. CPU Overview. Multiplexers. Chapter 4 The Processor 1. The Processor.

COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor The Processor - Introduction

### CS 351 Exam 2 Wed. 4/5/2017

CS 351 Exam 2 Wed. 4/5/2017 Name: Rules and Hints You may use one handwritten 8.5 11 cheat sheet (front and back). This is the only additional resource you may consult during this exam. No calculators.

### ECE 331 Hardware Organization and Design. Professor Jay Taneja UMass ECE - Discussion 3 2/8/2018

ECE 331 Hardware Organization and Design Professor Jay Taneja UMass ECE - jtaneja@umass.edu Discussion 3 2/8/2018 Study Jams Leader: Chris Bartoli Tuesday 5:30-6:45pm Elab 325 Wednesday 8:30-9:45pm Elab

### Chapter 5 Solutions: For More Practice

Chapter 5 Solutions: For More Practice 1 Chapter 5 Solutions: For More Practice 5.4 Fetching, reading registers, and writing the destination register takes a total of 300ps for both floating point add/subtract

### Comprehensive Exams COMPUTER ARCHITECTURE. Spring April 3, 2006

Comprehensive Exams COMPUTER ARCHITECTURE Spring 2006 April 3, 2006 ID Number 1 /15 2 /20 3 /20 4 /20 Total /75 Problem 1. ( 15 points) Logic Design: A three-input switching function is expressed as f(a,

### Codeword[1] Codeword[0]

Student #: ID: A CSE 221 - Quiz 3 - Fall 29 Problem 1. Convolutional encoding is commonly used on cell phones to ensure data is received with few errors using the low transmit power typically available

### Midnight Laundry. IC220 Set #19: Laundry, Co-dependency, and other Hazards of Modern (Architecture) Life. Return to Chapter 4

IC220 Set #9: Laundry, Co-dependency, and other Hazards of Modern (Architecture) Life Return to Chapter 4 Midnight Laundry Task order A B C D 6 PM 7 8 9 0 2 2 AM 2 Smarty Laundry Task order A B C D 6 PM

### CSE Quiz 3 - Fall 2009

Student #: ID: B CSE 221 - Quiz 3 - Fall 29 Problem 1. (a) Enter an appropriate value in each table cell corresponding to the Instruction in the column. Enter an X if the value is not applicable for the

### Processor (I) - datapath & control. Hwansoo Han

Processor (I) - datapath & control Hwansoo Han Introduction CPU performance factors Instruction count - Determined by ISA and compiler CPI and Cycle time - Determined by CPU hardware We will examine two

### ECE 3056: Architecture, Concurrency and Energy of Computation. Single and Multi-Cycle Datapaths: Practice Problems

ECE 3056: Architecture, Concurrency and Energy of Computation Single and Multi-Cycle Datapaths: Practice Problems 1. Consider the single cycle SPIM datapath. a. Specify the values of the control signals

### Lecture 5: Procedure Calls

Lecture 5: Procedure Calls Today s topics: Procedure calls and register saving conventions 1 Example Convert to assembly: while (save[i] == k) i += 1; i and k are in \$s3 and \$s5 and base of array save[]

### CS61C : Machine Structures

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #19 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker CS61C L19 CPU Design : Designing a Single-Cycle CPU

### Lecture 5: Procedure Calls

Lecture 5: Procedure Calls Today s topics: Memory layout, numbers, control instructions Procedure calls 1 Memory Organization The space allocated on stack by a procedure is termed the activation record

### ECE 30 Introduction to Computer Engineering

ECE 30 Introduction to Computer Engineering Study Problems, Set #3 Spring 2015 Use the MIPS assembly instructions listed below to solve the following problems. arithmetic add add sub subtract addi add

### Name: University of Michigan uniqname: (NOT your student ID number!)

The University of Michigan - Department of EECS EECS370 Introduction to Computer Organization Midterm Exam 1 October 22, 2009 Name: University of Michigan uniqname: (NOT your student ID number!) Open book,

### Midterm Questions Overview

Midterm Questions Overview Four questions from the following: Performance Evaluation: Given MIPS code, estimate performance on a given CPU. Compare performance of different CPU/compiler changes for a given

### Pipelining. lecture 15. MIPS data path and control 3. Five stages of a MIPS (CPU) instruction. - factory assembly line (Henry Ford years ago)

lecture 15 Pipelining MIPS data path and control 3 - factory assembly line (Henry Ford - 100 years ago) - car wash Multicycle model: March 7, 2016 Pipelining - cafeteria -... Main idea: achieve efficiency

### Computer Architecture I Midterm I

Computer Architecture I Midterm I April 11 2017 Computer Architecture I Midterm I Chinese Name: Pinyin Name: E-Mail... @shanghaitech.edu.cn: Question Points Score 1 1 2 12 3 16 4 14 5 18 6 17 7 22 Total:

### ECE 313 Computer Organization EXAM 2 November 11, 2000

This exam is open book and open notes. You have 50 minutes. Credit for problems requiring calculation will be given only if you show your work. 1. ALU Design / Logic Operations 20 Points The subset of

### Improving Performance: Pipelining

Improving Performance: Pipelining Memory General registers Memory ID EXE MEM WB Instruction Fetch (includes PC increment) ID Instruction Decode + fetching values from general purpose registers EXE EXEcute

### CSE 2021 COMPUTER ORGANIZATION

CSE 22 COMPUTER ORGANIZATION HUGH CHESSER CHESSER HUGH CSEB 2U 2U CSEB Agenda Topics:. Sample Exam/Quiz Q - Review 2. Multiple cycle implementation Patterson: Section 4.5 Reminder: Quiz #2 Next Wednesday

### ECE232: Hardware Organization and Design

ECE232: Hardware Organization and Design Lecture 14: One Cycle MIPs Datapath Adapted from Computer Organization and Design, Patterson & Hennessy, UCB R-Format Instructions Read two register operands Perform

### Processor Design Pipelined Processor (II) Hung-Wei Tseng

Processor Design Pipelined Processor (II) Hung-Wei Tseng Recap: Pipelining Break up the logic with pipeline registers into pipeline stages Each pipeline registers is clocked Each pipeline stage takes one

### CSc 256 Midterm 2 Fall 2011

CSc 256 Midterm 2 Fall 2011 NAME: 1a) You are given a MIPS branch instruction: x: beq \$12, \$0, y The address of the label "y" is 0x400468. The memory location at "x" contains: address contents 0x40049c

### Computer Architecture I Midterm I (solutions)

Computer Architecture I Midterm II May 9 2017 Computer Architecture I Midterm I (solutions) Chinese Name: Pinyin Name: E-Mail... @shanghaitech.edu.cn: Question Points Score 1 1 2 23 3 13 4 18 5 14 6 15

### 3/12/2014. Single Cycle (Review) CSE 2021: Computer Organization. Single Cycle with Jump. Multi-Cycle Implementation. Why Multi-Cycle?

CSE 2021: Computer Organization Single Cycle (Review) Lecture-10b CPU Design : Pipelining-1 Overview, Datapath and control Shakil M. Khan 2 Single Cycle with Jump Multi-Cycle Implementation Instruction:

### Digital Design & Computer Architecture (E85) D. Money Harris Fall 2007

Digital Design & Computer Architecture (E85) D. Money Harris Fall 2007 Final Exam This is a closed-book take-home exam. You are permitted a calculator and two 8.5x sheets of paper with notes. The exam

### ECE Exam I - Solutions February 19 th, :00 pm 4:25pm

ECE 3056 Exam I - Solutions February 19 th, 2015 3:00 pm 4:25pm 1. (35 pts) Consider the following block of SPIM code. The text segment starts at 0x00400000 and the data segment starts at 0x10010000..data

### CENG 3420 Lecture 06: Datapath

CENG 342 Lecture 6: Datapath Bei Yu byu@cse.cuhk.edu.hk CENG342 L6. Spring 27 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified to contain only: memory-reference

### CoE - ECE 0142 Computer Organization. Instructions: Language of the Computer

CoE - ECE 42 Computer Organization Instructions: Language of the Computer The Stored Program Concept The stored program concept says that the program is stored with data in the computer s memory. The computer