Computer Architecture

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1 University of Craiova Faculty of Automation, Computers & Electronics Department of Computers & Information Technology Computer Architecture Elementary Educational Computer (EEC) Cătălina Mancaș Dan Mancaș

2 Previous topics General structure of the CPU; CPU-MM transfer speed balancing techniques; Advanced organization of CPU communication: peripheral devices; I/O units; I/O processors. 2

3 The fundamental structure Data Flux de flow date Alternative Data Flow Flux de date alternativ CPU = ALU + CU Instructions Flux de instructiuni Flow Control Comenzi sau Line linii de control Status Informatii Line de stare sau linii de stare Unitatea Control de Control Unit (CU) (UC) Date de Input Data intrare si & programe Programs Unitatea Input de Intrare Unit (IU) (UI) Unitatea Arithmetic Logico- Logic Aritmeticã Unit (ALU) Date Unitatea Output de Iesire Unit (OU) (UO) Instructiuni Instructions Date de iesire Output Data sau rezultate & Results DMA Unitatea Memory de Memorie Unit (MU) (UM) DMA 3

4 General Structure of the CPU Magistrala Interna Data de Bus Date Magistrala Address Interna Bus de Adrese Bus Control Unitate Buffer/Driver Unit Magistrala System Bus Sistem ALU ALU CU UC Linii Control de Control Lines General Registre generale Registers R 1 Instruction Address Adresa Instructiune DEC k/2 k R 2 Operand Adresa Operand Address Operand Address PC incr. Bloc Control Secventiator Sequencer de Control er Processing Bloc de Procesare Block R 2 k EA Calcul Computation AE Decodificator OPCODE OPCODE Decoder Decoded Operatie decodificata Operation Status Reg. Register Stare ACC AR RA FR RF Operand Reg. Register Op. Generator Clock de tact Dispozitiv de procesare Processing Device Address Bloc de Block Adresa IR RI Instruction Bloc de Block Instructiune Linii interne de Control Linii interne de Stare 4

5 General Structure of the CPU Complex? 5

6 Today... Detailed organization of a computer; Elementary Educational Computer; General Structure; Functioning: FETCH, EXECUTE; Instructions: ADD, SUB, LOAD, STORE, JUMP, I/O. 6

7 Elementary Educational Computer The EEC conforms to the 5-unit structure defined by von Neumann's model; All units are presented in a simplified form consisting of only basic components. 7

8 Elementary Educational Computer Control Linii de control Lines R/ W UC ALU. BLOC CONTROL DE CONTROL BLOCK Flags DEPLASATOR SHIFTER SUMATOR/SCAZATOR ADDER/SUBTRACTOR SR RS (FR) RT3 RX1 DECODIFICATOR OPCODE DECODER FUNCTIE L K Incr RT2 RX2 RT1 RX3 ACC RI OPCODE ADRESA K PC K n n K UM U I/O UI UO n REGISTRU INPUT REGISTER INPUT REGISTRU OUTPUT REGISTER OUTPUT n K MAR 0... i k -1 MBR n UIA pe n biti R/ W 2 k x n 8

9 Memory Unit (MU) One level memory: the Main Memory (MM); Memory location: address on k bits; Communication with other units through: MAR Memory Address Register; MBR Memory Buffer Register or Memory Data Register. Two operations are allowed: READ and WRITE, controlled by the Control Unit. 9

10 Memory Unit (MU) 10

11 Memory Unit (MU) Organization of the memory: 2 k locations of n bits => 2 k n memory array 0 B n-1 B 1 B 0 1 i-1 i i+1 2 k

12 Memory Unit (MU) READ cycle: 1) Address is placed in MAR; 2) READ control signal is emitted; 3) Data is extracted from the addressed location; 4) Data is stored in MBR. WRITE cycle: 1) Address is placed in MAR; 2) Data is transferred in MBR; 3) WRITE control signal is emitted; 4) Data is stored in the addressed location. 12

13 Arithmetic-Logic Unit (ALU) SHIFTER Processing Device ADDER/SUBTRACTOR Local Memory 13

14 Arithmetic-Logic Unit (ALU) Implements binary arithmetic on n bits; Dimension of ALU operational units is assumed n; All registers inside ALU are n-dimensional; ALU contains: a simple register file (local memory): an Accumulator, three auxiliary registers: RX1, RX2, RX3; a Flag (Status) register (RS); a processing device: an Adder/Subtractor; a Shifter. 14

15 Arithmetic-Logic Unit (ALU) ALU performs a limited set of primitive operations; Communication between ALU and CU: CU sends the commands via control lines, ALU sends the status of the registers content (status signals, flags, condition signals), usually the Accumulator s. Possible set of status bits: zero, parity, sign, overflow etc. Operands are extracted either from register file (local memory) or from MM; Extraction from MM implies a READ cycle; Role of the Accumulator: special register communicating directly with the processing device, that contains one of the operands and where the result after processing is stored. 15

16 Control Unit (CU) The CU is formed of the following blocks: Program Counter (PC); Instruction Register (IR); Opcode (Function Decoder); Control Block (Control Sequencer). 16

17 Control Unit (CU) Control Lines CU CONTROL BLOCK OPCODE DECODER ADR 17

18 Control Unit (CU) - PC PC: contains the memory address where the next instruction to be executed is stored; Since the addressing space of MM is 2 k, the dimension of PC is k (identical with the dimension of MAR); PC has the incrementing facility, as well as a parallel load facility. 18

19 Control Unit (CU) - IR Instruction Register (IR) contains the current instruction which is in execution; IR is divided in two sub-registers according to the format of the instruction: OPCODE Sub-Register ADDRESS Sub-Register The OPCODE sub-register communicates with the OPCODE Decoder to interpret the current instruction (to decide which function must be executed). 19

20 Control Unit (CU) - IR The Address sub-register contains an address of the MM where one operand is stored; The address field contains always the effective address of the operand (not the logical address); In case of two operands operation it is assumed that the other operand is in the Accumulator; For reason of simplicity, there are missing the Function Register and the Address Register. 20

21 Control Unit (CU) Control Block The central role in the CU; a.k.a. Control Sequencer (Control Generator); Generates the control signals for the other units according to the operation (function) to be executed; The inputs in the Control Block are: the decoded (interpreted) function, master clock (from a Clock Generator), status flags (from ALU). 21

22 I/O Unit Simple I/O devices; They are communicating with: ALU (Accumulator); MM (MBR); CU (Instruction Register). Main components: Input Register; Output Register. 22

23 I/O Unit INPUT REGISTER OUTPUT REGISTER 23

24 Register Structure of EEC Any digital system can be viewed as a union of generalized registers and the data paths interconnecting them; Example: MM: 2 k locations => 2 k registers, as each location is an n-bit register; ALU + CU => CPU; The entire structure of the EEC can be reduced to a set of registers. 24

the opcode field of the instruction, on L bits yyyy = the address field of the instruction, on

25 Register Structure of EEC FR = flag register (status register), on n bits ACC = Accumulator, on n bits AX1, AX2, AX3 = auxiliary registers, on n bits IR = Instruction Register, on n bits xx = the opcode field of the instruction, on L bits yyyy = the address field of the instruction, on k bits PC = Program Counter, on k bits IU = Input unit, on n bits OU = Output unit, on n bits 25

binary coded form; Any instruction is executed in two major phases: 1.

26 EEC Functioning Acc. von Neumann's principles: both instructions and data are located in memory, in binary coded form; Any instruction is executed in two major phases: 1. FETCH: extracting the current instruction from the memory; decoding the OPCODE field. 2. EXECUTE: effective execution of the operation on the defined operands. 26

27 FETCH 2 READ UM UC CONTROL BLOC DE CONTROL BLOCK Incr MAR RI OPCODE ADRESA PC 2 MBR 3 27

28 FETCH 1) The initial address of the first instruction to be executed is already stored in PC; The content of PC is transferred to MAR; 2) CU is issuing a READ command to MM and a READ cycle is initiated; The content of the read location, representing an Instruction, is transferred to MBR; 3) From MBR the instruction is transferred to IR in CU; 4) The sub-register containing OPCODE is transferred to the Function (OPCODE) Decoder; Function (OPCODE) Decoder decodes the OPCODE and informs the Control Block of the CU, which, in turn, issues the appropriate control signals to the other units. 5) PC is incremented. 28

29 FETCH In a simplified RTL (Register Transfer Language) the FETCH phase can be described in the following form: 1. MAR (PC) 2. READ 3. IR (MBR) 4. DEC (IR) OPCODE 5. PC (PC)+1 6. Go to EXECUTE phase (IR) OPCODE : the content of the OPCODE sub-register of the IR; (PC): the content of the PC; (MBR): the content of the MBR. 29

30 FETCH CPU Memory FR AX1 READ 2 AX2 AX3 ACC zzzz x x y y y y (4.2.11) 4 IR x x y y y y 3 1 PC z z z z IU zzzz+1 5 OU 30

31 EXECUTE FETCH phase is common for all instructions; EXECUTE phase is specific for each kind of instructions; EXECUTE phase starts with extracting the operands from the memory => FETCH DATA; Therefore, EXECUTE: FETCH DATA + Actual Execution; Remember: with EEC, the Address field in the body of an Instruction represents the Effective Address (EA) of the operands (the address of the memory locations) and not the Logical Address (LA); EXECUTE is followed by FETCH of the next instruction; In what follows there are described extensively several simple instructions that are executed in EEC. 31

32 EEC Instructions - ADD The addition of two operands, where: the first operand is in the Accumulator, the second operand is in the memory at the address (yyyy), the sum is saved in the Accumulator. ACC (ACC) + (Memory) ADDRESS ; The address (yyyy) of the second operand is given in the body of the instruction (ADR field), being stored in the CU, in the (IR) ADDRESS sub-register. 32

33 EEC Instructions - ADD READ 33

34 EEC Instructions - ADD The entire operation takes place in the following steps: 1) Transfer the address field from (IR) ADDRESS into MAR transfer yyyy into MAR; 2) Initiate a READ operation from the location having the address yyyy; 3) Transfer of the extracted operand into the ALU, in register RX1; 4) Perform the addition between the contents of ACC and AX1, then store the result in the Accumulator; 5) Change the corresponding flags from the FR; 6) Go to the next FETCH phase. 34

35 EEC Instructions - ADD In RTL notation: 1) MAR (IR) ADDRESS 2) READ 3) (RX1) (Memory) ADDRESS 4) ACC (ACC) + (RX1) 5) FR New flags 6) Go to FETCH phase 35

36 EEC Instructions - SUB Subtraction operation, where: the subtrahend, i.e. the first operand: in ACC; the minuend, i.e. the second operand: in memory at the address specified explicitly in the instruction. Assumes reading from the memory the second operand and transferring it ALU, in RX1; After that, the subtraction takes place in the processing device; The difference is saved in ACC, accompanied by the corresponding changes of flags in the FR; ACC (ACC) - (Memory) ADDRESS 36

37 EEC Instructions - SUB SUBTRACTION 37

38 EEC Instructions - SUB Steps: 1) Transfer the address field from (IR) ADDRESS into MAR, which means transfer of yyyy into MAR; 2) Initiate a READ cycle, to extract the content of the location having the address yyyy; 3) Transfer of the extracted operand in ALU, in the register RX1; 4) The subtraction operation takes place in the processing device by subtracting the content of RX1 from the content of ACC; the difference is saved in the Accumulator; 5) Change the corresponding flags from the FR; 6) Go to the next FETCH phase. 38

39 EEC Instructions - LOAD Reading of an operand from the memory at the address (yyyy) specified in the instruction and transferring it into the Accumulator; ACC (Memory) ADDRESS Steps: 1. Transfer the address field from (IR) ADDRESS into MAR transfer yyyy into MAR; 2. Initiate a READ operation from the location with the address yyyy; 3. Transfer the extracted operand into the ALU, in the Accumulator and change the flags from FR. 4. Go to the next FETCH phase. 39

40 EEC Instructions - LOAD READ 40

41 EEC Instructions - LOAD If in the OPCODE there is provided a subfield specifying the destination register from the ALU, then there can be defined variants of the LOAD instruction: RX1 RX2 RX3 (Memory) ADDRESS (Memory) ADDRESS (Memory) ADDRESS 41

42 EEC Instructions - STORE The STORE Instruction ensures the transfer of the content of the Accumulator into the memory and storing it in the location having the address (yyyy) given in the instruction; ACC (Memory) ADDRESS Steps: 1. Transfer the content of the (IR) ADDRESS into the MAR; the content of MAR becomes yyyy; 2. Transfer the content of the Accumulator into the MBR; in this way the operand is prepared for further storing in the memory; 3. Initiate a WRITE operation, realising storing of the content from the MAR into the location with the address yyyy. 4. Go to the next FETCH phase. 42

43 EEC Instructions - STORE WRITE 43

44 EEC Instructions - STORE The STORE instruction can present variations by including in the OPCODE a subfield specifying the source register from ALU; in this way, the content of RX1, RX2 or RX3 can be stored in the memory at the specified address given in the instruction: (Memory) ADDRESS (Memory) ADDRESS (Memory) ADDRESS (RX1) (RX2) (RX3) 44

45 EEC Instructions JUMP (1) Unconditional JUMP at the address specified in the instruction transferring the address yyyy from the (IR) ADDRESS into the PC; Instead of using the address (zzzz+1), the address (yyyy) will be used in the next FETCH phase for extracting the next instruction from the memory.; (PC) (IR) ADDRESS Steps: 1. (PC) (IR) ADDRESS ; 2. Go to the next FETCH phase. 45

46 EEC Instructions JUMP (1) 46

47 EEC Instructions JUMP (2) Conditional JUMP tests a condition and if it is true then a jump takes place at the given address in the instruction; Otherwise the normal flow of execution continues the content of PC remains unaltered, so that the next FETCH will take place at the address (zzzz+1); If (condition) go to (address) else (zzzz+1); Steps: 1) Test the flag defined by the OPCODE; 2) If the condition is TRUE then transfer the address from (IR) ADDRESS into the PC, and go to 4); 3) If the condition is FALSE then go to 4); 4) Go to next FETCH phase. 47

48 EEC Instructions JUMP (2) 48

49 EEC Instructions JUMP (2) Test operation: checking a flag (a condition bit) from the Flag Register (FR): ZERO flag: the content of the Accumulator is 0; SIGN flag: reproducing the most significant bit of the Accumulator (0 -> a positive number is in the ACC; 1 -> a negative number is in the ACC); PARITY flag: shows if the number of 1 s in the Accumulator is odd or even; CARRY flag: if after an addition/subtraction operation it was generated a carry from the most significant column. 49

50 EEC Instructions INPUT The address field specifies one Input Register; INPUT Instruction reads the content of the addressed register and transfers it into the CPU, in the Accumulator; ACC (Input Register) ADDRESS Steps: 1. Identify the Input Register from the address stored in (IR) ADDRESS ; 2. READ the addressed Input Register and transfer its content into the ACC; 3. Go to next FETCH phase. 50

51 EEC Instructions INPUT 51

52 EEC Instructions OUTPUT The address field specifies one Output Registers representing the Output Unit; OUTPUT Instruction transfers the content of the ACC to the addressed Output Register and writes it in; (Output Register) ADDRESS ACC; Steps: 1. Identify the Output Register from the address existing in (IR) ADDRESS ; 2. Transfer the operand from ACC to the identified Output Register and write it in the register; 3. Go to next FETCH phase. 52

53 EEC Instructions OUTPUT 53

CS 265. Computer Architecture. Wei Lu, Ph.D., P.Eng.

CS 265. Computer Architecture. Wei Lu, Ph.D., P.Eng. CS 265 Computer Architecture Wei Lu, Ph.D., P.Eng. Part 3: von Neumann Architecture von Neumann Architecture Our goal: understand the basics of von Neumann architecture, including memory, control unit