ECE468 Computer Organization and Architecture. Designing a Multiple Cycle Controller

Transcription

1 ECE468 Computer Organization and Architecture Designing a Multiple Cycle Controller ECE468 multicontroller Review of a Multiple Cycle Implementation The root of the single cycle processor s problems: The cycle time has to be long enough for the slowest instruction Solution: Break the instruction into smaller steps Execute each step (instead of the entire instruction) in one cycle - Cycle time: time it takes to execute the longest step - Keep all the steps to have similar length This is the essence of the multiple cycle processor The advantages of the multiple cycle processor: Cycle time is much shorter Different instructions take different number of cycles to complete - Load takes five cycles - Jump only takes three cycles Allows a functional unit to be used more than once per instruction ECE468 multicontroller2

2 Review: Instruction Fetch Cycle, In the Beginning Every cycle begins right AFTER the clock tick: mem[pc] PC<3:> + 4 Clk You are here! One Logic Clock Cycle PCWr=? Clk PC MemWr=? RAdr Ideal WrAdr Dout Din IRWr=? Instruction Reg 4 op=? Control ECE468 multicontroller3 Clk Review: Instruction Fetch Cycle, The End Every cycle ends AT the next clock tick (storage element updates): IR <-- mem[pc] PC<3:> <-- PC<3:> + 4 Clk One Logic Clock Cycle PCWr= You are here! Clk PC MemWr= RAdr Ideal IRWr= WrAdr Din Dout Instruction Reg 4 Op = Add Control ECE468 multicontroller4 Clk

3 Putting it all together: Multiple Cycle Datapath PCWr PC PCWrCond PCSrc BrWr IorD MemWr IRWr RegDst RegWr SelA Target RAdr Ideal WrAdr Din Dout Instruction Reg Rs Rt Rt 5 5 Rd Ra Rb busa Reg File 4 Rw busw busb << Control Imm 6 ExtOp Extend MemtoReg SelB Op ECE468 multicontroller5 PCWr= PC Instruction Fetch Cycle: Overall Picture RAdr Ideal WrAdr Din Dout Instruction Reg Ifetch Op=Add : PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: s PCWrCond=x PCSrc= BrWr= IorD= MemWr= IRWr= SelA= Target busa busb Control SelB= Op=Add ECE468 multicontroller6

4 Register Fetch / Instruction Decode (Continue) busa <- Reg[rs] ; busb <- Reg[rt] ; Target <- PC + SignExt(Imm6)*4 PCWr= PC IorD=x Beq Rtype Ori RAdr ECE468 multicontroller7 PCWrCond= : MemWr= Ideal WrAdr Din Dout IRWr= Instruction Reg Op Control 6 Func 6 RegDst=x Rs Rt Rt Rd Imm 6 ExtOp= 5 5 Extend Op=Add : BrWr, ExtOp SelB= x: RegDst, PCSrc IorD, MemtoReg Others: s RegWr= Ra Rfetch/Decode Rb busa Reg File 4 Rw busw busb << 2 PCSrc=x SelA= 2 3 SelB= BrWr= Control Target Op=Add R-type Execution Output <- busa op busb RExec : RegDst SelA SelB= Op=Rtype x: PCSrc, IorD PCWr= PCWrCond= MemtoReg ExtOp PCSrc=x BrWr= IorD=x MemWr= IRWr= RegDst= RegWr= SelA= Target PC Rs Ra RAdr Rt 5 Rb busa Ideal 5 Reg File Rt 4 WrAdr Rw Din Dout Rd busw busb 2 3 << 2 Control Instruction Reg Imm Extend 6 ExtOp=x MemtoReg=x Op=Rtype SelB= ECE468 multicontroller8

5 R-type Completion Rfinish Op=Rtype R[rd] <- Output : RegDst, RegWr sela SelB= PCWr= PCWrCond= x: IorD, PCSrc ExtOp PCSrc=x BrWr= IorD=x MemWr= IRWr= RegDst= RegWr= SelA= Target PC Rs Ra RAdr Rt 5 Rb busa Ideal 5 Reg File Rt 4 WrAdr Rw Din Dout Rd busw busb 2 3 << 2 Control Instruction Reg Imm Extend 6 ExtOp=x MemtoReg= Op=Rtype SelB= ECE468 multicontroller9 Outline of Today s Lecture Review of FSM control From Finite State Diagrams to Microprogramming ABCs of microprogramming ECE468 multicontroller

6 FSM vs Microprogram Control may be designed using one of several initial representations The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique Initial Representation Finite State Diagram Microprogram Sequencing Control Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM hardwired control microprogrammed control ECE468 multicontroller 2 Initial Representation: Finite State Diagram Ifetch Op=Add Rfetch/Decode 8 BrComplete : PCWr, IRWr Op=Add Op=Sub x: PCWrCond AdrCal RegDst, Mem2R : BrWr, ExtOp beq SelB= : ExtOp Others: s SelB= x: IorD, Mem2Reg SelA x: RegDst, PCSrc RegDst, ExtOp SelB= IorD, MemtoReg : PCWrCond Op=Add lw or sw Others: s SelA PCSrc x: MemtoReg PCSrc Ori Rtype lw sw OriExec 3 RExec : RegDst SWMem SelA Op=Or : ExtOp LWmem 5 6 SelA, IorD : ExtOp SelB= : SelA Op=Rtype SelB= MemWr SelA x: PCSrc, IorD SelB= Op=Add SelB= MemtoReg x: MemtoReg x: MemtoReg Op=Add ExtOp IorD, PCSrc PCSrc x: PCSrc,RegDst MemtoReg OriFinish Rfinish : SelA 7 Op=Rtype Op=Or 4 LWwr RegWr, ExtOp MemtoReg : RegDst, RegWr sela x: IorD, PCSrc SelB= SelB= SelB= Op=Add x: IorD, PCSrc : SelA x: PCSrc ExtOp RegWr IorD ECE468 multicontroller2

7 Sequencing Control: Explicit Next State Function Control Logic Inputs O u t p u t s Multicycle Datapath Opcode State Reg Next state number is encoded just like datapath controls ECE468 multicontroller3 Logic Representative: Logic Equations Next state from current state State -> State State -> S2, S6, S8, S State 2 -> State 3 -> State 4 ->State State 5 -> State State 6 -> State 7 State 7 -> State State 8 -> State State 9-> State State -> State State -> State Alternatively, prior state & condition S4, S5, S7, S8, S9, S -> State -> State -> State 2 -> State 3 -> State 4 State2 & op = sw -> State 5 -> State 6 State 6 -> State 7 -> State 8 State & op = jmp -> State 9 -> State State -> State ECE468 multicontroller4

8 Implementation Technique: Programmed Logic Arrays Each output line the logical OR of logical AND of input lines or their complement: AND minterms specified in top AND plane, OR sums specified in bottom OR plane Op5 Op4 Op3 Op2 Op Op S3 S2 S S = 6 = = 7 = 2 = 8 = 3 = 9 = 4 = = 5 = = ECE468 multicontroller5 R = beq = lw = sw = ori = jmp = NS3 NS2 NS NS Implementation Technique: Programmed Logic Arrays Each output line the logical OR of logical AND of input lines or their complement: AND minterms specified in top AND plane, OR sums specified in bottom OR plane Op5 Op4 Op3 Op2 Op Op S3 S2 S S = 6 = = 7 = 2 = 8 = 3 = 9 = 4 = = 5 = = ECE468 multicontroller6 lw = sw = R = ori = beq = jmp = NS3 NS2 NS NS

9 Multicycle Control Given numbers of FSM, can turn determine next state as function of inputs, including current state Turn these into Boolean equations for each bit of the next state lines Can implement easily using PLA What if many more states, many more conditions? What if need to add a state? ECE468 multicontroller7 Sequencer and Microprogramming Initial Representation Finite State Diagram Microprogram Sequencing Control Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM hardwired control microprogrammed control ROM can be thought of as a sequence of control words Control word can be thought of as instruction: microinstruction Rather than program in binary, use assembly language ECE468 multicontroller8

10 Sequencer-based control unit Control Logic Outputs Multicycle Datapath Adder Inputs State Reg ROM & Addr Select Types of branching Set state to Dispatch (state & 2) Use incremented state number Opcode ECE468 multicontroller9 Sequencer-based control unit details Adder Address Select Logic Control Logic Inputs State Reg 3 2 ROM2 Opcode ROM Dispatch ROM Op Name State Rtype jmp beq ori lw sw Dispatch ROM 2 Op Name State lw sw ECE468 multicontroller2

11 Designing a Microinstruction Set Start with list of control signals Group signals together that make sense: called fields Places fields in some logical order ( operation & operands first and microinstruction sequencing last) Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals To minimize the width, encode operations that will never be used at the same time ECE468 multicontroller2 Start with list of control signals, grouped into fields Signal name Effect when deasserted Effect when asserted SelA st operand = PC st operand = Reg[rs] RegWrite None Reg is written MemtoReg Reg write data input = Reg write data input = memory RegDst Reg dest no = rt Reg dest no = rd TargetWrite None Target reg = MemRead None at address is read MemWrite None at address is written IorD address = PC address = IRWrite None IR = PCWrite None PC = PCSource PCWriteCond None IF zero then PC = PCSource Signal name Value Effect Op adds subtracts does function code does logical OR SelB 2nd input = Reg[rt] 2nd input = 4 2nd input = sign extended IR[5-] 2nd input = sign extended, shift left 2 IR[5-] 2nd input = zero extended IR[5-] PCSource PC = PC = Target PC = PC+4[29-26] : IR[25 ] << 2 ECE468 multicontroller22

12 Start with list of control signals, cont d For next state function (next microinstruction address), use Sequencer-based control unit from last lecture Signal Value Effect Sequen Next µaddress = -cing Next µaddress = dispatch ROM Next µaddress = dispatch ROM 2 Next µaddress = µaddress + Adder Address Select Logic State Reg ROM2 ROM Opcode ECE468 multicontroller23 Microinstruction Format Field Name Width Control Signals Set Control 2 Op SRC SelA SRC2 3 SelB Destination 4 RegWrite, MemtoReg, RegDst, TargetWrite 3 MemRead, MemWrite, IorD Register IRWrite PCWrite Control 3 PCWrite, PCWriteCond, PCSource Sequencing 2 AddrCtl Total 9 ECE468 multicontroller24

13 Legend of Fields and Symbolic Names Field Name Values for Field Function of Field with Specific Value Add adds Subt subtracts Func code does function code Or does logical OR SRC PC st input = PC rs st input = Reg[rs] SRC2 4 2nd input = 4 Extend 2nd input = sign ext IR[5- Extend 2nd input = zero ext IR[5-] Extshft 2nd input = sign ex, sl IR[5-] rt 2nd input = Reg[rt] destination Target Target = rd Reg[rd] = Read PC Read memory using PC Read Read memory using output Write Write memory using output register IR IR = Mem Write rt Reg[rt] = Mem Read rt Mem = Reg[rt] PC write PC = output Target-cond IF then PC = Target jump addr PC = PCSource Sequencing Seq Go to sequential µinstruction Fetch Go to the first microinstruction Dispatch i Dispatch using ROMi ( or 2) ECE468 multicontroller25 Microprogram Label SRC SRC2 Dest Mem Reg PC Write Sequencing Fetch Add PC 4 Read PC IR Seq Add PC Extshft Target Dispatch LWSWAdd rs Extend Dispatch 2 LW2 Add rs Extend Read Seq Add rs Extend Read Write rt Fetch SW2 Add rs Extend Write Read rt Fetch Rtype Func rs rt Seq Func rs rt rd Fetch BEQ Subt rs rt Target cond Fetch JUMP jump address Fetch ORI Or rs Extend Seq Or rs Extend rd Fetch ECE468 multicontroller26

14 Implementing Control with a ROM Instead of a PLA, use a ROM with one word per state ( Control word ) State number Control Word Bits 8-2 Control Word Bits ECE468 multicontroller27 Macroinstruction Interpretation Main execution unit ADD SUB AND DATA User program plus Data this can change! one of these is mapped into one of these CPU control memory AND microsequence eg, Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) ECE468 multicontroller28

15 Extreme Horizontal 3 N3 N2 N N input select bit for each loadable register enbmar enbac Incr PC control Depending on bus organization, many potential control combinations simply not wrong, ie, implies transfers that can never happen at the same time Makes sense to encode fields to save ROM space Example: gate Rx and gate Ry to same bus should never happen encoded in single bit which is decoded rather than two separate bits NOTE: encoding should be just sufficient that parallel actions that the datapath supports should still be specifiable in a single microinstruction ECE468 multicontroller29 Horizontal vs Vertical Microprogramming Most microprogramming-based controllers vary between: horizontal organization ( control bit per control point) vertical organization (fields encoded in the control memory and must be decoded to control something) Horizontal + more control over the potential parallelism of operations in the datapath - uses up lots of control store Vertical + easier to program, not very different from programming a RISC machine in assembly language - extra level of decoding may slow the machine down ECE468 multicontroller3

16 MIR Controller Implementation reg xfer enb D S T ld A ld B enb S R C gateir gatepc A B Op enb enbenb x Branch 2 ECE468 multicontroller3 M U X ld cnt clr AC upc from rest of microword, perhaps concatenated or passed thru the (PC relative) clk Hierarchy of States Not all critical control information is derived from control logic Eg, IR contains useful control information, such as register sources, destinations, opcodes, etc enable signals from control R S D E C R S 2 D E C R D D E C Register File IR to control op rs rs2 rd ECE468 multicontroller

17 Microprogramming Pros and Cons Ease of design Flexibility Easy to adapt to changes in organization, timing, technology Can make changes late in design cycle, or even in the field Can implement very powerful instruction sets (just more control memory) Generality Can implement multiple instruction sets on same machine Can tailor instruction set to application Compatibility Many organizations, same instruction set Costly to implement Slow ECE468 multicontroller33 Summary: Multicycle Control Microprogramming and hardwired control have many similarities, perhaps biggest difference is initial representation and ease of change of implementation, with ROM generally being easier than PLA Initial Representation Finite State Diagram Microprogram Sequencing Control Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM hardwired control microprogrammed control ECE468 multicontroller34