Project Description EEC 483 Computer Organization, Spring 2019

Transcription

1 Project Description EEC 483 Computer Organization, Spring 2019 Title: Implement a (single-cycle) MIPS processor on Altera DE10-Lite using Quartus and VHDL Goal: This project is designed to help understand the architecture and operation principles of modern microprocessors. Objective: Your team (2 people) will design and implement a single-cycle MIPS processor using VHDL and Quartus on the Altera DE10-Lite system, which performs a subset of MIPS instructions (add, sub, slt, and, or, nor, lw, sw, beq, bne, j). Overview: This project aims at designing a MIPS processor. The ALU control and main control blocks are designed in Project #1 and Project #2. This is extended to the complete implementation of a single-cycle implementation of MIPS CPU in Project #3 and Project #4. Due dates: Project #1, Due Thursday, Feb 7 Project #2, Due Thursday, Feb 28 (Project presentation) Project #3, Due Thursday, Apr 11 Project #4, Due Thursday, May 2 (Final presentation)

2 Project #2: (Thursday, Feb 28) Implement a main control circuit and an ALU control that supports add, sub, slt, and, or, lw, and sw instructions. Implement the MIPS architecture with an emphasis on interfacing with DM (data memory) and Registers. Step 1: Building control circuit (mips.vhd) Implement the main control circuit of the MIPS CPU (mips.vhd). o More specifically, implement control signals such as RegDst, ALUSrc, MemtoReg, RegWrite, MemWrite and ALUOp(1:0), which will be based on the 6-bit opcode of the instruction, instruction_mips(31:26) or opcode(5:0). o The implementation in fact is to figure out a Boolean expression for each of the control signal. For example, how do you express RegDst in terms of opcode(0) ~ opcode(5)? o Hint: You do not have to use the K-map method because there are so many don t cares. The following table shows the signals for the control circuit. Refer Section C.5 and Figure C.5.12 (which is a summary of Figures C.5.1 through C.5.11) for details main control circuit (see Fig. 4.18) input derived signals Instruct opcode RegDst ALUSrc MemtoReg RegWrite MemWrite ALUOp(1:0) add sub slt and or nor (N/A) lw sw x 1 x ***The following 3 instructions are not the scope this project, but it is better to take them into considertation when developing Boolean expressions for the control signals. beq x 0 x bne x 0 x j x x x 0 0 xx Note: You must declare some signals. Please see below as an example. signal opcode: std_logic_vector(5 downto 0); signal RegDst, ALUSrc, MemtoReg, MemWrite, RegWrite: std_logic; signal ALUOp: std_logic_vector(1 downto 0); Note: MemRead control is not used because we use asynchronous read. of memory in this implementation. (Please read the Appendix B. CLOCK in the below for details.) Note: Branch control signal is not used because it is beyond of the scope of Project #2.

3 Step 2: Building an ALU control circuit (mips.vhd) In Project #1, ALU control signal (ALUctl) has been generated based on opcode and function code. But here is a more structured (and simpler) method.(mips.vhd) Implement the ALU control circuit of the MIPS CPU (mips.vhd). o More specifically, implement ALU control signals ALUctl(3:0) based on ALUOp(1:0) and 6-bit function of the instruction (func). o ALUOp(1:0) come from the main control circuit in Step 1 and func(5:0) come from the instruction, instruction_mips(5:0). o The implementation is in fact to figure out a Boolean expression for each of the control signal. For example, how do you express ALUctl(3) in terms of ALUOp(1:0) and func(5:0)? o Hint: You do not have to use the K-map method because there are so many don t cares. Here are the signals for the ALU control circuit. Refer Section C.5 and Figure C.5.12 (which is a summary of Figures C.5.1 through C.5.11) for details bit ALU with and/or/less-than support (see Fig. 4.13) Inputs: ALUOp, Func Outputs: ALUctl ALU control logic input input derived signals Instruct ALUOp Func[5:0] ALUctl add sub slt and or nor (N/A) lw/sw 00 xxxxxx 0010 ***The following 2 instructions are not the scope this project, but it is better to take them into considertation when developing Boolean expressions for the control signals beq/bne 01 xxxxxx You must declare some signals. Please see below as an example. signal func: std_logic_vector(5 downto 0);

4 Step 3: Use Control Signals to Make connections among the Components (mips.vhd) opcode(5:0) = instruction_mips (31:26) RegDst ALUSrc MemtoReg RegWrite MemWrite MemRead Used to control 3 multiplexors in mips.vhd -- Used in mips.vhd (done) -- used in data_memory_64b.vhd (done) -- Not used in this implementation func(5:0) = instruction_mips(5:0) ALUOp(1:0) ALUctl(3:0) -- Used in alu.vhd (done in Project#1) Implement 3 multiplexors, each of which is controlled by 3 control signals, RegDst, ALUSrc, and MemtoReg, respectively. 4-bit ALU control signal (ALUctl(3:0)) has already been connected to alu_32 module (Step 2). No additional work is needed as long as you generate these four control signals correctly. RegWrite and MemWrite enables writing to register or memory, which has already been implemented in mips.vhd and data_memory_64b.vhd, respectively (Step 1). No additional work is needed as long as you generate these two control signals correctly. Step 4: Interfacing Data Memory (mips.vhd) Operands may come from data memory. o You need to compute memory address (in case of LW and SW instruction). o For that matter, you need to use the 16-bit offset from the instruction, which is available in mips.vhd by the signal name, instruction_mips(15 down to 0). o This goes through sign-extend that copies MSB of the 16-bit input 16 times to make up the 32-bit output (mips.vhd). Interfacing data memory: o Mips (mips.vhd) gives information to Data memory (data_memory_ 64B.vhd) via three signals: memory_in_mips <= ; -- DM data to be written ( sw instruction) memory_address_mips <= ; -- DM address to be read/written ( lw & sw ) memory_write_mips <= ; -- MemWrite control signal ( sw instruction) o Mips (mips.vhd) takes information to Data memory (data_memory_64b. vhd) via one signal: <= memory_out_mips ; -- DM data read from DM and is being written -- to the destination register ( lw )

5 Step 4: Testing To test your design, you ll use a MIPS machine code program in the instruction memory module (inst_mem_128b_rev). Description of the test program and the expected results are in Appendix C. You can test your design using your own programs. To generate machine code, you can get some help from, e.g., Just type your assembly program such as add $1, $2, $3, it will output machine code for you. It allows comments as well as labels. Appendix A: Register file in mips.vhd o Register file consisting of 32 registers, each of which is 32-bits, is implemented in mips.vhd. Note that it supports asynchronous read and synchronous write. (Please read the Appendix B. CLOCK in the below for details.) They are normally initialized to zero but may be set to different values for testing purpose. $0=0 absolute zero $4=4 used to increment memory address $5=0x84 -- data memory address that contains two operands $6=0x8c -- base address that stores the operation results $7=1 -- for incrementing register data o Two operands to the ALU were hard-coded in Project #1. Now, in Project #2, they come from registers (in case of Add, Sub, And, Or, or Slt instruction) or 16- bit offset of the instruction (in case of Lw or Sw instruction). The 16-bit offset is available in mips.vhd by the signal name, instruction_mips(15 down to 0). Appendix B: CLOCK o For all storage elements inside and outside our CPU (instruction memory, data memory, PC, registers, etc.), we will assume that reads are done using combinational logic (asynchronous read, i.e., we can read at any time we wish) but changes (writing) happen only at the rising edge of the clock. o Our implementation will be such that instruction execution will commence immediately after the rising edge of the clock and that all necessary values are computed during the clock cycle using combinatorial logic. The final state changes (in registers, PC, and data memory) will happen at the very end just when the next rising edge occurs (synchronous write). o Notice that in between two consecutive rising edges of the clock, the signals of the datapath and the control will have values which may be incorrect. For example, in the beginning of a clock cycle, PC just gets updated (e.g., PC+4). At that instance, CPU has not read the instruction memory yet and thus the correct 32-bit instruction is not available yet. Thus, the register file may have been reading arbitrary registers and the ALU may have been producing arbitrary results. o This is OK as it does not change any storage elements (registers, PC, or data memory). Eventually, once it gets the correct 32-bit instruction word, the register file will see the right register numbers on its inputs and will after a

6 while produce the correct values on its outputs. Because the control will eventually produce the appropriate values for all control signals we will eventually see the appropriate results out of the ALU, or from or to memory. o The key to making the whole thing work correctly is that no storage element will change prior to the next rising edge of the clock. Thus, if we make the clock slow enough there will be sufficient time to produce all appropriate values and then make the correct updates instantaneously. o Above-mentioned comments are borrowed from the following webpage: Appendix C: Test Program Here is the description of the test program in inst_mem_128b.vhd: o Cycle 1, 2: The test program first reads two data from DM (memory address 0($5) & 4($5), where $5=0x84) into $2 and $3, respectively. Since memory addresses are 0($5) and 4($5), respectively, and $5=0x84, it reads from memory location 0x84 & 0x88. Converting it decimal and dividing it by 4 gives you 33 & 34. In data_memory_64b.vhd, you can notice that the two data are 0xc000 0ff0 and 0x , respectively. o Cycle 3-7: Then, it performs add, 2 sub s, 2 slt s operations using the two operands ($2 and $3). o Cycle 8-17: Results of the operations are saved into DM using 5 sw instructions. And then they are read again using 5 lw instructions. Since memory addresses are 0($6) ~ 16($6) and $6=0x8c, it reads/ writes from/to memory location 0x8c ~ 0x9c. What you should observe during the execution of the test program is: o At default, HEX/LED shows ALUOut (=> memory_address) when sw(0)=0. When sw(0)=1, it shows PC. o During cycle 1 & 2, ALU computes the memory address and is shown on HEX/LED; thus you should observe 0x84 and 0x88. o During cycle 3-7, ALU performs the corresponding arithmetic operations. You should observe 0x (add), 0x3fff ffe0 (sub), 0xc (sub), 1 (slt) and 0 (slt) o During cycle 8-12, ALU computes the memory address and is shown on HEX/LED; thus you should observe 0x8c ~ 0x9c. o During cycle 13-17, ALU computes the memory address and is shown on HEX/LED; thus you should observe 0x8c ~ 0x9c.

7 Submission (Due Feb 28) Submit a report which must 1. Describe Boolean expressions for each of the 7 control signals in Step 1. (1 point) 2. Include the section of VHDL code (mips.vhd) for the 7 control signals. (1 point) 3. Describe Boolean expressions for each of the 4 ALU control signal in Step 2. (1 point) 4. Include the section of VHDL code (mips.vhd) for the 4 ALU control signals. (1 point) 5. Include the section of VHDL code (mips.vhd) that uses the three multiplexor signals in Step 3. (1 point) 6. Describe how you implement sign_extend in Step 4. (1 point) 7. Include the section of VHDL code (mips.vhd) for memory interfacing in Step 4 memory_in_mips, memory_address_mips, memory_write_mips, and memory_out_mips. (2 point) 8. Explicitly mention if your design works, partially works, or is not completed yet. (2 points) Submit your VHDL code. (Just the vhdl files only. Do not send me the whole directory.) You should send me a 2-min video demonstration. Show the code briefly and show it compiles/ downloads properly as well as executes properly. (10 points)