Digital Design: An Embedded Systems Approach Using VHDL

Transcription

1 igital esign: An Embedded Systems Approach Using Chapter 4 Sequential Basics Portions of this work are from the book, igital esign: An Embedded Systems Approach Using, by Peter J. Ashenden, published by Morgan Kaufmann Publishers, Copyright 27 Elsevier Inc. All rights reserved. Sequential Basics Sequential circuits Outputs depend on current inputs and previous inputs Store state: an abstraction of the history of inputs Usually governed by a periodic clock signal igital esign Chapter 4 Sequential Basics 2

2 -Flipflops -bit storage element We will treat it as a basic component Other kinds of flipflops SR (set/reset), JK, T (toggle) igital esign Chapter 4 Sequential Basics 3 Registers Store a multi-bit encoded value One -flipflop per bit Stores a new value on each clock cycle d() q() signal d, q:...;... reg: process () is if rising_edge() then q <= d; end process reg; sensitivity list d() d(n) n n q() q(n) igital esign Chapter 4 Sequential Basics 4 2

3 Pipelines Using Registers Total delay = elay + elay 2 + elay 3 Interval between outputs > Total delay d_in combinational circuit combinational circuit 2 combinational circuit 3 d_out d_in combinational circuit combinational circuit 2 combinational circuit 3 d_out Clock period = max(elay, elay 2, elay 3 ) Total delay = 3 clock period Interval between outputs = clock period igital esign Chapter 4 Sequential Basics 5 Pipeline Example Compute the average of corresponding numbers in three input streams New values arrive on each clock edge library ieee; use ieee.std_logic_64.all, ieee.fixed_pkg.all; entity average_pipeline is port ( : in std_logic; a, b, c : in sfixed(5 downto -8); avg : out sfixed(5 downto -8) ); end entity average_pipeline; igital esign Chapter 4 Sequential Basics 6 3

4 Pipeline Example architecture rtl of average_pipeline is signal a_plus_b, sum, sum_div_3 : sfixed(5 downto -8); signal saved_a_plus_b, saved_c, saved_sum : sfixed(5 downto -8); a_plus_b <= a + b; reg : process () is if rising_edge() then saved_a_plus_b <= a_plus_b; saved_c <= c; end process reg;... igital esign Chapter 4 Sequential Basics 7 Pipeline Example sum <= saved_a_plus_b + saved_c; reg2 : process () is if rising_edge() then saved_sum <= sum; end process reg2; sum_div_3 <= saved_sum * to_fixed(./3., sum_div_3'left, sum_div_3'right); reg3 : process () is if rising_edge() then avg <= sum_div_3; end process reg3; end architecture average_pipeline; igital esign Chapter 4 Sequential Basics 8 4

5 -Flipflop with Enable Storage controlled by a clock-enable stores only when = on a rising edge of the clock is a synchronous control input igital esign Chapter 4 Sequential Basics 9 Register with Enable One flipflop per bit and wired in common signal d, q:...;... reg: process () is if rising_edge() then if ce = '' then q <= d; end process reg; igital esign Chapter 4 Sequential Basics 5

6 Register with Synchronous Reset Reset input forces stored value to reset input must be stable around rising edge of reset reset igital esign Chapter 4 Sequential Basics Synch Reset in single-bit data flipflop: process () is if rising_edge() then if reset = '' then q <= ''; elsif ce = '' then q <= d; end process flipflop; vector data reg: process () is if rising_edge() then if reset = '' then q <= ""; elsif ce = '' then q <= d; end process reg; igital esign Chapter 4 Sequential Basics 2 6

7 Register with Asynchronous Reset Reset input forces stored value to reset can become at any time, and effect is immediate reset should return to synchronously reset reset igital esign Chapter 4 Sequential Basics 3 Asynch Reset in reg: process (, reset) is if reset = '' then q <= ""; elsif rising_edge() then if ce = '' then q <= d; end process reg; reset is an asynchronous control input here include it in the sensitivity list so that the process responds to changes immediately igital esign Chapter 4 Sequential Basics 4 7

8 Example: Accumulator Sum a sequence of signed numbers A new number arrives when data_en = Clear sum to on synch reset library ieee; use ieee.std_logic_64.all, ieee.numeric_std.all; entity accumulator is port (, reset, data_en : in std_logic; data_in : in signed(5 downto ); data_out : out signed(9 downto ) ); end entity accumulator; igital esign Chapter 4 Sequential Basics 5 Example: Accumulator architecture rtl of accumulator is signal sum, new_sum : signed(9 downto ); new_sum <= sum + resize(data_in, sum'length); reg: process () is if rising_edge() then if reset = '' then sum <= (others => ''); elsif data_en = '' then sum <= new_sum; end process reg; data_out <= sum; end architecture rtl; igital esign Chapter 4 Sequential Basics 6 8

9 Flipflop and Register Variations pre clr library ieee; use ieee.std_logic_64.all; entity flipflop_n is port ( _n,, pre_n, clr_n, : in std_logic;, _n : out std_logic ); end entity flipflop_n; architecture behavour of flipflop_n is ff: process (_n, pre_n, clr_n) is assert not ( pre_n = '' and clr_n = '') report "Illegal inputs:" & "pre_n and clr_n both ''"; if pre_n = '' then <= ''; _n <= ''; elsif clr_n = '' then <= ''; _n <= ''; elsif falling_edge(_n) then if = '' then <= ; _n <= not ; end process ff; end architecture behavour; igital esign Chapter 4 Sequential Basics 7 Shift Registers Performs shift operation on stored data Arithmetic scaling Serial transfer of data _in (n ) (n ) _in load_en (n 2) () load_en (n 2) () igital esign Chapter 4 Sequential Basics 8 9

10 Example: Sequential Multiplier 6 6 multiply over 6 clock cycles, using one adder Shift register for multiplier bits Shift register for lsb s of accumulated product y(5...) y_load_en y_ce x(5...) x_ce P_reset P_ce 6-bit shift reg _in load_en 6-bit reg 6-bit adder x c6 y c s bit reg reset 5-bit shift reg _in P(3...5) 5 P(4...) igital esign Chapter 4 Sequential Basics 9 Latches Level-sensitive storage ata transmitted while enable is '' transparent latch ata stored while enable is '' LE LE igital esign Chapter 4 Sequential Basics 2

11 Feedback Latches Feedback in gate circuits produces latching behavior Example: reset/set (RS) latch +V S R R S Current RTL synthesis tools don t accept models with unclocked feedback igital esign Chapter 4 Sequential Basics 2 Latches in Latching behavior is usually an error! mux_block : process (sel, a, b, a2, b2) is if sel = '' then z <= a; z2 <= b; else z <= a2; z3 <= b2; end process mux_block; Values must be stored for z2 while sel = '' for z3 while sel = '' Oops! Should be z2 <=... igital esign Chapter 4 Sequential Basics 22

12 Counters Stores an unsigned integer value increments or decrements the value Used to count occurrences of events repetitions of a processing step Used as timers count elapsed time intervals by incrementing periodically igital esign Chapter 4 Sequential Basics 23 Free-Running Counter + Increments every rising edge of up to 2 n, then wraps back to i.e., counts modulo 2 n This counter is synchronous all outputs governed by clock edge igital esign Chapter 4 Sequential Basics 24 2

13 Example: Periodic Control Signal Count modulo 6 clock cycles Control output = '' every 8 th and 2 th cycle decode count values and + ctrl igital esign Chapter 4 Sequential Basics 25 Example: Periodic Control Signal library ieee; use ieee.std_logic_64.all, ieee.numeric_std.all; entity decoded_counter is port ( : in std_logic; ctrl : out std_logic ); end entity decoded_counter; architecture rtl of decoded_counter is signal count_value : unsigned(3 downto ); counter : process () is if rising_edge() then count_value <= count_value + ; end process counter; ctrl <= '' when count_value = "" or count_value = "" else ''; end architecture rtl; igital esign Chapter 4 Sequential Basics 26 3

14 Count Enable and Reset Use a register with control inputs + reset reset Increments when = '' on rising clock edge Reset: synch or asynch igital esign Chapter 4 Sequential Basics 27 Terminal Count Status signal indicating final count value counter n TC TC is '' for one cycle in every 2 n cycles frequency = clock frequency / 2 n Called a clock divider igital esign Chapter 4 Sequential Basics 28 4

15 ivider Example Alarm clock beep: 5Hz from MHz clock -bit counter TC count tone2 tone count tone2 tone igital esign Chapter 4 Sequential Basics 29 ivide by k ecode k as terminal count and reset counter register Counter increments modulo k Example: decade counter Terminal count = 9 counter 2 reset igital esign Chapter 4 Sequential Basics 3 5

16 ecade Counter in library ieee; use ieee.std_logic_64.all, ieee.numeric_std.all; entity decade_counter is port ( : in std_logic; q : out unsigned(3 downto ) ); end entity decade_counter; architecture rtl of decade_counter is signal count_value : unsigned(3 downto ); count : process () is if rising_edge() then count_value <= (count_value + ) mod ; end process count; q <= count_value; end architecture rtl; igital esign Chapter 4 Sequential Basics 3 own Counter with Load Load a starting value, then decrement Terminal count = Useful for interval timer load =? TC igital esign Chapter 4 Sequential Basics 32 6

17 Loadable Counter in library ieee; use ieee.std_logic_64.all, ieee.numeric_std.all; entity interval_timer is port (, load : in std_logic; data : in unsigned(9 downto ); tc : out std_logic); end entity interval_timer; architecture rtl of interval_timer is signal count_value : unsigned(9 downto ); count : process () is if rising_edge() then if load = '' then count_value <= data; else count_value <= count_value - ; end process count; tc <= '' when count_value = else ''; end architecture rtl; igital esign Chapter 4 Sequential Basics 33 Reloading Counter in architecture repetitive of interval_timer is signal load_value, count_value : unsigned(9 downto ); count : process () is if rising_edge() then if load = '' then load_value <= data; count_value <= data; elsif count_value = then count_value <= load_value; else count_value <= count_value - ; end process count; tc <= '' when count_value = else ''; end architecture repetitive; igital esign Chapter 4 Sequential Basics 34 7

18 Ripple Counter Each bit toggles between and when previous bit changes from to 2 n 2 2 igital esign Chapter 4 Sequential Basics 35 Ripple or Synch Counter? Ripple counter is ok if length is short clock period long relative to flipflop delay transient wrong values can be tolerated area must be minimal E.g., alarm clock Otherwise use a synchronous counter igital esign Chapter 4 Sequential Basics 36 8

19 atapaths and Control igital systems perform sequences of operations on encoded data atapath Combinational circuits for operations Registers for storing intermediate results Control section: control sequencing Generates control signals Selecting operations to perform Enabling registers at the right times Uses status signals from datapath igital esign Chapter 4 Sequential Basics 37 Example: Complex Multiplier Cartesian form, fixed-point operands: 4 pre-, 2 post-binary-point bits result: 8 pre-, 24 post-binary-point bits Subject to tight area constraints a = a r + ja i b = b r + jbi p = ab = p + jp = a b a b ) + j( a b + r i ( r r i i r i aibr 4 multiplies, add, subtract Perform sequentially using multiplier, adder/subtracter igital esign Chapter 4 Sequential Basics 38 ) 9

20 Complex Multiplier atapath a_r a_i a_sel b_r b_i b_sel pp_ce pp2_ce ± p_r p_i sub p_r_ce p_i_ce igital esign Chapter 4 Sequential Basics 39 Complex Multiplier in library ieee; use ieee.std_logic_64.all, ieee.fixed_pkg.all; entity multiplier is port (, reset : in std_logic; input_rdy : in std_logic; a_r, a_i, b_r, b_i : in sfixed(3 downto -2); p_r, p_i : out sfixed(7 downto -24) ); end entity multiplier; architecture rtl of multiplier is signal a_sel, b_sel, pp_ce, pp2_ce, sub, p_r_ce, p_i_ce : std_logic; -- control signals signal a_operand, b_operand : sfixed(3 downto -2); signal pp, pp, pp2, sum : sfixed(7 downto -24);... igital esign Chapter 4 Sequential Basics 4 2

21 Complex Multiplier in a_operand <= a_r when a_sel = '' else a_i; -- mux b_operand <= b_r when b_sel = '' else b_i; -- mux pp <= a_operand * b_operand; -- multiplier pp_reg : process () is -- partial product register if rising_edge() then if pp_ce = '' then pp <= pp; end process pp_reg; pp2_reg : process () is -- partial product register 2 if rising_edge() then if pp2_ce = '' then pp2 <= pp; end process pp2_reg; igital esign Chapter 4 Sequential Basics 4 Complex Multiplier in sum <= pp + pp2 when sub = '' else pp - pp2; -- add/sub p_r_reg : process () is -- result real-part register if rising_edge() then if p_r_ce = '' then p_r <= sum; end process p_r_reg; p_i_reg : process () is -- result imag-part register if rising_edge() then if p_i_ce = '' then p_i <= sum; end process p_i_reg; control circuit end architecture rtl; igital esign Chapter 4 Sequential Basics 42 2

22 Multiplier Control Sequence Avoid resource conflict First attempt. a_r * b_r pp_reg 2. a_i * b_i pp2_reg 3. pp pp2 p_r_reg 4. a_r * b_i pp_reg 5. a_i * b_r pp2_reg 6. pp + pp2 p_i_reg Takes 6 clock cycles igital esign Chapter 4 Sequential Basics 43 Multiplier Control Sequence Merge steps where no resource conflict Revised attempt. a_r * b_r pp_reg 2. a_i * b_i pp2_reg 3. pp pp2 p_r_reg a_r * b_i pp_reg 4. a_i * b_r pp2_reg 5. pp + pp2 p_i_reg Takes 5 clock cycles igital esign Chapter 4 Sequential Basics 44 22

23 Multiplier Control Signals Step a_sel b_sel pp_ce pp2_ce sub p_r_ce p_i_ce igital esign Chapter 4 Sequential Basics 45 Finite-State Machines Used the implement control sequencing Based on mathematical automaton theory A FSM is defined by set of inputs: Σ set of outputs: Γ set of states: S initial state: s S transition function: δ: S Σ S output function: ω: S Σ Γ or ω: S Γ igital esign Chapter 4 Sequential Basics 46 23

24 FSM in Hardware reset reset current_state next state logic inputs output logic outputs Mealy FSM only Mealy FSM: ω: S Σ Γ Moore FSM: ω: S Γ igital esign Chapter 4 Sequential Basics 47 FSM Example: Multiplier Control One state per step Separate idle state? Wait for input_rdy = '' Then proceed to steps, 2,... But this wastes a cycle! Use step as idle state Repeat step if input_rdy '' Proceed to step 2 otherwise Output function efined by table on slide 43 Moore or Mealy? current_ state step step step2 step3 step4 step5 Transition function input_ rdy next_ state step step2 step3 step4 step5 step igital esign Chapter 4 Sequential Basics 48 24

25 State Encoding Encoded in binary N states: use at least log 2 N bits Encoded value used in circuits for transition and output function encoding affects circuit complexity Optimal encoding is hard to find CA tools can do this well One-hot works well in FPGAs Often use... for idle state reset state register to idle igital esign Chapter 4 Sequential Basics 49 FSMs in Use an enumeration type for state values abstract, avoids specifying encoding type multiplier_state is (step, step2, step3, step4, step5); signal current_state, next_state : multiplier_state;... igital esign Chapter 4 Sequential Basics 5 25

26 Multiplier Control in state_reg : process (, reset) is if reset = '' then current_state <= step; elsif rising_edge() then current_state <= next_state; end process state_reg; next_state_logic : process (current_state, input_rdy) is case current_state is when step => if input_rdy = '' then next_state <= step; else next_state <= step2; when step2 => next_state <= step3; when step3 => next_state <= step4; when step4 => next_state <= step5; when step5 => next_state <= step; end case; end process next_state_logic; igital esign Chapter 4 Sequential Basics 5 Multiplier Control in Moore FSM output_logic : process (current_state) is case current_state is when step => a_sel <= ''; b_sel <= ''; pp_ce <= ''; pp2_ce <= ''; sub <= ''; p_r_ce <= ''; p_i_ce <= ''; when step2 => a_sel <= ''; b_sel <= ''; pp_ce <= ''; pp2_ce <= ''; sub <= ''; p_r_ce <= ''; p_i_ce <= ''; when step3 => a_sel <= ''; b_sel <= ''; pp_ce <= ''; pp2_ce <= ''; sub <= ''; p_r_ce <= ''; p_i_ce <= ''; when step4 => a_sel <= ''; b_sel <= ''; pp_ce <= ''; pp2_ce <= ''; sub <= ''; p_r_ce <= ''; p_i_ce <= ''; when step5 => a_sel <= ''; b_sel <= ''; pp_ce <= ''; pp2_ce <= ''; sub <= ''; p_r_ce <= ''; p_i_ce <= ''; end case; end process output_logic; igital esign Chapter 4 Sequential Basics 52 26

27 State Transition iagrams Bubbles to represent states Arcs to represent transitions Example,, S = {s, s2, s3} Inputs (a, a2): Σ = {(,), (,), (,), (,)} δ defined by diagram, s,, s2, s3,, igital esign Chapter 4 Sequential Basics 53 State Transition iagrams Annotate diagram to define output function Annotate states for Moore-style outputs Annotate arcs for Mealy-style outputs Example x, x 2 : Moore-style y, y 2, y 3 : Mealy-style, /,,, /,, s, /,, s2,,, /,, /,,, /,, s3, /,,,, /,,, /,, igital esign Chapter 4 Sequential Basics 54 27

28 Multiplier Control iagram Input: input_rdy Outputs a_sel, b_sel, pp_ce, pp2_ce, sub, p_r_ce, p_i_ce step,,,,,, step2,,,,,, step5,,,,,, step4,,,,,, step3,,,,,, igital esign Chapter 4 Sequential Basics 55 Bubble iagrams or? Many CA tools provide editors for bubble diagrams Automatically generate for simulation and synthesis iagrams are visually appealing but can become unwieldy for complex FSMs Your choice... or your manager's! igital esign Chapter 4 Sequential Basics 56 28

29 Register Transfer Level RTL a level of abstraction data stored in registers transferred via circuits that operate on data inputs outputs control section igital esign Chapter 4 Sequential Basics 57 Clocked Synchronous Timing Registers driven by a common clock Combinational circuits operate during clock cycles (between rising clock edges) t c t co t pd 2 t su t co t pd t slack t su t co + t pd + t su < t c 2 igital esign Chapter 4 Sequential Basics 58 29

30 Control Path Timing t co t su t co + t pd-s + t pd-o + t pd-c + t su < t c t pd-s t pd-c t co + t pd-s + t pd-ns + t su < t c t pd-o t pd-ns t su Ignore t pd-s for a Moore FSM igital esign Chapter 4 Sequential Basics 59 Timing Constraints Inequalities must hold for all paths If t co and t su the same for all paths Combinational delays make the difference Critical path The combinational path between registers with the longest delay etermines minimum clock period for the entire system Focus on it to improve performance Reducing delay may make another path critical igital esign Chapter 4 Sequential Basics 6 3

31 Interpretation of Constraints. Clock period depends on delays System can operate at any frequency up to a maximum OK for systems where high performance is not the main requirement 2. elays must fit within a target clock period Optimize critical paths to reduce delays if necessary May require revising RTL organization igital esign Chapter 4 Sequential Basics 6 Clock Skew 2 2 t h 2 Need to ensure clock edges arrive at all registers at the same time Use CA tools to insert clock buffers and route clock signal paths igital esign Chapter 4 Sequential Basics 62 3

32 Off-Chip Connections elays going off-chip and inter-chip Input and output pad delays, wire delays Same timing rules apply Use input and output registers to avoid adding external delay to critical path 2 igital esign Chapter 4 Sequential Basics 63 Asynchronous Inputs External inputs can change at any time Might violate setup/hold time constraints Can induce metastable state in a flipflop Unbounded time to recover May violate setup/hold time of subsequent flipflop MTBF e = k f k 2 >> igital esign Chapter 4 Sequential Basics 64 k t 2 f f 2 32

33 Synchronizers asynch_in synch_in If input changes outside setup/hold window Change is simply delayed by one cycle If input changes during setup/hold window First flipflop has a whole cycle to resolve metastability See data sheets for metastability parameters igital esign Chapter 4 Sequential Basics 65 Switch Inputs and ebouncing Switches and push-buttons suffer from contact bounce Takes up to ms to settle Need to debounce to avoid false triggering +V R Requires two inputs and two resistors S Must use a breakbefore-make doublethrow switch igital esign Chapter 4 Sequential Basics 66 33

34 Switch Inputs and ebouncing Alternative Use a single-throw switch Sample input at intervals longer than bounce time Look for two successive samples with the same value +V Assumption Extra circuitry inside the chip is cheaper than extra components and connections outside igital esign Chapter 4 Sequential Basics 67 ebouncing in library ieee; use ieee.std_logic_64.all; entity debouncer is port (, reset : in std_logic; -- frequency = 5MHz pb : in std_logic; pb_debounced : out std_logic ); end entity debouncer; architecture rtl of debouncer is signal count5 : integer range to ; signal _Hz : std_logic; signal pb_sampled : std_logic; igital esign Chapter 4 Sequential Basics 68 34

35 ebouncing in div_hz : process (, reset) is if reset = '' then _Hz <= ''; count5 <= ; elsif rising_edge() then if count5 = then count5 <= ; _Hz <= ''; else count5 <= count5 + ; _Hz <= ''; end process div_hz; debounce_pb : process () is if rising_edge() then if _Hz = '' then if pb = pb_sampled then pb_debounced <= pb; pb_sampled <= pb; end process debounce_pb; end architecture rtl; igital esign Chapter 4 Sequential Basics 69 Verifying Sequential Circuits Verification Testbench Apply Test Cases esign Under Verification (UV) Checker UV may take multiple and varying number of cycles to produce output Checker needs to synchronize with test generator ensure UV outputs occur when expected ensure UV outputs are correct ensure no spurious outputs occur igital esign Chapter 4 Sequential Basics 7 35

36 Example: Multiplier Testbench entity multiplier_testbench is end entity multiplier_testbench; library ieee; use ieee.std_logic_64.all, ieee.fixed_pkg.all, ieee.math_complex.all; architecture verify of multiplier_testbench is constant t_c : time := 5 ns; signal, reset : std_logic; signal input_rdy : std_logic; signal a_r, a_i, b_r, b_i : sfixed(3 downto -2); signal p_r, p_i : sfixed(7 downto -24); signal a, b : complex; duv : entity work.multiplier(rtl) port map (, reset, input_rdy, a_r, a_i, b_r, b_i, p_r, p_i ); _gen : process is wait for t_c / 2; <= ''; wait for t_c / 2; <= '; end process _gen; reset <= '', '' after 2 * t_c ns; igital esign Chapter 4 Sequential Basics 7 Example: Multiplier Testbench apply_test_cases : process is wait until falling_edge() and reset = ''; a <= cmplx(.,.); b <= cmplx(., 2.); input_rdy <= ''; wait until falling_edge(); input_rdy <= ''; for i in to 5 loop wait until falling_edge(); end loop; a <= cmplx(.,.); b <= cmplx(.,.); input_rdy <= ''; wait until falling_edge(); input_rdy <= ''; for i in to 6 loop wait until falling_edge(); end loop; -- further test cases... wait; end process apply_test_cases; a_r <= to_sfixed(a.re, a_r'left, a_r'right); a_i <= to_sfixed(a.im, a_i'left, a_i'right); b_r <= to_sfixed(b.re, b_r'left, b_r'right); b_i <= to_sfixed(b.im, b_i'left, b_i'right); igital esign Chapter 4 Sequential Basics 72 36

37 Example: Multiplier Testbench check_outputs : process is variable p : complex; wait until rising_edge() and input_rdy = ''; p := a * b; for i in to 5 loop wait until falling_edge(); end loop; assert abs (to_real(p_r) - p.re) < 2.**(-2) and abs (to_real(p_i) - p.im) < 2.**(-2); end process check_outputs; end architecture verify; igital esign Chapter 4 Sequential Basics 73 Asynchronous Timing Clocked synchronous timing requires global clock distribution with minimal skew path delay between registers < clock period Hard to achieve in complex multi-ghz systems Globally asynch, local synch (GALS) systems ivide the systems into local clock domains Inter-domain signals treated as asynch inputs Simplifies clock managements and constraints elays inter-domain communication elay-insensitive asynchronous systems no clock signals igital esign Chapter 4 Sequential Basics 74 37

38 Other Clock-Related Issues Inter-chip clocking istributing high-speed clocks on PCBs is hard Often use slower off-chip clock, with on-chip clock a multiple of off-chip clock Synchronize on-chip with phase-locked loop (PLL) In multi-pcb systems treat off-pcb signals as asynch inputs Low power design Continuous clocking wastes power Clock gating: turn off clock to idle subsystems igital esign Chapter 4 Sequential Basics 75 Summary Registers for storing data synchronous and asynchronous control clock enable, reset, preset Latches: level-sensitive usually unintentional in Counters free-running dividers, terminal count, reset, load, up/down igital esign Chapter 4 Sequential Basics 76 38

39 Summary RTL organization of digital systems datapath and control section Finite-State Machine (FSM) states, inputs, transition/output functions Moore and Mealy FSMs bubble diagrams Clocked synch timing and constraints critical path and optimization Asynch inputs, switch debouncing Verification of sequential systems igital esign Chapter 4 Sequential Basics 77 39