Project Part A: Single Cycle Processor

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Byron Sherman
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1 Curtis Mayberry Andrew Kies Mark Monat Iowa State University CprE 381 Professor Joseph Zambreno Project Part A: Single Cycle Processor Introduction The second part in the three part MIPS Processor design lab, this project assembles a single cycle MIPS processor. Each part of the processor, the control logic, data path, instruction fetch logic and ALU design is brought together to form our first fully operational microprocessor. The processor handles forty five unique instructions. Although the final part of the project improves upon our single cycle design to create a pipelined processor, the single cycle processor is still able to perform the same computations, just not as efficiently. Pre-lab R-Type Instructions (Opcode ) Instruction Function add rd, rs, rt addu rd, rs, rt and rd, rs, rt jalr rd, rs jr rs mul rd nor rd, rs, rt or rd, rs, rt sll rd, rt, sa sllv rd, rt, rs slt rd, rs, rt sltu rd, rs, rt slt rd, rs, rt sltu rd, rs, rt sra rd, rt, rs srav rd, rt, rs srl rd, rt, sa srlv rd, rt, rs

2 sub rd, rs, rt subu rd, rs, rt xor rd, rs, rt I-Type Instructions (All opcodes except , 00001x, and 0100xx) Instruction Opcode Notes addi rt, rs, immediate addiu rt, rs, immediate andi rt, rs, immediate beq rs, rt, label bgez rs, label rt = bgtz rs, label rt = blez rs, label rt = bltz rs, label rt = bne rs, rt, label lb rt, immediate(rs) lbu rt, immediate(rs) lh rt, immediate(rs) lhu rt, immediate(rs) lui rt, immediate lw rt, immediate(rs) ori rt, rs, immediate sb rt, immediate(rs) slti rt, rs, immediate sltiu rt, rs, immediate sh rt, immediate(rs) sw rt, immediate(rs) xori rt, rs, immediate J-Type Instructions (Opcode 00001x) Instruction Opcode Target j label coded address of label jal label coded address of label

3 Part 1: Control Logic Unit The entire single cycle processor needs a brain that controls all of the functions of the processor based on the instruction that has been decoded. Part 1a A spreadsheet detailing a list of each supported instruction s control signals was created. See the attached file Control Instructions.xlsx for our list of instruction control signals. Part 1b The MIPS processor control logic unit was described using dataflow VHDL and incorporates a 25 bit control bud. See attached file Processor_Ctl_logic.vhd for our implementation. The control logic unit was tested using the test bench tb_processor_ctl_logic.vhd. Part 2: Instruction Fetch Logic Our instruction fetch logic was built on top of the provided generic memory module. The instruction fetch not only provides the instruction specified by the program counter, but also handles the incrementing of the PC and the branching and jumping logic that affects the program counter. Part 2a The instruction logic control signals control the functioning of the jumping and branching logic. These jump control signals include i_c_jr, which enables the jump register function and i_c_jump that handles all other jump instructions, including jump and jump and link instructions. The branch control logic includes i_c_branch, which enables branches. Part 2b The instruction fetch schematic is outlined using a dotted line in the main processor schematic in part 3. Part 2c The generic memory that was used for the mips instruction memory, gen_mem is the same as the memory used for the data memory and is tested in the test bench tb_gen_mem_wcontrol.vhd, which also includes extra control logic to facilitate the data memory. It is also tested within the instruction fetch test bench tb_instruction_fetch.vhd. Part 2d The instruction fetch logic is implemented using structural VHDL in file Instruction_Fetch.vhd. The test bench was implemented using assert statements that automatically check each test case of the instruction fetch logic. The assert statement compares the simulated value with the expected value. A green arrow on the test bench waveform corresponds to a passed test, whereas a red arrow corresponds to a failed test. All instructions matched there expected outputs and the test was successful.

4 Part 3 The MIPS processor design shown in figure 1 was created and then implemented in structural VHDL. Figure 1: MIPS single cycle processor design The processor implements a reset instruction and uses the gen_mem memory module for both instruction and data memory. The major challenges included mistakes that needed to be worked out in our test bench. We had a number of tests where the test bench s expected value was incorrect. We also had to rework our jump register and load/store logic. Also, the ALU had to be redesigned to incorporate new features needed for the functioning of the processor.

5 Part 4 Testing was an extensive part of our processor design flow. The testing and debugging of the processor took significantly longer than the design of the processor. There were three tests that had to be run, including a test bench of every instruction, a BubbleSort algorithm and a MergeSort algorithm. A.do script was created in each instance to simplify the running of the test bench. Part 4a We had to create a program that tested each instruction individually. We ran 53 separate tests for the 45 unique instructions. The test bench contained over six hundred lines of test code and included assert statements to check each test to see if the test s output matched the expected output. The testbench file is tb_mips_single_cycle_processor.vhd. Part 4b Next a BubbleSort algorithm coded in MIPS was ran in a separate test bench. Two memory initialization files, imem_bubblesortours.mif and dmem_bubblesort_2.mif were used for the instruction and data memory, respectively. The test bench was then ran from a script and the device under test was simulated. The contents of the memory were then viewed to see if they were properly sorted. Part 5 On November 16, 2010 we successfully demoed our test application making use of all 45 instructions and the BubbleSort algorithm we wrote. We were also able to successfully demonstrate the Taylor series sine approximation program that was provided. Conclusion The Single Cycle processor as the penultimate step to creating a final pipelined MIPS processor in VHDL has proven capable of all the functionality required in a MIPS processor. The design incorporates the data path, control logic, instruction fetch logic and memories needed to construct a fully functioning processor. The ALU had to be redesigned and both the instruction and data memory had to be altered. The processor had to be thoroughly tested using a number of programs. Each of these programs had to be written, have test benches designed and test scripts written. IN the end having a fully functioning MIPS processor has paid off and the group is excited to move forward to implementing the pipelined processor.

MIPS Reference Guide

MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming