# MIPS Instruction Reference

Save this PDF as:

Size: px
Start display at page:

## Transcription

6 Page 6 of 9 MULTU -- Multiply unsigned Multiplies \$s by \$t and stores the result in \$LO. Operation: \$LO = \$s * \$t; advance_pc (4); multu \$s, \$t ss ssst tttt NOOP -- no operation Performs no operation. Operation: advance_pc (4); noop Note: The encoding for a NOOP represents the instruction SLL \$0, \$0, 0 which has no side effects. In fact, nearly every instruction that has \$0 as its destination register will have no side effect and can thus be considered a NOOP instruction. OR -- Bitwise or Bitwise logical ors two registers and stores the result in a register Operation: \$d = \$s \$t; advance_pc (4); or \$d, \$s, \$t ss ssst tttt dddd d ORI -- Bitwise or immediate Bitwise ors a register and an immediate value and stores the result in a register Operation: \$t = \$s imm; advance_pc (4); SB -- Store byte ori \$t, \$s, imm SLL -- Shift left logical ss ssst tttt iiii iiii iiii iiii The least significant byte of \$t is stored at the specified address. Operation: MEM[\$s + offset] = (0xff & \$t); advance_pc (4); sb \$t, offset(\$s) ss ssst tttt iiii iiii iiii iiii

7 Page 7 of 9 Shifts a register value left by the shift amount listed in the instruction and places the result in a third register. Zeroes are shifted in. Operation: \$d = \$t << h; advance_pc (4); sll \$d, \$t, h ss ssst tttt dddd dhhh hh SLLV -- Shift left logical variable Shifts a register value left by the value in a second register and places the result in a third register. Zeroes are shifted in. Operation: \$d = \$t << \$s; advance_pc (4); sllv \$d, \$t, \$s ss ssst tttt dddd d SLT -- Set on less than (signed) If \$s is less than \$t, \$d is set to one. It gets zero otherwise. Operation: if \$s < \$t \$d = 1; advance_pc (4); else \$d = 0; advance_pc (4); slt \$d, \$s, \$t ss ssst tttt dddd d SLTI -- Set on less than immediate (signed) If \$s is less than immediate, \$t is set to one. It gets zero otherwise. Operation: if \$s < imm \$t = 1; advance_pc (4); else \$t = 0; advance_pc (4); slti \$t, \$s, imm ss ssst tttt iiii iiii iiii iiii SLTIU -- Set on less than immediate unsigned If \$s is less than the unsigned immediate, \$t is set to one. It gets zero otherwise. Operation: if \$s < imm \$t = 1; advance_pc (4); else \$t = 0; advance_pc (4); sltiu \$t, \$s, imm ss ssst tttt iiii iiii iiii iiii SLTU -- Set on less than unsigned If \$s is less than \$t, \$d is set to one. It gets zero otherwise. Operation: if \$s < \$t \$d = 1; advance_pc (4); else \$d = 0; advance_pc (4); sltu \$d, \$s, \$t

8 Page 8 of ss ssst tttt dddd d SRA -- Shift right arithmetic Shifts a register value right by the shift amount (shamt) and places the value in the destination register. The sign bit is shifted in. Operation: \$d = \$t >> h; advance_pc (4); sra \$d, \$t, h t tttt dddd dhhh hh SRL -- Shift right logical Shifts a register value right by the shift amount (shamt) and places the value in the destination register. Zeroes are shifted in. Operation: \$d = \$t >> h; advance_pc (4); srl \$d, \$t, h t tttt dddd dhhh hh SRLV -- Shift right logical variable Shifts a register value right by the amount specified in \$s and places the value in the destination register. Zeroes are shifted in. Operation: \$d = \$t >> \$s; advance_pc (4); srlv \$d, \$t, \$s ss ssst tttt dddd d SUB -- Subtract Subtracts two registers and stores the result in a register Operation: \$d = \$s - \$t; advance_pc (4); sub \$d, \$s, \$t ss ssst tttt dddd d SUBU -- Subtract unsigned Subtracts two registers and stores the result in a register Operation: \$d = \$s - \$t; advance_pc (4); subu \$d, \$s, \$t ss ssst tttt dddd d SW -- Store word

9 Page 9 of 9 The contents of \$t is stored at the specified address. Operation: MEM[\$s + offset] = \$t; advance_pc (4); sw \$t, offset(\$s) ss ssst tttt iiii iiii iiii iiii SYSCALL -- System call Generates a software interrupt. Operation: advance_pc (4); syscall The syscall instruction is described in more detail on the System Calls page. XOR -- Bitwise exclusive or Exclusive ors two registers and stores the result in a register Operation: \$d = \$s ^ \$t; advance_pc (4); xor \$d, \$s, \$t ss ssst tttt dddd d XORI -- Bitwise exclusive or immediate Bitwise exclusive ors a register and an immediate value and stores the result in a register Operation: \$t = \$s ^ imm; advance_pc (4); xori \$t, \$s, imm ss ssst tttt iiii iiii iiii iiii Updated on September 10, 1998

### MIPS Reference Guide

MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming

### MIPS Instruction Format

MIPS Instruction Format MIPS uses a 32-bit fixed-length instruction format. only three different instruction word formats: There are Register format Op-code Rs Rt Rd Function code 000000 sssss ttttt ddddd

### ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### Week 10: Assembly Programming

Week 10: Assembly Programming Arithmetic instructions Instruction Opcode/Function Syntax Operation add 100000 \$d, \$s, \$t \$d = \$s + \$t addu 100001 \$d, \$s, \$t \$d = \$s + \$t addi 001000 \$t, \$s, i \$t = \$s +

### SPIM Instruction Set

SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large

### Assembly Programming

Designing Computer Systems Assembly Programming 08:34:48 PM 23 August 2016 AP-1 Scott & Linda Wills Designing Computer Systems Assembly Programming In the early days of computers, assembly programming

### ECE232: Hardware Organization and Design. Computer Organization - Previously covered

ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization

### Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats

Today s Lecture Homework #2 Midterm I Feb 22 (in class closed book) MIPS Assembly Language Computer Science 14 Lecture 6 Outline Assembly Programming Reading Chapter 2, Appendix B 2 Review: A Program Review:

### Mips Code Examples Peter Rounce

Mips Code Examples Peter Rounce P.Rounce@cs.ucl.ac.uk Some C Examples Assignment : int j = 10 ; // space must be allocated to variable j Possibility 1: j is stored in a register, i.e. register \$2 then

### ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### ECE Exam I February 19 th, :00 pm 4:25pm

ECE 3056 Exam I February 19 th, 2015 3:00 pm 4:25pm 1. The exam is closed, notes, closed text, and no calculators. 2. The Georgia Tech Honor Code governs this examination. 3. There are 4 questions and

### Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers

CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers \$0 \$31 Multiply divide Coprocessor 1 (FPU) Registers

### CS 4200/5200 Computer Architecture I

CS 4200/5200 Computer Architecture I MIPS Instruction Set Architecture Dr. Xiaobo Zhou Department of Computer Science CS420/520 Lec3.1 UC. Colorado Springs Adapted from UCB97 & UCB03 Review: Organizational

### The MIPS R2000 Instruction Set

The MIPS R2000 Instruction Set Arithmetic and Logical Instructions In all instructions below, Src2 can either be a register or an immediate value (a 16 bit integer). The immediate forms of the instructions

### CPS311 - COMPUTER ORGANIZATION. A bit of history

CPS311 - COMPUTER ORGANIZATION A Brief Introduction to the MIPS Architecture A bit of history The MIPS architecture grows out of an early 1980's research project at Stanford University. In 1984, MIPS computer

### CSc 256 Final Spring 2011

CSc 256 Final Spring 2011 NAME: Problem1: Convertthedecimalfloatingpointnumber 4.3toa32 bitfloat(inbinary)inieee 754standardrepresentation.Showworkforpartialcredit.10points Hint:IEEE754formatfor32 bitfloatsconsistsofs

### Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions

Outline EEL-4713 Computer Architecture Multipliers and shifters Multiplication and shift registers Chapter 3, section 3.4 Next lecture Division, floating-point 3.5 3.6 EEL-4713 Ann Gordon-Ross.1 EEL-4713

### EE 109 Unit 8 MIPS Instruction Set

1 EE 109 Unit 8 MIPS Instruction Set 2 Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system

### Concocting an Instruction Set

Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter 2.1-2.7 L03 Instruction Set 1 A General-Purpose Computer The von

### ICS 233 COMPUTER ARCHITECTURE. MIPS Processor Design Multicycle Implementation

ICS 233 COMPUTER ARCHITECTURE MIPS Processor Design Multicycle Implementation Lecture 23 1 Add immediate unsigned Subtract unsigned And And immediate Or Or immediate Nor Shift left logical Shift right

### A Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3

A Processor Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Let s build a MIPS CPU but using Harvard architecture Basic Computer System Registers ALU

EE 352 Unit 3 MIPS ISA Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system Instruction set is the vocabulary the HW can understand and the SW is composed

### Computer Architecture Experiment

Computer Architecture Experiment Jiang Xiaohong College of Computer Science & Engineering Zhejiang University Architecture Lab_jxh 1 Topics 0 Basic Knowledge 1 Warm up 2 simple 5-stage of pipeline CPU

### MIPS%Assembly% E155%

MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage \$0 0 the constant value 0 \$at 1 assembler temporary

### ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 \$zero all bits are zero 16 \$s0 local variable 1 \$at assembler temporary 17 \$s1 local

### ECE 2035 A Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 14 December 2016

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### EE108B Lecture 3. MIPS Assembly Language II

EE108B Lecture 3 MIPS Assembly Language II Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements Urgent: sign up at EEclass and say if you are taking 3 or 4 units Homework

### A General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction

page 1 Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... A General-Purpose Computer The von Neumann Model Many architectural approaches

### Digital System Design II

Digital System Design II 数字系统设计 II Peng Liu ( 刘鹏 ) Dept. of Info. Sci. & Elec. Engg. Zhejiang University liupeng@zju.edu.cn Lecture 2 MIPS Instruction Set Architecture 2 Textbook reading MIPS ISA 2.1-2.4

### CS 61c: Great Ideas in Computer Architecture

MIPS Functions July 1, 2014 Review I RISC Design Principles Smaller is faster: 32 registers, fewer instructions Keep it simple: rigid syntax, fixed instruction length MIPS Registers: \$s0-\$s7,\$t0-\$t9, \$0

### HW2 solutions You did this for Lab sbn temp, temp,.+1 # temp = 0; sbn temp, b,.+1 # temp = -b; sbn a, temp,.+1 # a = a (-b) = a + b;

HW2 solutions 3.10 Pseuodinstructions What is accomplished Minimum sequence of Mips Move \$t5, \$t3 \$t5=\$t3 Add \$t5, \$t3, \$0 Clear \$t5 \$t5=0 Xor \$t5, \$t5, \$t5 Li \$t5, small \$t5=small Addi \$t5, \$0, small

### We will study the MIPS assembly language as an exemplar of the concept.

MIPS Assembly Language 1 We will study the MIPS assembly language as an exemplar of the concept. MIPS assembly instructions each consist of a single token specifying the command to be carried out, and

### MIPS PROJECT INSTRUCTION SET and FORMAT

ECE 312: Semester Project MIPS PROJECT INSTRUCTION SET FORMAT This is a description of the required MIPS instruction set, their meanings, syntax, semantics, bit encodings. The syntax given for each instruction

### MIPS Instructions: 64-bit Core Subset

MIPS Instructions: 64-bit Core Subset Spring 2008 General notes: a. R s, R t, and R d specify 64-bit general purpose registers b. F s, F t, and F d specify 64-bit floating point registers c. C d specifies

### CS61C : Machine Structures

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures \$2M 3D camera Lecture 8 MIPS Instruction Representation I Instructor: Miki Lustig 2014-09-17 August 25: The final ISA showdown: Is ARM, x86, or

### Concocting an Instruction Set

Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Lab is posted. Do your prelab! Stay tuned for the first problem set. L04 Instruction

### Midterm. CS64 Spring Midterm Exam

Midterm LAST NAME FIRST NAME PERM Number Instructions Please turn off all pagers, cell phones and beepers. Remove all hats & headphones. Place your backpacks, laptops and jackets at the front. Sit in every

### CS 61c: Great Ideas in Computer Architecture

Introduction to Assembly Language June 30, 2014 Review C Memory Layout Local variables disappear because the stack changes Global variables don t disappear because they are in static data Dynamic memory

### A Processor! Hakim Weatherspoon CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3

A Processor! Hakim Weatherspoon CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Announcements! HW2 available later today HW2 due in one week and a half Work alone

### Lecture 6 Decision + Shift + I/O

Lecture 6 Decision + Shift + I/O Instructions so far MIPS C Program add, sub, addi, multi, div lw \$t0,12(\$s0) sw \$t0, 12(\$s0) beq \$s0, \$s1, L1 bne \$s0, \$s1, L1 j L1 (unconditional branch) slt reg1,reg2,reg3

### CS152 Computer Architecture and Engineering. Lecture 1 Introduction & MIPS Review Dave Patterson. www-inst.eecs.berkeley.

CS152 Computer Architecture and Engineering Lecture 1 Introduction & MIPS Review 2003-08-26 Dave Patterson (www.cs.berkeley.edu/~patterson) www-inst.eecs.berkeley.edu/~cs152/ CS 152 L01 Introduction &

### Anne Bracy CS 3410 Computer Science Cornell University. See P&H Chapter: , , Appendix B

Anne Bracy CS 3410 Computer Science Cornell University The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, and Sirer. See P&H Chapter: 2.16-2.20, 4.1-4.4,

### CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats

CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs61c/sp16 1 Machine Interpretation Levels of Representation/Interpretation

### CS61C Machine Structures. Lecture 10 - MIPS Branch Instructions II. 2/8/2006 John Wawrzynek. (www.cs.berkeley.edu/~johnw)

CS61C Machine Structures Lecture 10 - MIPS Branch Instructions II 2/8/2006 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS 61C L10 MIPS Branch II (1) Compiling C if into

### Computer Architecture. Chapter 3: Arithmetic for Computers

182.092 Computer Architecture Chapter 3: Arithmetic for Computers Adapted from Computer Organization and Design, 4 th Edition, Patterson & Hennessy, 2008, Morgan Kaufmann Publishers and Mary Jane Irwin

### Review of the Machine Cycle

MIPS Branch and Jump Instructions Cptr280 Dr Curtis Nelson Review of the Machine Cycle When a program is executing, its instructions are located in main memory. The address of an instruction is the address

### Chapter 6. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 6 <1>

Chapter 6 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 6 Chapter 6 :: Topics Introduction Assembly Language Machine Language Programming Addressing

### Lab 3: Pipelined MIPS Assigned: Wed., 2/13; Due: Fri., 3/1 (Midnight)

CMU 18-447 Introduction to Computer Architecture Spring 2013 1/7 Lab 3: Pipelined MIPS Assigned: Wed., 2/13; Due: Fri., 3/1 (Midnight) Instructor: Onur Mutlu TAs: Justin Meza, Yoongu Kim, Jason Lin It

### Compiling Techniques

Lecture 10: An Introduction to MIPS assembly 18 October 2016 Table of contents 1 Overview 2 3 Assembly program template.data Data segment: constant and variable definitions go here (including statically

### CHW 362 : Computer Architecture & Organization

CHW 362 : Computer Architecture & Organization Instructors: Dr Ahmed Shalaby Dr Mona Ali http://bu.edu.eg/staff/ahmedshalaby14# http://www.bu.edu.eg/staff/mona.abdelbaset Assignment What is the size of

### REGISTERS INSTRUCTION SET DIRECTIVES SYSCALLS

MARS REGISTERS INSTRUCTION SET DIRECTIVES SYSCALLS ΗΥ 134: ΕΙΣΑΓΩΓΗ ΣΤΗΝ ΟΡΓΑΝΩΣΗ ΚΑΙ ΣΧΕΔΙΑΣΗ Η/Υ Ι Registers MIPS has 32 integer registers. The hardware architecture specifies that: General purpose register

### MIPS Assembly Programming

COMP 212 Computer Organization & Architecture COMP 212 Fall 2008 Lecture 8 Cache & Disk System Review MIPS Assembly Programming Comp 212 Computer Org & Arch 1 Z. Li, 2008 Comp 212 Computer Org & Arch 2

### Tailoring the 32-Bit ALU to MIPS

Tailoring the 32-Bit ALU to MIPS MIPS ALU extensions Overflow detection: Carry into MSB XOR Carry out of MSB Branch instructions Shift instructions Slt instruction Immediate instructions ALU performance

### Fundamentals of Computer Systems

Fundamentals of Computer Systems The MIPS Instruction Set Martha A. Kim Columbia University Fall 2015 1 / 67 Instruction Set Architectures MIPS The GCD Algorithm MIPS Registers Types of Instructions Computational

### CO Computer Architecture and Programming Languages CAPL. Lecture 13 & 14

CO20-320241 Computer Architecture and Programming Languages CAPL Lecture 13 & 14 Dr. Kinga Lipskoch Fall 2017 Frame Pointer (1) The stack is also used to store variables that are local to function, but

### Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21

2.9 Communication with People: Byte Data & Constants Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21 32: space 33:! 34: 35: #...

### Chapter 6 :: Topics. Chapter 6 :: Architecture

Chapter 6 :: Architecture Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Chapter 6 :: Topics Introduction Assembly Language Machine Language Programming Addressing Modes

### CPU Design for Computer Integrated Experiment

CPU Design for Computer Integrated Experiment Shan Lu, Guangyao Li, Yijianan Wang CEIE, Tongji University, Shanghai, China Abstract - Considering the necessity and difficulty of designing a CPU for students,

### SMIPS Processor Specification

SMIPS Processor Specification CS250 VLSI Systems Design September 25, 2009 SMIPS is the version of the MIPS instruction set architecture (ISA) we ll be using for the processors we implement in 6.884. SMIPS

### COMP MIPS instructions 2 Feb. 8, f = g + h i;

Register names (save, temporary, zero) From what I have said up to now, you will have the impression that you are free to use any of the 32 registers (\$0,..., \$31) in any instruction. This is not so, however.

### Harnessing FPGAs for Computer Architecture Education

Harnessing FPGAs for Computer Architecture Education Mark Holland, James Harris, Scott Hauck Department of Electrical Engineering University of Washington, Seattle, WA 98195, USA mholland@ee.washington.edu,

### Lab 2: Single-Cycle MIPS Assigned: Fri., 2/1; Due: Fri., 2/15 (Midnight)

CMU 18-447 Introduction to Computer Architecture Spring 2013 1/6 1. Introduction Lab 2: Single-Cycle MIPS Assigned: Fri., 2/1; Due: Fri., 2/15 (Midnight) Instructor: Onur Mutlu TAs: Justin Meza, Yoongu

### MIPS ISA and MIPS Assembly. CS301 Prof. Szajda

MIPS ISA and MIPS Assembly CS301 Prof. Szajda Administrative HW #2 due Wednesday (9/11) at 5pm Lab #2 due Friday (9/13) 1:30pm Read Appendix B5, B6, B.9 and Chapter 2.5-2.9 (if you have not already done

### Chapter loop: lw \$v1, 0(\$a0) addi \$v0, \$v0, 1 sw \$v1, 0(\$a1) addi \$a0, \$a0, 1 addi \$a1, \$a1, 1 bne \$v1, \$zero, loop

Chapter 3 3.7 loop: lw \$v1, 0(\$a0) addi \$v0, \$v0, 1 sw \$v1, 0(\$a1) addi \$a0, \$a0, 1 addi \$a1, \$a1, 1 bne \$v1, \$zero, loop Instructions Format OP rs rt Imm lw \$v1, 0(\$a0) I 35 4 3 0 addi \$v0, \$v0, 1 I 8

### Overview of Today s Lecture

Overview of Today s Lecture CS152 Computer Architecture and Engineering Lecture 2 Review of MIPS ISA and Performance January 18, 2001 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) Review from Last

### Inequalities in MIPS (2/4) Inequalities in MIPS (1/4) Inequalities in MIPS (4/4) Inequalities in MIPS (3/4) UCB CS61C : Machine Structures

CS61C L8 Introduction to MIPS : Decisions II & Procedures I (1) Instructor Paul Pearce inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures http://www.xkcd.org/627/ Lecture 8 Decisions & and Introduction

### CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014

B CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014 DUE : March 3, 2014 READ : - Related sections of Chapter 2 - Related sections of Chapter 3 - Related sections of Appendix A - Related sections

### Today s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA.

Today s topics CS/COE1541: Introduction to Computer Architecture MIPS operations and operands MIPS registers Memory view Instruction encoding A Review of MIPS ISA Sangyeun Cho Arithmetic operations Logic

### RISC, CISC, and Assemblers

RISC, CISC, and Assemblers Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See P&H Appendix B.1 2, and Chapters 2.8 and 2.12; als 2.16 and 2.17 Big Picture: Understanding Tradeoffs

### A MIPS R10000-LIKE OUT-OF-ORDER MICROPROCESSOR IMPLEMENTATION IN VERILOG HDL

A MIPS R10000-LIKE OUT-OF-ORDER MICROPROCESSOR IMPLEMENTATION IN VERILOG HDL A Design Project Report Presented to the Engineering Division of the Graduate School Of Cornell University In Partial Fulfillment

### Announcements. EE108B Lecture MIPS Assembly Language III. MIPS Machine Instruction Review: Instruction Format Summary

Announcements EE108B Lecture MIPS Assembly Language III Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b PA1 available, due on Thursday 2/8 Work on you own (no groups) Homework

### CS61C : Machine Structures

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 13 Introduction to MIPS Instruction Representation I Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia Anyone seen Terminator? Military

### ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design

ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2014 Sources: Computer

### MIPS (SPIM) Assembler Syntax

MIPS (SPIM) Assembler Syntax Comments begin with # Everything from # to the end of the line is ignored Identifiers are a sequence of alphanumeric characters, underbars (_), and dots () that do not begin

### Problem maximum score 1 35pts 2 22pts 3 23pts 4 15pts Total 95pts

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences CS61c Summer 2001 Woojin Yu Midterm Exam This is a closed-book exam. No calculators

### COMP 303 MIPS Processor Design Project 3: Simple Execution Loop

COMP 303 MIPS Processor Design Project 3: Simple Execution Loop Due date: November 20, 23:59 Overview: In the first three projects for COMP 303, you will design and implement a subset of the MIPS32 architecture

### Computer Systems Architecture

Computer Systems Architecture http://cs.nott.ac.uk/ txa/g51csa/ Thorsten Altenkirch and Liyang Hu School of Computer Science and IT University of Nottingham Lecture 05: Comparisons, Loops and Bitwise Operations

### Computer Organization MIPS Architecture. Department of Computer Science Missouri University of Science & Technology

Computer Organization MIPS Architecture Department of Computer Science Missouri University of Science & Technology hurson@mst.edu Computer Organization Note, this unit will be covered in three lectures.

### Computer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#:

Computer Science and Engineering 331 Midterm Examination #1 Fall 2000 Name: Solutions S.S.#: 1 41 2 13 3 18 4 28 Total 100 Instructions: This exam contains 4 questions. It is closed book and notes. Calculators

### Welcome to CS250 VLSI Systems Design

Image Courtesy: Intel Welcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee YUNSUP LEE Email: yunsup@cs.berkeley.edu Please add [CS250] in the subject Will try to get back in a day CS250 Newsgroup Post

### Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture

Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:

### CS3350B Computer Architecture

CS3350B Computer Architecture Winter 2015 Lecture 4.1: MIPS ISA: Introduction Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted d from lectures on Computer Organization and Design, Patterson & Hennessy,

### Assembly Language Programming. CPSC 252 Computer Organization Ellen Walker, Hiram College

Assembly Language Programming CPSC 252 Computer Organization Ellen Walker, Hiram College Instruction Set Design Complex and powerful enough to enable any computation Simplicity of equipment MIPS Microprocessor

### B649 Graduate Computer Architecture. Lec 1 - Introduction

B649 Graduate Computer Architecture Lec 1 - Introduction http://www.cs.indiana.edu/~achauhan/teaching/ B649/2009-Spring/ 1/12/09 b649, Lec 01-intro 2 Outline Computer Science at a Crossroads Computer Architecture

### CS 61C: Great Ideas in Computer Architecture Introduction to Assembly Language and MIPS Instruction Set Architecture

CS 61C: Great Ideas in Computer Architecture Introduction to Assembly Language and MIPS Instruction Set Architecture Instructors: Bernhard Boser & Randy H. Katz http://inst.eecs.berkeley.edu/~cs61c/fa16

### Lab 4 Report. Single Cycle Design BAOTUNG C. TRAN EEL4713C

Lab 4 Report Single Cycle Design BAOTUNG C. TRAN EEL4713C Added Hardware : Andi and Ori : For this instruction, I had to add a zero extender into my design. Which therefore required me to add a mux that

### Chapter 3 Arithmetic for Computers

Chapter 3 Arithmetic for Computers 1 Arithmetic Where we've been: Abstractions: Instruction Set Architecture Assembly Language and Machine Language What's up ahead: Implementing the Architecture operation

### All instructions have 3 operands Operand order is fixed (destination first)

Instruction Set Architecture for MIPS Processors Overview Dr. Arjan Durresi Louisiana State University Baton Rouge, LA 70803 durresi@csc.lsu.edu These slides are available at: http://www.csc.lsu.edu/~durresi/_07/

### EN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design

EN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown

### Fast Arithmetic. Philipp Koehn. 19 October 2016

Fast Arithmetic Philipp Koehn 19 October 2016 1 arithmetic Addition (Immediate) 2 Load immediately one number (s0 = 2) li \$s0, 2 Add 4 (\$s1 = \$s0 + 4 = 6) addi \$s1, \$s0, 4 Subtract 3 (\$s2 = \$s1-3 = 3)

### MIPS Hello World. MIPS Assembly 1. # PROGRAM: Hello, World! # Data declaration section. out_string:.asciiz "\nhello, World!\n"

MIPS Hello World MIPS Assembly 1 # PROGRAM: Hello, World!.data # Data declaration section out_string:.asciiz "\nhello, World!\n".text # Assembly language instructions main: # Start of code section li \$v0,

### UCB CS61C : Machine Structures

inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 10 Introduction to MIPS Procedures I Sr Lecturer SOE Dan Garcia 2014-02-14 If cars broadcast their speeds to other vehicles (and the

### Machine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine

Machine Language Instructions Introduction Instructions Words of a language understood by machine Instruction set Vocabulary of the machine Current goal: to relate a high level language to instruction

### Numbers: positional notation. CS61C Machine Structures. Faux Midterm Review Jaein Jeong Cheng Tien Ee. www-inst.eecs.berkeley.

CS 61C Faux Midterm Review (1) CS61C Machine Structures Faux Midterm Review 2002-09-29 Jaein Jeong Cheng Tien Ee www-inst.eecs.berkeley.edu/~cs61c/ Numbers: positional notation Number Base B B symbols

### Architecture II. Computer Systems Laboratory Sungkyunkwan University

MIPS Instruction ti Set Architecture II Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Making Decisions (1) Conditional operations Branch to a

### Review (1/2) IEEE 754 Floating Point Standard: Kahan pack as much in as could get away with. CS61C - Machine Structures

Review (1/2) CS61C - Machine Structures Lecture 11 - Starting a Program October 4, 2000 David Patterson http://www-inst.eecs.berkeley.edu/~cs61c/ IEEE 754 Floating Point Standard: Kahan pack as much in

### Implementing Algorithms in MIPS Assembly

1 / 18 Implementing Algorithms in MIPS Assembly (Part 1) January 28 30, 2013 2 / 18 Outline Effective documentation Arithmetic and logical expressions Compositionality Sequentializing complex expressions

### ECE 154A Introduction to. Fall 2012

ECE 154A Introduction to Computer Architecture Fall 2012 Dmitri Strukov Lecture 4: Arithmetic and Data Transfer Instructions Agenda Review of last lecture Logic and shift instructions Load/store instructionsi