CSE 2021 Computer Organization. Hugh Chesser, CSEB 1012U W9-W

Transcription

1 CSE 22 Computer Organization Hugh Chesser, CSEB 2U

2 Agenda Topics:. Single Cycle Review (Sample Exam/Quiz Q) 2. ultiple cycle implementation Patterson: Section 4.5 Reminder: Quiz #2 Next Wednesday (November ) 2

3 ain Control (4) 4 Add [3 26] Control RegDst Branch em emtoreg Op em Src Reg Shift left 2 Add result PCSrc PC address memory [3 ] [25 2] [2 6] [5 ] [5 ] 2 Registers 2 6 Sign 32 extend control Zero result Address Data memory [5 ] 3

4 Activity (Sample Quiz, Exam Q) We wish to add jr(jump ) to the single cycle pathfrom the previous slide. Add the necessary connections to the single cycle pathblock diagram to implement the jrinstruction. Also, append the table below to add the necessary control signals needed for the jr instruction. RegDst Src emtoreg Reg em em Branch Op Op R-format lw sw beq 4

5 Answer (Part ): odify the path as shown 5

6 Answer (Part 2): append the table below to add the necessary control signals needed for the jr instruction. RegDst Src emtoreg Reg em em Branch JumpReg Op Op R-format lw sw beq jr 6

7 Why single-cycle implementation is not used? Assuming no delay at adder, sign extension unit, shift left unit, PC, control unit, and U: Load cycle requires 5 functional units: instruction fetch, access,, memory access, access Store cycle requires 4 functional units: instruction fetch, access,, memory access R-type instruction cycle requires 4 functional units: instruction fetch, access,, access Path for a branch instruction requires 3 functional units: instruction fetch, access, Path for a jump instruction requires functional unit: instruction fetch Using a clock cycle of equal duration for each instruction is a waste of resources. 7

8 Why ulticycle? Example: Assume that the operation times for major functional unit in a microprocessor are: emory unit ~ 2ns, and adders ~ 2ns, Register file ~ ns Compare the performance of the following instruction mix Loads: 24%; Stores: 2%; instructions: 44%; Branches: 8%; Jumps: 2% on the two implementations Implementation I: All instructions operate in clock cycle Implementation II: Each instruction is as long as it needs to be. Class Functional units used (Steps involved) type fetch Register Access Register Access 6ns Load word fetch Register Access emory Access Register Access 8ns Store word fetch Register Access emory Access 7ns Branch fetch Register Access 5ns Branch fetch 2ns Average time per instruction: Implementation : ~ 8ns Implementation 2: ~.24(8)+.2(7)+.44(6)+.8(5)+.2(2) = 6.34ns 8

9 ulticycle Implementation : Execution of each instruction is broken into different steps Each step requires clock cycle Each instruction takes multiple clock cycles Functional Unit: Can be used more than once in an instruction (but still only once in a clock cycle) Advantages: Functional units can be shared and adder is combined Single memory is used for instructions and 9

10 ulticycle Implementation: Abstract Diagram PC Address emory Data or emory Data Register # Registers Register # Register # A B Out One is used for incrementing PC and for arithmetic operations Data memory and memory are combined 5 additional s are added. An instruction (IR) to hold instructions before distributing to file or 2. A memory (DR) to hold before distributing to file or 3. Registers A and B that hold before the 4. Register out that hold computed by

11 ulticycle Implementation: ultiplexers added PC u x Address emory emdata [25 2] [2 6] [5 ] [5 ] emory [5 ] u x u x 6 2 Registers Sign extend 2 32 Shift left 2 A B 4 u x u 2 x 3 Zero result Out Because functional units are shared, multiplexers are added to select between different devices. U before memory selects either the PC output (fetch instruction) or output (storing ) 2. U before write selects write- number (instruction [5-] or instruction[2-6]) 3. U before write selects from Out (R-type instruction) or emdata (lw instruction) 4. Upper U before selects PC output (increment PC) or (R-type instruction) 5. Lower U before selects 2, or sign extended instruction[5-] or shift left sign extended instruction[5-], or 4

12 ulticycle Implementation: Controls added IorD em em IR RegDst Reg SrcA PC Address emory emdata [25 2] [2 6] [5 ] [5 ] [5 ] 2 Registers 2 A B Zero result Out emory 6 Sign extend 32 Shift left 2 control [5 ] emtoreg SrcB Op Because functional units are shared, multiplexers are added to select between different devices. U before memory selects either the PC output (fetch instruction) or output (storing ) 2. U before write selects write- number (instruction [5-] or instruction[2-6]) 2

13 ulticycle Implementation: Control Units added PC Address emory emdata [3-26] [25 2] [2 6] [5 ] [5 ] PCCond PC IorD em em emtoreg IR [25 ] [5 ] Outputs Control Op [5 ] PCSource Op SrcB SrcA Reg RegDst 2 Registers 2 A B Shift 28 left 2 PC [3-28] Zero result Jump address [3-] Out 2 emory 6 Sign extend 32 Shift left 2 control [5 ] 3

14 Action of -bit Control Signals Control Input IorD em em IR RegDst Reg SrcA emtoreg PC PCCond PC supplies address to memory (instruction fetch) None None None None Effect when Deasserted () Register specified by [2-6] (lw) PC is the first operand in (increment PC) Data of the file comes from Out Operation at PC depends on PCCond and zero output of Operation at PC depends on PC Effect when asserted () out supplies address to memory (lw/sw) emory content specified by address is placed on em o/p (lw/any instruction) I/p is stored at specified address (sw) emdata o/p is written on IR (instruction fetch) Register specified by [5-] (R-type) Data from Data i/p is written on the specified by Register number Register A is the first operand in Data of the file comes from DR PC is written; Source is determined by PCSource PC is written if zero o/p of = ; Source is determined by PCSource 4

15 Action of 2-bit Control Signals Control Input Op SrcB PCSource Value performs an add operation performs a subtract operation The second operand of = 4 The second operand of is sign extended [5-] The second operand of is sign extended, 2-bit left shifted [5- ] Output of (PC + 4) is sent to PC Effect The function field of defines the operation of The second operand of comes from Register B Contents of Out (branch target address = PC x offset) is sent to PC Contents of [25-], shift left by 2, and concatenated with the SB 4- bits of PC is sent to PC (jump instruction) 5