MIPS Architecture. Fibonacci (C) Fibonacci (Assembly) Another Example: MIPS. Example: subset of MIPS processor architecture

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Jade Brittany Freeman
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Another Eample: IPS From the Harris/Weste book Based on the IPS-like processor from the Hennessy/Patterson book IPS Architectre Eample: sbset of IPS processor

program conter Set Encoding -bit instrction encoding Reqires for cycles to fetch on -bit path format eample encoding 5 5 5 5 R add $rd, $ra, $rb ra rb rd fnct 5 5 I

1 Another Eample: IPS From the Harris/Weste book Based on the IPS-like processor from the Hennessy/Patterson book IPS Architectre Eample: sbset of IPS processor architectre Drawn from Patterson & Hennessy IPS is a -bit architectre with s Consider -bit sbset sing -bit path Only implement s ($ - $7) $ hardwired to -bit program conter Set Encoding -bit instrction encoding Reqires for cycles to fetch on -bit path format eample encoding R add $rd, $ra, $rb ra rb rd fnct 5 5 I beq $ra, $rb, imm ra rb imm J j dest dest Fibonacci (C) f = ; f - = - f n = f n- + f n- f =,,,, 5,,, Fibonacci (Assembly) st statement: n = How do we translate this to assembly?

icroarchitectre lticycle μarchitectre from Patterson & Hennessy PCEn Cond IorD em em emtoreg Otpts Control PCSorce ALUOp ALUSrcB ALUSrcA Reg IR[:] Op [5: ] RegDst PC Address emory emdata [:] [5 : ] [

2 Fibonacci (Assembly) Fibonacci (Binary) st statement: addi $, $, How do we translate this to machine langage? Hint: se instrction encodings below format eample encoding R add $rd, $ra, $rb ra rb rd fnct 5 5 I beq $ra, $rb, imm ra rb imm J j dest dest Fibonacci (Binary) achine langage program IPS icroarchitectre lticycle μarchitectre from Patterson & Hennessy PCEn Cond IorD em em emtoreg Otpts Control PCSorce ALUOp ALUSrcB ALUSrcA Reg IR[:] Op [5: ] RegDst PC Address emory emdata [:] [5 : ] [ : ] [5 : ] [7: ] [5:] Shift left [5: ] Registers A B Zero ALU ALU reslt Jmp address ALUOt emory ALU control ALUControl [5: ] lticycle Controller Logic Design em em ALUSrcA = ALUSrcA = IorD = IorD = IR IR ALUSrcB = ALUSrcB = ALUOp = ALUOp = PCSorce = PCSorce = Reset emory address comptation 5 ALUSrcA = ALUSrcB = ALUOp = (Op = 'L B') (Op = 'S B') fetch em em decode/ ALUSrcA = ALUSrcA = fetch IorD = IorD = 4 IR IR ALUSrcB = ALUSrcB = ALUSrcA = ALUOp = ALUOp = ALUSrcB = ALUOp = PCSorce = PCSorce = (Op = 'L B ') or (Op = 'S B ') emory emory access access R-type completion RegDst = em em Reg IorD = IorD = emtoreg = -back step 7 (Op = R-type) Branch Jmp Eection completion completion (Op = 'BEQ') 9 ALUSrcA = ALUSrcA = ALUSrcB = ALUSrcB = ALUOp = PCSorce = ALUOp= Cond PCSorce = (Op = 'J') Start at t level Hierarchically decompose IPS into nits T-level interface crystal oscillator Clk reset memread memwrite IPS processor adr write mem eternal memory RegDst= Reg emtoreg=

3 PCEn PC Address emory emdata emory Cond IorD em em emtoreg PCSorce ALUOp ALUS rcb ALUS rca Otpts Control RegWri te Op IR[:] RegDst [5: ] [5 : ] [: ] [5 : ] [ : ] [5 : ] [5: ] [7 : ] Registers Wr ite Wr ite [5 : ] Shift left A Zero ALU ALU reslt B ALU control ALUControl Jmp address ALUOt Verilog Code Block Diagram // t level design incldes both mips processor and memory modle mips_mem #(parameter WIDTH =, REGBITS = )(clk, reset); inpt clk, reset; wire memread, memwrite; wire [WIDTH-:] adr, write; wire [WIDTH-:] mem; // instantiate the mips processor mips #(WIDTH,REGBITS) mips(clk, reset, mem, memread, memwrite, adr, write); // instantiate memory for code and emem #(WIDTH) emem(clk, memwrite, adr, write, mem); memwrite memread ph ph reset adr[7:] write[7:] mem[7:] zero [5:] alsrca alsrcb[:] controller pcen pcsorce[:] memtoreg regdst iord regwrite irwrite[:] path al[:] alcontrol fnct[5:] alcontrol[:] // simplified IPS processor modle mips #(parameter WIDTH =, REGBITS = ) (inpt clk, reset, inpt [WIDTH-:] mem, otpt memread, memwrite, otpt [WIDTH-:] adr, write); wire [:] instr; wire zero, alsrca, memtoreg, iord, pcen, regwrite, regdst; wire [:] al,pcsorce,alsrcb; wire [:] irwrite; wire [:] alcont; controller cont(clk, reset, instr[:], zero, memread, memwrite, alsrca, memtoreg, iord, pcen, regwrite, regdst, pcsorce, alsrcb, al, irwrite); alcontrol ac(al, instr[5:], alcont); path #(WIDTH, REGBITS) dp(clk, reset, mem, alsrca, memtoreg, iord, pcen, regwrite, regdst, pcsorce, alsrcb, irwrite, alcont, zero, instr, adr, write); T-level code modle controller(inpt clk, reset, inpt [5:], inpt zero, otpt reg memread, memwrite, alsrca, memtoreg, iord, otpt pcen, otpt reg regwrite, regdst, otpt reg [:] pcsorce, alsrcb, al, otpt reg [:] irwrite); parameter FETCH = 4'b; parameter FETCH = 4'b; parameter FETCH = 4'b; parameter FETCH4 = 4'b; parameter DECODE = 4'b; parameter EADR = 4'b; parameter LBRD = 4'b; parameter LBWR = 4'b; parameter SBWR = 4'b; parameter RTYPEEX = 4'b; parameter RTYPEWR = 4'b; parameter BEQEX = 4'b; parameter JEX = 4'b; parameter ADDIWR = 4'b; // added for ADDI parameter LB = 'b; parameter SB = 'b; parameter RTYPE = 'b; parameter BEQ = 'b; parameter J = 'b; parameter ADDI = 'b; /// added for ADDI reg [:] state, netstate; reg pcwrite, pcwritecond; State Encodings... Opcodes... Local reg variables... Controller Parameters ain state machine NS logic Setting Control Signal Otpts // state if(reset) state <= FETCH; else state <= netstate; // net state logic (combinational) case(state) FETCH: netstate <= FETCH; FETCH: netstate <= FETCH; FETCH: netstate <= FETCH4; FETCH4: netstate <= DECODE; DECODE: case() LB: netstate <= EADR; SB: netstate <= EADR; ADDI: netstate <= EADR; RTYPE: netstate <= RTYPEEX; BEQ: netstate <= BEQEX; J: netstate <= JEX; // shold never happen defalt: netstate <= FETCH; EADR: case() LB: netstate <= LBRD; SB: netstate <= SBWR; ADDI: netstate <= ADDIWR; // shold never happen defalt: netstate <= FETCH; LBRD: netstate <= LBWR; LBWR: netstate <= FETCH; SBWR: netstate <= FETCH; RTYPEEX: netstate <= RTYPEWR; RTYPEWR: netstate <= FETCH; BEQEX: netstate <= FETCH; JEX: netstate <= FETCH; ADDIWR: netstate <= FETCH; // shold never happen defalt: netstate <= FETCH; // set all otpts to zero, then // conditionally assert jst the // apprriate ones irwrite <= 4'b; pcwrite <= ; pcwritecond <= ; regwrite <= ; regdst <= ; memread <= ; memwrite <= ; alsrca <= ; alsrcb <= 'b; al <= 'b; pcsorce <= 'b; iord <= ; memtoreg <= ; case(state) FETCH: memread <= ; irwrite <= 4'b; alsrcb <= 'b; pcwrite <= ; FETCH: memread <= ; irwrite <= 4'b; alsrcb <= 'b; pcwrite <= ; FETCH: memread <= ; irwrite <= 4'b; alsrcb <= 'b; pcwrite <= ; FETCH4: memread <= ; irwrite <= 4'b; alsrcb <= 'b; pcwrite <= ; DECODE: alsrcb <= 'b;...

4 modle alcontrol(inpt [:] al, inpt [5:] fnct, otpt reg [:] alcont); Verilog: alcontrol case(al) 'b: alcont <= 'b; // add for lb/sb/addi 'b: alcont <= 'b; // sb (for beq) defalt: case(fnct) // R-Type instrctions 'b: alcont <= 'b; // add (for add) 'b: alcont <= 'b; // sbtract (for sb) 'b: alcont <= 'b; // logical and (for and) 'b: alcont <= 'b; // logical or (for or) 'b: alcont <= 'b; // set on less (for slt) defalt: alcont <= 'b; // shold never happen modle al #(parameter WIDTH = ) (inpt [WIDTH-:] a, b, inpt [:] alcont, otpt reg [WIDTH-:] reslt); wire [WIDTH-:] b, sm, slt; Verilog: al assign b = alcont[]? ~b:b; assign sm = a + b + alcont[]; // slt shold be if most significant bit of sm is assign slt = sm[width-]; always@(*) case(alcont[:]) 'b: reslt <= a & b; 'b: reslt <= a b; 'b: reslt <= sm; 'b: reslt <= slt; Verilog: regfile modle regfile #(parameter WIDTH =, REGBITS = ) (inpt clk, inpt regwrite, inpt [REGBITS-:] ra, ra, wa, inpt [WIDTH-:] wd, otpt [WIDTH-:] rd, rd); reg [WIDTH-:] RA [(<<REGBITS)-:]; // three ported file // read two ports combinationally // write third port on rising edge of clock // hardwired to if (regwrite) RA[wa] <= wd; assign rd = ra? RA[ra] : ; assign rd = ra? RA[ra] : ; Verlog: Other stff modle zerodetect #(parameter WIDTH = ) (inpt [WIDTH-:] a, otpt y); assign y = (a==); modle fl #(parameter WIDTH = ) (inpt clk, inpt [WIDTH-:] d, otpt reg [WIDTH-:] q); q <= d; modle flen #(parameter WIDTH = ) (inpt clk, en, inpt [WIDTH-:] d, otpt reg [WIDTH-:] q); if (en) q <= d; modle flenr #(parameter WIDTH = ) (inpt clk, reset, en, inpt [WIDTH-:] d, otpt reg [WIDTH-:] q); if (reset) q <= ; else if (en) q <= d; modle m #(parameter WIDTH = ) (inpt [WIDTH-:] d, d, inpt s, otpt [WIDTH-:] y); assign y = s? d : d; modle m4 #(parameter WIDTH = ) (inpt [WIDTH-:] d, d, d, d, inpt [:] s, otpt reg [WIDTH-:] y); case(s) 'b: y <= d; 'b: y <= d; 'b: y <= d; 'b: y <= d; IPS icroarchitectre lticycle μarchitectre from Patterson & Hennessy PC PCEn Address emory emdata [:] [5 : ] [ : ] [5 : ] [7: ] emory Cond IorD em em emtoreg IR[:] [5: ] Otpts Control Op [5: ] PCSorce ALUOp ALUSrcB ALUSrcA Reg RegDst [5:] Shift left Registers A B ALU control Zero ALU ALU reslt ALUControl Jmp address ALUOt modle path #(parameter WIDTH =, REGBITS = ) (inpt clk, reset, inpt [WIDTH-:] mem, inpt alsrca, memtoreg, iord, pcen, regwrite, regdst, inpt [:] pcsorce, alsrcb, inpt [:] irwrite, inpt [:] alcont, otpt zero, otpt [:] instr, otpt [WIDTH-:] adr, write); // the size of the parameters mst be changed to match the WIDTH parameter localparam CONST_ZERO = 'b; localparam CONST_ONE = 'b; wire [REGBITS-:] ra, ra, wa; wire [WIDTH-:] pc, netpc, md, rd, rd, wd, a, src, src, alreslt, alot, const4; // shift left constant field by assign const4 = {instr[width-:],'b}; // file address fields assign ra = instr[regbits+:]; Verilog: Datapath assign ra = instr[regbits+5:]; m #(REGBITS) regm(instr[regbits+5:], instr[regbits+:], regdst, wa); [5: ] 4

5 // indepent of bit width, load instrction into for -bit s over for cycles flen #() ir(clk, irwrite[], mem[7:], instr[7:]); flen #() ir(clk, irwrite[], mem[7:], instr[5:]); flen #() ir(clk, irwrite[], mem[7:], instr[:]); flen #() ir(clk, irwrite[], mem[7:], instr[:4]); // path flenr #(WIDTH) pcreg(clk, reset, pcen, netpc, pc); fl #(WIDTH) areg(clk, rd, a); fl fl #(WIDTH) mdr(clk, mem, md); #(WIDTH) wrd(clk, rd, write); fl #(WIDTH) res(clk, alreslt, alot); Verilog: Datapath m #(WIDTH) adrm(pc, alot, iord, adr); m #(WIDTH) srcm(pc, a, alsrca, src); m4 #(WIDTH) srcm(write, CONST_ONE, instr[width-:], const4, alsrcb, src); m4 #(WIDTH) pcm(alreslt, alot, const4, CONST_ZERO, pcsorce, netpc); m #(WIDTH) wdm(alot, md, memtoreg, wd); regfile #(WIDTH,REGBITS) rf(clk, regwrite, ra, ra, wa, wd, rd, rd); al #(WIDTH) alnit(src, src, alcont, alreslt); zerodetect #(WIDTH) zd(alreslt, zero); Start at t level Logic Design Hierarchically decompose IPS into nits T-level interface crystal oscillator Clk reset memread memwrite IPS processor adr write mem eternal memory Verilog: ememory Verilog: ememory // eternal memory accessed by IPS modle ememory #(parameter WIDTH = ) (clk, memwrite, adr, write, mem); inpt clk; inpt memwrite; inpt [WIDTH-:] adr, write; otpt reg [WIDTH-:] mem; reg [:] RA [(<<WIDTH-)-:]; wire [:] word; initial $readmemh("memfile.dat",ra); // read and write bytes from -bit word if(memwrite) case (adr[:]) 'b: RA[adr>>][7:] <= write; 'b: RA[adr>>][5:] <= write; 'b: RA[adr>>][:] <= write; 'b: RA[adr>>][:4] <= write; assign word = RA[adr>>]; case (adr[:]) 'b: mem <= word[7:]; 'b: mem <= word[5:]; 'b: mem <= word[:]; 'b: mem <= word[:4]; // eternal memory accessed by IPS modle emem #(parameter WIDTH = ) (clk, memwrite, adr, write, mem); inpt inpt inpt otpt clk; memwrite; [WIDTH-:] adr, write; [WIDTH-:] mem; wire memwriteb, clkb; // UC RA has active low write enable... not(memwriteb, memwrite); // Looks like yo need to clock the memory early // to make it work with the crrent control... not(clkb, clk); // Instantiate the UC SPRA modle UCSPRA mips_ram (.CK(clkB),.CEN('b),.WEN(memwriteB),.OEN('b),.ADR(adr),.DI(write),.DOUT(mem)); Verilog: ememory Verilog: ememory Use makemem to generate memory Limited to 4 rows... Can bild it ot of mltiple SRAs SRA4 (for cies) Appro 454microns each... 5

6 Verilog: ememory Simlation model is the switch-level simlation of the Verilog strctral netlist Or yo cold write a behavioral model...

MIPS Architecture. An Example: MIPS. From the Harris/Weste book Based on the MIPS-like processor from the Hennessy/Patterson book

MIPS Architecture. An Example: MIPS. From the Harris/Weste book Based on the MIPS-like processor from the Hennessy/Patterson book An Eample: IPS From the Harris/Weste book Based on the IPS-like processor from the Hennessy/Patterson book IPS Architectre w Eample: sbset of IPS processor architectre n Drawn from Patterson & Hennessy