A Reconfigurable Arithmetic Datapath Architecture

Transcription

1 A Reconfigurle Arithmetic Dtpth Architecture Reiner W. Hrtenstein, Riner Kress, Helmut Reinig University of Kiserslutern Erwin-Schrödinger-Strße, D Kiserslutern, Germny Fx: , emil: Astrct A reconfigurle dt-driven rithmetic dtpth rchitecture for ALUs is presented which my e used for custom computing mchines, Xputers nd other dptle computer systems s well s for rpid prototyping of high speed dtpths. Fine grined prllelism is chieved y using simple reconfigurle processing elements which re clled dtpth units (DPUs). The word-oriented dtpth simplifies the mpping of pplictions onto the rchitecture. Pipelining is supported y the rchitecture. The progrmming environment llows utomtic mpping of the opertors from high level descriptions. Two implementtions, one y FPGAs nd one with stndrd cells re shown. 1. Introduction For numericl computtions with custom computing mchines, word-oriented dtpths re necessry. A recent trend in FPGA rchitectures moves towrd support of efficient implementtion of dtpth circuits. Xilinx XC4000 series [11] provides fst 2-it ddition t ech logic cell y specil crry circuit. AT&T's ORCA [6] supports lrger dt mnipultions. For exmple 16 it dder requires only four function locks. Word-oriented dtpths re not directly supported y FPGAs currently ville, since these circuits re evluted for oth rndom logic control nd dtpth pplictions. Word-oriented dtpths in reconfigurle circuits hve the dditionl dvntge of opertors eing mpped more efficiently. Thus they support progrmming environments for custom computing mchines. Hrdwre designers usully hve no prolem in using custom computing mchines, since most of the progrmming models these mchines provide re t hrdwre level. Algorithms hve to e expressed y hrdwre description lnguge. Then they hve to e synthesized to the dedicted hrdwre, or the ppliction hs to e edited vi schemtic editor nd mpped y n FPGA vendor tool [2], [1]. People coming from the softwre side re more used to progrm with procedurl high level lnguge. To mke custom computing mchines more interesting to such people, procedurl model for high level progrmming is needed. Some custom computing mchines, consisting of n ccelertor ord nd host, support function clls from high level lnguges to e executed on the ccelertor ord, ut they re not le to configure the ord from this level, e. g. [3]. Some reserchers strt to evlute compilers for their ords to compile high level input lnguge directly. Gokhle nd Minnich [4] for exmple present such compiler to progrm n rry of FPGA chips in high level prllel C using SIMD progrmming model. However still prolems re the utomtic mpping of loops, rithmetic nd logic opertors. This pper introduces n Xputer [8] sed methodology solving these prolems which strongly supports rithmetic pplictions. The Xputer provides hrdwre nd softwre environment for reconfigurle ALU (ralu). The ralu hs to compute user defined compound opertor only. A compiler for the Xputer supports the high level lnguge C s input. The ralu progrmming environment hs to compile rithmetic nd logic expressions s well s conditions into the ralu. The mchine prdigm of the Xputer is descried in [7]. The reconfigurle dt-driven ALU proposed here, consists of the ralu control nd the reconfigurle dtpth rchitecture (rdpa). The rdpa is word-oriented sclle regulr rry of simple processing elements clled dtpth units (DPUs). The DPUs provide higher grnulrity of the sic function units thn usul FPGAs. This supports utomtic mpping of rithmetic nd logic opertors to the rdpa. Using the Xputer with the dtdriven ralu llows the progrmming from high level lnguge. The rchitecture does not only fit s reconfigurle ALU for Xputers, it my lso e used for ny other - 1 -

2 kind of dptle computer system s well s universl ccelertor coprocessor or for rpid prototyping of high speed dtpths. First, this pper gives short introduction to the hrdwre environment. Section 3 introduces the rdpa. An implementtion with commercil FPGA chips nd one with stndrd cells is shown nd oth re compred to ech other. The usge s ralu for Xputers is explined in section 4. The progrmming environment llows the mpping of opernds nd conditions to the rdpa utomticlly (section 5). The finl sections present n exmple nd conclude the pper. 2. Hrdwre environment Dt Sequencer Control Memory Instr. Sequencer Generic Address Genertor Generic Address Genertor MoMus Bus interfce VMEus Scn Window ralu Sunet Scn Window ralu Sunet Scn Window ralu Sunet Mny pplictions require the sme dt mnipultions to e performed on lrge mount of dt, e. g. sttement locks in nested loops. Xputers re especilly designed to reduce the von-neumnn ottleneck of repetitive decoding nd interpreting ddress nd dt computtions. High performnce improvements hve een chieved for the clss of regulr, scientific computtions [7], [8]. An Xputer consists of three mjor prts: the dt sequencer, the dt memory nd the ralu including multiple scn windows nd opertor sunets. Scn windows re kind of window to the dt memory. They contin ll the dt, which re ccessed or modified within the ody of loop. The dt mnipultions re done y the ralu sunets, which hve prllel ccess to the scn windows. The scn windows re updted y their corresponding generic ddress genertors, which re the most essentil prt of the dt sequencer. Ech generic ddress genertor cn produce ddress sequences which correspond to up to three nested loops under hrdwre control. The term dt sequencing derives from the fct tht the sequence of dt triggers the opertions in the ralu, insted of von-neumnn instruction sequence. Pipelining cross loop oundries is supported. Generlly, for ech nesting level of nested loops seprte ralu sunet is required to perform the computtions ssocited with tht nesting level. For most lgorithms, only three nested loops re necessry for the computtion, this mens tht in the worst cse three ralu sunets re sufficient. The ralu sunets perform ll computtions on the dt in the scn windows y pplying user-configured complex opertor to tht dt. The sunets need not to e of the sme type. Sunets cn e configured for rithmetic or it level opertions. The dt-driven reconfigurle dtpth rchitecture proposed here is well suited for rithmetic, nd in the FPGA version lso for it level opertions. The Xputer prototype, Mp-oriented Mchine 3 (MoM- 3), hs direct ccess to the host's min memory. The ralu sunets receive their dt directly from locl memory or Host Min Memory Figure 1. The Xputer prototype Mp-oriented Mchine 3 (MoM-3) vi the MoMus from the min memory. The MoMus hs n synchronous us protocol. The dtpth rchitecture is designed for the synchronous us protocol of the MoMus, ut it cn lso e used y synchronous us with minor modifictions. Figure 1 shows our prototype MoM Reconfigurle dtpth rchitecture The rdpa is the dt mnipultor of the dt-driven ralu. The rdpa ws designed to evlute ny rithmetic nd logic expression from high level description. Therefore the grnulrity of the sic opertion is incresed from the itwise level to wordlevel with possile opertions such s ddition or multipliction. This gretly simplifies the utomtic mpping onto the rchitecture. A regulr structure like in systolic rrys is required for the sclility, lso cross chip oundries. Systolic rry structures comine intensive locl communiction nd computtion with decentrlized prllelism in compct pckge. The sic cell of the rdpa is clled dtpth unit (DPU). Ech DPU hs two input nd two output registers which my form some prt of the scn window of the Xputer prdigm. The dtflow direction is only from west nd/or north to est nd/or south. The communiction etween the neighouring DPUs is synchronized y hndshke. This voids prolems of clock skew nd ech DPU cn hve different computtion time for its opertor. The opertion in the DPU is dt-driven, this mens tht the opertion is evluted when the required opernds re ville. After completion of the opertion, the result in the output register of the DPU is declred to e vlid

3 As soon s the input registers of the succeeding DPU re free, the dt will e trnsferred nd the next computtion strts. In systolic rchitectures the high I/O requirements often mke the integrtion into chips prolem. To reduce the numer of input nd output pins, seril link is used for dt trnsfer etween neighour DPUs (32 its re converted into series of 2 it niles), s shown in figure 2. prllel to seril converter I/O us chip 1 seril op op op link seril to prllel converter PCB Figure 2. The sclle rdpa rchitecture etween chip oundries A glol I/O us hs een implemented into the rdpa permitting the DPUs to write from the output registers directly outside the rry nd to red directly from the outside. This mens input dt to expressions mpped into the rdpa do not need to e routed through the DPUs. Principlly, the glol I/O us is used for reding nd writing the scn window contents to the rry. A single us is sufficient for our Xputer prototype MoM-3 since the dt from the min memory of the host is mde ville y the us lso. For other systems it my e etter to hve dedicted input nd output us. The communiction etween the outside control unit nd the DPUs is synchronized y hndshke like the internl communictions. Ech DPU which hs to communicte using the glol I/O us gets n ddress for its input nd/or output register during configurtion. The rdpa control unit cn ddress DPU register directly using the us. The DPU where the ddress mtches performs the hndshke with the outside control unit nd receives or sends the dt. The propgtion of interim results, which ccounts for the lrgest unch of communiction, is hndled through the internl communiction pths, nd therefore fully prllel. An extensile set of opertors for ech DPU is provided y lirry. The set includes the opertors of the progrmming lnguge C. Other opertors such s the prllel prefix opertor re provided. The prllel prefix opertor [5] hs n internl feedck. For exmple queue of scnmx opertors cn e used for esy implementtion of hrdwre ule sort [10]. The scn-mx computes the mximum from the input vrile nd the internl feedck vrile nd gives the mximum s result nd stores the other vlue internlly. Opertors cn lso e used for chip 2 routing, even mixed with other opertions, e. g. first multiply with nd write the result to the south, then route vrile to the est. Conditions re implemented in the rdpa in the following wy. Ech communiction chnnel hs n dditionl condition it. If this it is true, the opertion is computed, otherwise not. In ech cse the condition it is routed with the dt using the sme hndshke. The condition opertor sends to one neighouring DPU true condition it, to the other one flse it. The 'flse' pth is evluted very quick, ecuse the condition it is routed only. With this technique lso nested if_then_else sttements cn e evluted. An exmple is shown in figure 3. The then nd theelse pth cn e merged t the end with merge opertor (m). This opertor routes the vlue with the vlid condition it to its output. With the proposed sclle model for the rdpa, the rry cn e expnded lso cross printed circuit ord oundries, e. g. with connectors nd flexile cle. This mkes it possile to connect the outputs of the est rry oundry with the west one, to uild torus. The sme is possile for the south nd the north. With the dt-driven concept, the user need not worry out synchroniztion. For the implementtion of the rdpa two possiilities re presented. The first is sed on FPGAs nd the second one is the sed on stndrd cells. 3.1 FPGA implementtion of the rdpa The communiction model of the DPU cn e implemented into SRAM sed FPGAs. A lrge reconfigurle dtpth rchitecture cn e implemented into multiple FPGA chips. The FPGA chips re rrnged in n rry with single us nd configurtion lines to ech chip. All ) ) Figure 3. sttement t w if ( < ) (1) if ( > c) (2) x = u v * w; (3) else (4) x = u - s * w; (5) else (6) x = w * t v * z; (7) < v < s z > c c<< v w w - (<)&(c) Exmple of nested if_then_else u m m u x - 3 -

4 other wiring is locl, therefore no field progrmmle interconnect component (FPIC) is required. On ech FPGA, n rry of DPUs is implemented depending on the size of the FPGA nd the complexity of the opertors. If complex opertor like multipliction is implemented into n FPGA, the other DPUs cn only e used for routing or simple opertors in this chip. The rdpa progrmming environment, presented in section 5 tkes this fct into considertion. The implementtion of the DPUs using FPGAs hs the dvntge tht speed criticl opertors cn e implemented fully or prtly in prllel if necessry. Also the opertions itself cn e pipelined. The progrmming environment detects the criticl pth with the criticl opertions. Slow ripple crry dders cn e sustituted y conditionl sum dders or other fster dders. A lirry of opertors, which cn e extended, is ville in the rdpa progrmming environment. The communiction chnnels re ll the sme for ech DPU. The progrmmer hs to put the mcros for the opertors nd the communiction together in schemtic editor. Then the DPUs re mpped with vendor tool to the FPGA structure. This is done for ech FPGA, no prtitioning is necessry. Especilly it level opertors re well suited for FPGA implementtion. The DPUs re smller, fster nd lrger numer cn e implemented on chip. Different widths of the dtpth cn e used lso. 3.2 Stndrd cell implementtion of the rdpa The rdpa implemented with stndrd cells hs 32 it dtpth. The opertors of the DPUs re configurle with fixed ALU nd microprogrmmed control. This mens opertors such s ddition, sutrction or logicl opertors cn e evluted directly, wheres multipliction or division re implemented sequentilly. A lirry of opertors is ville nd new opertors cn e uild with microssemler. The stndrd cell implementtion of the proposed model hs higher density of the rithmetic opertions nd the dely times re known for ech opertion. The time for synthesis of the ralu ord is reduced ecuse the opertors in the DPUs re microprogrmmed.as mentioned efore the rry is sclle y using severl chips of the sme type. The DPUs hve no ddress efore configurtion since ll chips re identicl. The DPUs re identified y their loction in the rdpa rry. Consequently ech DPU hs n x- nd y-ddress like the elements in mtrix. A configurtion word consists of configurtion it which distinguishes the configurtion dt from computtionl dt. Furthermore it consists of the x- nd the y-ddress, the ddress of the DPU s configurtion memory, nd the dt for this memory. Ech time configurtion word is trnsferred to DPU, the DPU checks the x- nd the y-ddress. If the y-ddress is lrger thn zero nd the x-ddress is lrger thn zero, the DPU checks if the neighoring DPUs re usy. If the neighoring DPU in y-direction is not usy, the y-ddress will e decresed y one nd the resulting configurtion word will e trnsferred to this DPU. If the DPU in y- direction is usy nd the DPU in x-direction is not usy the x-ddress will e decresed y one nd the resulting configurtion word will e trnsferred to this DPU. If oth neighouring DPUs re usy, the DPU wits until one finishes. With this strtegy n utomtic lod distriution for the configurtion is implemented. If the y-ddress is lrger thn zero nd the x-ddress is zero, the ddress will e decresed y one nd the configurtion word will e trnsferred to the next DPU in y-direction. If the y-ddress is zero nd the x-ddress is lrger thn zero, the x-ddress will e decresed y one nd the configurtion word will e trnsferred in x-direction. If oth ddresses re zero, the trget DPU is reched, nd the ddress of the DPU s configurtion memory shows the plce where the dt will e written. Becuse of the lod distriution in the rdpa rry, one seril link t the rry oundry is sufficient to configure the complete rry. The physicl chip oundries re completely trnsprent to the user. The communiction structure llows dynmic in-circuit reconfigurtion of the rdpa rry. This implies prtil reconfigurility during runtime [9]. Further the configurtion technique llows to migrte designs from smller rry to lrger rry without modifiction. Even newer genertion rdpa chips with more DPUs integrted do not need recompiltion of the configurtion dt. The configurtion is dt-driven, nd therefore specil timing does not hve to e considered. With the proposed model for the DPA, the rry cn e expnded lso cross printed circuit ord oundries, e. g. with connectors nd flexile cle. Therefore it is possile to connect the outputs of the est (south) rry oundry with the west (north) one, to uild torus. 4. Reconfigurle dt-driven ALU A sunet of the reconfigurle dt-driven ALU consists of two min prts: the control for the ralu nd the reconfigurle dtpth rchitecture, s shown in figure 4. Sunets cn run in prllel. Here the connection to the MoMus is shown only. The register file is useful for optimizing memory cycles, e. g. when one dt word of sttement will e used lter on in nother sttement. Then the dt word does not hve to e red gin over the externl us. In ddition, the register file mkes it possile to use ech DPU in the rdpa for opertions y using the internl us - 4 -

5 FIFO glol I/O us sttus configurtion MoMus to GAGs, Host, Min Memory rdpa ddress genertion unit register file rdpa control unit rdpa Figure 4. One sunet of the reconfigurle dtdriven ALU for routing. If different expressions hve common suexpression, this suexpression hs to e computed only once. If the rdpa does not provide the routing cpcity for this reduction, e. g. if three or more suexpressions re in common, the interim result cn e routed through the register file. The ddress genertion unit delivers the ddress for the DPU registers efore ech dt is written into the rdpa over the us. The rdpa control unit holds progrm to control the different units of the dt driven ralu. The instruction set consists of instructions for loding dt into the rdpa to specific DPU from the MoMus or the register file, for receiving dt from specific DPU, or rnches on specil control signl from the generic ddress genertors. The rdpa control supports context switches etween three control progrms which llows to use three independent virtul ralu sunets. The control progrm is loded during configurtion. The reconfigurle dt-driven ALU llows lso pipelined opertion s shown in the exmple in section 6. A sttus cn e reported to the generic ddress genertors (GAG) to inform on overflows or to force the GAGs to compute dt dependent ddresses. The input FIFO is currently only one word deep for ech direction. This is sufficient ecuse the dt flow is regulr to the min memory. Normlly the ralu does not hve to wit for dt. 5. Progrmming environment Sttements which cn e mpped to the rdpa rry re rithmetic nd logic expressions s well s conditions. Loops re hndled y the generic ddress genertors. The input lnguge for progrmming the ralu is the ralu progrmming lnguge. The syntx of the sttements follows the C progrmming lnguge syntx (see lso figure 3). In ddition, the lnguge provides the size of the used scn windows nd the next hndle position (reltive to the ctul position). The hndle position is the lower left corner of the oundry of the scn window. By providing the hndle position the ralu gets the necessry informtion for pipelining the complete sttement lock. The ralu progrmming lnguge file is prsed nd dt structure like n strct progrm tree is computed. Common suexpressions re tken into considertion. The opertors of ech sttement re llocted with stright forwrd lgorithm. The numer of DPUs used is optimized. Ech llocted opertor is then ssocited to DPU in the ralu rry. To recognize possile prlleliztion nd to find dt dependencies etween the sttements, dt dependency nlysis is performed. Due to the glol I/O us of the rdpa rry, the loding of the dt nd the storing re restricted to one opertion per time. For est performnce, n optiml sequence of these I/O opertions hs to e determined. Compring n s soon s possile (ASAP) with n s lte s possile (ALAP) schedule, the time criticl pth is detected. A priority function is developed from these schedules which gives the rnge of the I/O opertions of the opernds. With list sed scheduling method the optiml sequence of the I/O opertions is found. Memory cycles cn e optimized using the register file when the scn pttern of the GAGs works with overlpping scn windows. The rdpa configurtion file is computed from the mpping informtion of the DPUs nd lirry with the code of the opertors. The configurtion file for the ralu control unit nd the configurtion file for the GAGs is extrcted from the finl schedule of the I/O opertors. For the FPGA implementtion, the mcros for the necessry opertions re provided. The user hs to put them together with templte of the communiction in schemtic editor. The mpping is done y vendor tool e. g. from Xilinx. Alterntively the environment provides hrdwre description lnguge file which hs to e synthesized with synthesis tool, e. g. Synopsys. The progrmming environment of the ralu is shown in figure

6 new opertors Lirry of Opertors Configurtion Code Genertion Configurtion File reconfigurle Dtpth Architecture Figure 5. ralu Progrmming Lnguge Alloction of the Opertors ralu Control File APT, Dt Structure Control Reg. File Prser ralu Dt Dependency Anlysis Scheduling & Memory Optimiztion Code Genertion for ralu nd GAG Control GAG Control File Generic Address Genertor 6. Exmple: two dimensionl FIR filter GAG The ralu progrmming environment The two dimensionl FIR (finite impulse response) filter is one whose impulse response processes only finite numer of nonzero smples. The eqution for generl two dimensionl FIR filter is y nm = k ij x n i, i j m j. (1) In this exmple two dimensionl filtering of second order is shown. Since the focus on this pper is only on the ralu for Xputers, the ddress genertion for the dt is not explined, plese refer to [8]. Suppose the processed dt is written into the sme memory from which the dt is red, one scn window is sufficient. It is of the size 3 y 3 s shown in figure 6c. All 9 scn window positions re for reding nd the middle is lso for writing. The window scns over the dt mp with video scn, step width one. After ech step it performs the eqution: w 11new = w 22 k 22 w 12 k 12 w 02 k 02 w 21 k 21 w 11 k 11 w 01 k 01 w 20 k 20 w 10 k 10 w 00 k 00 The k ij re the coefficients of the filter nd the w ij contin the dt t the corresponding scn window positions. (2) Figure 6 shows eqution (2) mpped into the rdpa. The input registers of the DPUs nmed with w ij represent the scn window positions. The input registers nmed with k ij represent the registers with coefficients of the FIR filter loded t configurtion. At ech step of the scn window three new dt words re loded, three old ones re removed nd one output word is written ck. Figure 6c shows the loding of the dt. At the eginning, dt word 0 is loded cross the us directly to w 00, 0 to w 01, c 0 to w 02, 1 to w 10 nd so on. As soon s dt words rrive in the input registers of the DPUs the opertion will e performed (dt-driven). As shown in figure 6 the multiply-route opertion evlutes the multipliction nd routes the input dt from west to the next DPU est. So the dt required in the next step need not to e loded gin cross the us. The pipeline is filled y loding the first nine input dt words over the us, then the internl routing resources re used. Only the three new dt words hve to e routed y the us. The prototype implementtion of the rdpa works with 32 it fixed-point nd integer input words. Currently the host computer's memory is very slow. The clock frequency of the system is 25 MHz. In mny pplictions the coefficients re set up in such wy tht shift opertions re sufficient nd multiplictions re not necessry. If high throughput is needed, DPUs cn e linked together to implement pipelined multiplier. Benchmrk results re given in tle 1. The performnce figures re worst cse estimtion of our prototype. The speed of the exmples 2 to 5 depend not on the order of the filter s long s the necessry hrdwre (numer of DPUs) is provided. The sme is pplies for exmple 6. ) k 22 k 12 k 02 w 22 w 12 w 02 k 21 k 11 k 01 w 21 w 11 w 01 k 20 k 10 k 00 w 20 w 10 w 00 w 02 w 12 w 22 w 00 w 10 w y w 11new Figure 6. ) Two dimensionl FIR filter mpped into the rdpa, ) equivlent opertion of the multiply-route opertion, c) the corresponding scn window c) w 01 x ) w 11 w 21 <=> d c - 6 -

7 # Algorithms Opertions # of DPUs Time Steps per Opertion Performnce Fst Fourier Trnsformtion *,, ms 2 FIR filter, n th order *, 2(n1) ns/dt word 3 FIR filter, n th order shift, 2(n1) ns/dt word 4 n m two dim. FIR filter *, 2(n1)(m2) ns/dt word 5 n m two dim. FIR filter shift, 2(n1)(m2) ns/dt word 6 Bulesort, length n scn-mx n ns/dt word Tle 1. Benchmrk results 7. Conclusions A progrmming model for n FPGA sed hrdwre pltform for dt-driven reconfigurle dtpth rchitecture (rdpa) hs een presented which strongly supports numericl pplictions. It my e used s reconfigurle ALU (ralu) for custom computing mchines (CCMs), Xputers nd other dptle computer systems s well s for rpid prototyping of high speed dtpths. Together with the Xputer hrdwre nd softwre environment system hs een implemented which is progrmmle in high level lnguge. The word-orienttion of the dtpth nd the increse of the fine grnulrity of the sic opertions gretly simplifies the utomtic mpping onto the rchitecture. The sclle rdpa provides prllel nd pipelined evlution of the compound opertors. An implementtion with FPGA chips nd one with stndrd cells is shown. The FPGA implementtion supports vrile width of dtpths, lso for it level opertions. The stndrd cell version of the implementtion of the rdpa is microprogrmmle. It provides higher density of the opertors. The rchitecture is in-circuit dynmiclly reconfigurle, which implies lso prtil reconfigurility t runtime. A prototype chip with stndrd cells hs een completely specified in the hrdwre description Verilog nd will e sumitted for friction to the Eurochip 1 orgniztion soon. It hs 32 it dtpths nd provides rithmetic resources for integer nd fixed-point numers. The FPGA version is eing implemented y using Xilinx softwre tools. The progrmming environment is specified nd is eing implemented on Sun SPARCsttions. References [1] J. M. Arnold: The Splsh 2 Softwre Environment; IEEE Workshop on FPGAs for Custom Computing Mchines, FCCM'93, IEEE Computer Society Press, Np, CA, pp , April Eurochip is microelectronics project of the CEC. [2] S. Csselmn: Virtul Computing nd The Virtul Computer; IEEE Workshop on FPGAs for Custom Computing Mchines, FCCM'93, IEEE Computer Society Press, Np, CA, pp , April 1993 [3] N. N.: Gig Ops: Technicl Overview of C to Hrdwre Compiltion nd Development System for FPGA Computing; Pre-Relese Documenttion, Rev. 0.7, Gig Opertions Corportion, Berkeley, 1993 [4] M. Gokhle, R. Minnich: FPGA Computing in Dt Prllel C; IEEE Workshop on FPGAs for Custom Computing Mchines, FCCM'93, IEEE Computer Society Press, Np, CA, pp , April 1993 [5] S. A. Guccione, M. J. Gonzlez: A Dt-Prllel Progrmming Model for Reconfigurle Architectures; IEEE Workshop on FPGAs for Custom Computing Mchines, FCCM'93, IEEE Computer Society Press, Np, CA, pp , April 1993 [6] D. Hill, B. Britton, B. Oswld, N.-S. Woo, S. Singh, C.-T. Chen, B. Krmeck: ORCA: A New Architecture for High-Performnce FPGAs; in H. Grüncher, R. W. Hrtenstein (Eds.): Field-Progrmmle Gte Arrys, Lecture Notes in Computer Science, Springer-Verlg, Berlin, 1993 [7] R. W. Hrtenstein, A. G. Hirschiel, M. Riedmüller, K. Schmidt, M. Weer: A Novel ASIC Design Approch Bsed on New Mchine Prdigm; IEEE Journl of Solid-Stte Circuits, Vol. 26, No. 7, July 1991 [8] R. W. Hrtenstein, A. G. Hirschiel, K. Schmidt, M. Weer: A Novel Prdigm of Prllel Computtion nd its Use to Implement Simple High-Performnce Hrdwre; Future Genertion Systems 7 (1991/92), p , Elsevier Science Pulishers, North-Hollnd, 1992 [9] P. Lysght, J. Dunlop: Dynmic Reconfigurtion of Fieldprogrmmle Gte Arrys; Proceedings of the 3rd Interntionl Workshop on Field Progrmmle Logic nd Applictions, Oxford, Sept [10] N. Petkov: Systolische Algorithmen und Arrys; Akdemie-Verlg, Berlin 1989 [11] N. N.: The XC4000 Dt Book; Xilinx, Inc.,