Assembly Language Design

Transcription

1 Assembly Language Design Instruction Set 1. Data Movement 2. Arithmetic 3. Logical 4. Conversion 5. Program Control 6. System Control Syntax & System Characteristics 1. Assembly Directives 2. Constants 3. Data Size 4. Multibyte Data Addressing 5. Registers 6. Operands

2 1. Data Movement memory to memory moves are not possible on a load/store system register instructions load/fetch, store, move/transfer, exchange, swap move multiple/fill clear/reset, set stack instructions push, pop/pull, move port instructions (implies ports are not memory mapped) in, out

3 2. Arithmetic constrained by the design of the ALU defined in terms of data types allowed addresses... considered to be unsigned integers numbers... defined by type, length, and representation

4 2. Arithmetic numbers integer or fixed point signed/unsigned sign-magnitude, 1's complement, 2's complement extended precision floating point decimal short, long, extended precision format of mantissa, exponent, and bias packed decimal storage format vs execution format pure binary-coded-decimal instructions decimal adjust instruction; calculation done in binary and result converted to BCD with decimal adjust

5 2. Arithmetic instructions... add, subtract, multiply, divide with/without carry absolute, negate increment, decrement sign extension, length conversion compare (2 operands), test (1 operand vs 0)

6 3. Logical constrained by design of the ALU instructions... and, or, exclusive or, not set, clear... at bit level shift... left, right, arithmetic, logical rotate... left, right, through carry or extend bit shift and rotate are not necessarily part of the ALU

7 4. Conversion specialized instructions for certain applications instructions... translate... translate values in a section of memory based on a table of correspondences convert... convert the contents of a word from one form to another

8 5. Program Control instructions... unconditional branch, unconditional jump, unconditional skip (absolute or relative addressing) conditional branch, conditional jump, conditional skip (constrained by condition code register) subroutine call, return, return with skip execute... fetch operand from a specified location and execute as an instruction; PC is not modified

9 5. Program Control condition codes... carry, extended carry, auxiliary carry (BCD), overflow, parity, sign/negative, zero condition code bits/flags may be set, cleared, or unaffected during the execution of an instruction consider... minimum requirements calculated in software? implemented in hardware? trade-offs

10 5. Program Control condition codes... trigger... on almost all instructions? only on arithmetic or logical instructions? require that a special command be issued to set the condition codes (CMP, TEST)? a limited set of arithmetic instructions modify condition codes? ALU operations? data movement?... h/w implications?

11 5. Program Control condition codes... examples... M68000 ADDI.W #1,D0 where D0.W = $FFFE = (-2) 10 result D0.W = flags.. Zero = Sign = Overflow = Carry = Auxiliary Carry = Extended Carry = M68000 ADDI.W #$8001,D0 where D0.W = $FFFE result D0.W = flags.. Zero = Sign = Overflow = Carry = Auxiliary Carry = Extended Carry =

12 5. Program Control subtraction and the carry bit example... 28AF - B408 carry bit = 1 (borrow) example A0F carry bit = 0 (no borrow)

13 5. Program Control signed branches example... assume (D0.W) = $7FFA (MC68000) CMPI.W #-8,D0 CMPI.W #-8,D0 BPL label BGE label => CMPI computes $7FFA - (-8) => flags: Zero = 0, Sign = 1, Carry = 1, Overflow = 1 => BPL (plus) --> no branch because Sign = 1 => BGE (greater or equal) --> branch because destination > source

14 5. Program Control unsigned branches used with addresses, characters, and unsigned arithmetic unsigned numbers are interpreted as positive numbers operations do not generate signed overflow function defined in terms of carry and zero

15 5. Program Control unsigned branches Branch high dest > source Branch high or same dest >= source (branch on carry clear) Branch low dest < source (branch on carry set) Branch low or same dest <= source

16 5. Program Control example: assume ADDR = $ and (A0) = $000004FE CMPA.W #ADDR,A0 CMPA.W #ADDR, A0 BLE label BLS label => CMPA computes 04FE => flags: Zero = 0, Sign = 0, Carry = 1, Overflow = 0 => BLS (lower or same) --> branch since carry set => BLE (less than or equal) --> no branch since Sign=Overflow=0

17 some typical branch codes (not exhaustive): carry clear (CC/NC) overflow clear (VC/NO) not sign (NS) not zero (NZ) not parity (NP); parity odd (PO) not equal (NE) true (T) plus (PL) higher (HI/NLS); above (A) higher or same (HS/NLO); above or equal (AE) greater than (GT/NLE) greater than or equal (GE/NLT) carry set (CS/C) overflow set (VS/O) sign (S) zero (Z) parity (P); parity even (PE) equal (EQ) false (F) minus (MI) lower (LO/NHS); below (B) lower or same (LS/NHI); below or equal (BE) less than (LT/NGE) less than or equal (LE/NGT)

18 6. System Control instructions... operating system call... causes an interrupt, which passes control to the operating system halt or stop wait/hold... stop program execution, test a specified condition continuously; when the condition is satisfied, resume execution vectored/nonvectored interrupts; enable and disable interrupt

19 Syntax and System Characteristics 1. Assembly Directives instructions to the assembler (not really part of the assembly language) origin, end, equate, set define constant, reserve storage 2. Constants numeric constants... binary, decimal, hex, octal prefix, suffix character... strings, ASCII, EBCDIC location counter reference typically, * (M68000) or $ (PIC), e.g. BR *+5

20 Syntax and System Characteristics 3. Data Size bit operations basic word size: data and address variations per instruction explicit reference on operation is preferred to implied sizing, e.g. MC68000 vs Intel 8086 or only handle one size of data e.g. PIC

21 Syntax and System Characteristics 4. Multibyte Data Addressing usually fixed for an architecture must be selected when designing the machine language byte ordering criteria... big endian little endian bi-endian faster for comparing character strings faster, less confusing, decimal and ASCII dumps consistent order for storing integers and characters easier to perform multiprecision arithmetic easier to convert a 32 bit address into a 16 bit address supports both modes on a process basis machine state register has 1 bit for the endian mode of the kernel and 1 bit for the endian mode of the current process example PowerPC

22 Syntax and System Characteristics 4. Multibyte Data Addressing bit ordering criteria... are the bits labelled from 0 or from 1, i.e. for 8 bits, 0 to 7 or 1 to 8? what is the bit order? may/may not be consistent with byte ordering what is the order for transmission on a bit serial line? is this important? combining byte and bit ordering... right-end addressing byte order little endian bit order from most significant to least significant (least significant at right) used by VAX, 80x86 (Intel), Alpha left-end addressing byte order big endian bit order from least significant to most significant (least significant at left) used by IBM mixed addressing byte order big endian bit order from most significant to least significant (least significant at right) used by Motorola 68000, SPARC, RISC

23 Syntax and System Characteristics 5. Registers types.. accumulator(s) typically 1, sometimes 2 all data must go through the accumulator for data transfers to/from memory and for any ALU operation special registers usually addressing registers e.g. index, base, or stack pointer registers general purpose registers can be used by any instruction (with a few restrictions) may be grouped as data and address registers if length of the two register types are different typical configurations... accumulator and special registers accumulator and general registers general registers; may have data/address distinction

24 Syntax and System Characteristics 6. Operands must decide on the number of operands in each instruction must decide on the order of operands; be consistent! has implications for the bus architecture of dataflow sections never make the programmer specify an implied register

25 Syntax and System Characteristics 6. Operands choices... 0 operands instruction conveys all information e.g. negate on an accumulator based machine e.g. stop if no transfer to operating system 1 operand need address for one operand e.g. negate on a general purpose machine either the source or destination is implied e.g. move on an accumulator machine e.g. stop if transfer to operating system

26 Syntax and System Characteristics 6. Operands choices... 2 operands one source and one destination e.g. move on a general purpose machine one source and one destination where destination is also a source e.g. an add on a general purpose machine 3 operands two source and one destination e.g. an add on a general purpose machine 4+ operands special functions with more than two sources e.g. string processing