Chapter 1. Microprocessor, Microcontroller and Programming Basics

Transcription

1 Curse bjectives Chapter 1 Micrprcessr, Micrcntrller and Prgramming Basics t develp an in-depth understanding f the peratin f micrprcessrs and micrcntrllers machine language prgramming micrprcessr interfacing techniques t be able t use Mtrla 68HC11 micrcntrller cmpetently t be able t design and implement micrprcessr-based systems in bth hardware and sftware t be able t apply this knwledge t mre advanced structures Cmmn cmputer rganizatin ALU (Arithmetic Lgic Unit) is a circuitry, which is capable f ding varius peratins (fr example ADD, SHIFT, AND, OR, etc) n certain n-chip registers. CPU (Central Prcessing Unit) is the cmbinatin f the cntrl lgic, assciated registers and the arithmetic lgic unit. Cmputer buses Address bus: carries the address f a unique memry r input/utput (I/O) device 1

2 Data bus: carries data stred in memry (r an I/O device) t the CPU r frm the CPU t the memry (r I/O device) Cntrl bus: is a cllectin f cntrl signals that crdinate and synchrnize the whle system Blck diagram f a typical CPU CPU structure The main functins are data transfer arithmetic and lgic peratins decisin making (instructinal flw cntrl) The register array cnsists f at least ne accumulatr, prgram cunter and stack pinter. The cntrl unit cntrls all the peratins in a CPU and basically it puts the CPU in ne f the fetch and executin phases. Memry The memry in a cmputer system stres the data and instructins f the prgrams. 2

3 Main memry types ROM (read-nly memry) prgrammed permanently at the factry, cannt be altered RAM (randm-access memry) read and write memry EPROM (erasable prgrammable ROM) nnvlatile, written electrically but erased ptically EEPROM (electrically ROM) nnvlatile, bth written and erased electrically Operatin f the CPU 3

4 Fetch cycle (phase): The CPU puts the address f the instructin t be executed n the address bus. The address infrmatin cmes frm the prgram cunter (PC) maintained by the cntrl unit. The cntrl bus hlds the infrmatin fr reading the memry lcatin and the data bus hlds the instructin frm the memry which is stred int the instructin register (IR) PC is updated t pint t the next instructin. Execute cycle (phase): Instructin in the IR is decded The required data transfer and the required lgical and arithmetic peratin are perfrmed The result is written back either t ne f the registers r memry r I/O device Cmmn peratins perfrmed in ALU are: additin, subtractin, lgical AND, OR, XOR, NOT increment, decrement, shift, clear, etc. Micrcmputer CPU n a single IC micrprcessr (µp). The terms CPU, µp and MPU (micrprcessr unit) are synnymus CPU is the cmbinatin f the ALU and cntrl unit f any cmputer. When the CPU is a single IC; it is called a µp and is als referred t as the MPU. When the MPU is cnnected t memry and I/O, the arrangement becmes a MICROCOMPUTER. Many different MPUs are prduced by many different IC vendrs (e.g., Mtrla, Intel, Texas Instruments, Zilg, Natinal Semicnductrs, etc.). Majr differences are in wrd size, the number and types f instructins that can be perfrmed, the types f external cntrl signals available, the amunt f memry that can be addressed. 4

5 Micrcntrller A micrcntrller unit (MCU) cntains an MPU, memry, and I/O circuitry n a single chip. Such a chip can perfrm cntrl peratins withut the need fr any external circuitry. e.g. Mtrla MC68HC11 (als a micrprcessr in the expanded multiplexed mde)e.g. Intel 8051 Micrprcessrs vs micrcntrllers Micrprcessrs: high perfrmance, general purpse brains fr PCs and wrkstatins Instructin decde and cntrl, arithmetic/lgic peratins, registers, timing, external cntrl Typical cst: $75 -- $500, Annual demand: 10s f millins Micrcntrllers: devices with high levels f integratin fr embedded cntrl Micrprcessr functins plus n-chip memry and peripheral functins (e.g. prts, timers) "Swiss army knife" f micrprcessr technlgy Typical cst: $1-- $25, Annual demand: billins! Micrprcessr Includes memry management unit, lts f cache Perfrmance is the mst imprtant feature (cst is imprtant, but secndary) Used mainly in desktp machines Micrcntrller Integrated RAM and ROM, n cache Includes lts f peripherals Used mainly in embedded applicatins and ften invlves real-time cntrl Imprtant features include: lw cst, lw pwer cnsumptin, number f integrated peripherals, interrupt respnse time, amunt f RAM and ROM Bttm-up view f micrcntrller systems 5

6 Micrcntrller applicatins Pcket pagers (lw-pwer, interprets characters, user interface) Cameras (lw-pwer, expsure and fcus cntrl, user interface) "Levelmeter (measures angle, audible and visual user interface) Keybard cntrllers (scanning, debunce, autrepeat, diagnstics) Mdems (ne fr data transmissin, n fr cmmand prcessing) Pltters (cmmand interpretatin, encders, mtr cntrl) Clr cpiers (paper psitining, clr expsure, sensrs) Charge card pay phnes (card reading, dialing, carrier access) Lawn sprinkler cntrller (timer, valve cntrl, user interface) Instrumentatin (user interface, GPIB interface, cmpute values) Clsed-lp engine cntrl (fuel/air mixture, ignitin, pressure sensing, etc.) Antilck braking system cntrl (mnitrs tractin, cntrls brake) Dynamic ride cntrl (adjusts suspensin) Blck Diagram f a Mtrla M68HC11 Based Applicatins Example: An Emergency Cntrl System Cmparisn f sme ppular micrcntrllers Mtrla HC11 The HC11 family includes a large number f variatins, ranging frm single-chips t larger micrs with bank-switching supprt. Mtrla HC12 6

7 The HC12 family is the next step up frm the HC11, ffering better perfrmance, better memry management, and mre features. Mtrla 6805 The 6805 family is the next step dwn frm the HC11, with mre single-chip variatins, smaller packages, and lwer cst. Micrchip PIC The devices are readily available, reasnably priced, very fast, and cme in lts f variatins, hwever, with small memry maps and pr supprt fr cmpilers. Intel 8051 The 8051 was ne f the first micrcntrller families, and remains ne f the mst cmmnly used. The devices are available frm multiple surces, are cheap, have decent tls, and ffer a nice upgrade path t larger and mre capable part. What is EE447 abut? MC68HC11 is the MPU chice in EE447 Yu will be studying hw it is cmbined with memry and I/O devices t prduce a 68HC11 based micrcmputer, and hw it is prgrammed t perfrm varius peratins Mst f what yu learn abut the 68HC11 can be applied t any ther MPU r micrcmputer yu may encunter later. Majr features f Mtrla M68HC11 HCMOS Technlgy (lw pwer / high speed) On- chip RAM, ROM, EEPROM Basic cre functins f MC6801 imprved instructin set functinality 2 perating mdes and 2 test mdes On-chip cunter / timer On-chip analg- t- digital cnversin On-chip parallel and serial prts Imprved interrupt capabilities than earlier prducts -- supprts 21 interrupt vectrs Sme fault detectin capability fr majr errrs (pwer, illegal instructin, hung prcessr) Available in at least 25 different versins Different pin cunts and packaging Different amunts/ types f memry RAM size (192 t 1.25K bytes) ROM size (4K t 32K bytes) EEPROM (512 t 2K bytes) ROM, EPROM, r EEPROM prgram memry Memry maps vary frm versin t versin! Different I/ O capabilities (number f timers, chip selects, DMA channels, A/ D types, etc.) Mdes f peratin 2 perating mdes and 2 test mdes Operating mdes Single chip N external address and data bus functins 7

8 CPU can nly access n-chip memry Prts B and C are general purpse parallel I/ O All sftware needed t cntrl MCU must be in internal memry On reset, executin begins at address $E000 Lcated in ROM Expanded multiplexed External memry and peripheral devices can be accessed by time-multiplexed address- data bus Prt B used fr high byte f address (utput) Prt C prvides lw byte f address (utput) and 8-bit data (bi-directinal) External address latch is required Executin begins at address $E000 Single chip mde Expanded multiplexed mde 8

9 Test mdes Special btstrap On pwer up r reset, the prgram in the btstrap ROM is executed CPU waits fr a 256-byte prgram segment t be dwnladed thrugh the serial link and stred starting at address $0000 Executin then begins at address $0000 Permits wide variety f prgrams t be dwnladed Special test Primarily a testing mde fr the manufacturer Overrides sme autmatic prtectin mechanisms -- risky! I/O Prts Prt A (8 bits) Als used fr timer Prt D (6 bits) Als used fr asynchrnus (SCI) and synchrnus serial (SPI) I/O Prt E (8 bits) Als used fr A/D cnverter Prt B (8 bits) Als used as address in expanded mde Prt C (8 bits) Als used as data/ address in expanded mde MC68HC11 detailed blck diagram 9

10 Prgramming languages Applicatin prgrams User runs an existing sftware package, Limited flexibility utside intended applicatin Examples: Excel, Netscape, Wrd,... High-level language (HLL) User writes prgrams t perfrm task(s) Very flexible, easy t use (nce language is learned!) Examples: C, C++, Java, Frtran Assembly language Harder t use than HLLs Machine and cnfiguratin dependent Requires detailed knwledge f the µp itself and its instructin set Still used where extremely high perfrmance, shrt prgrams are required Machine cde Native language f the prcessr itself Prgrams are the actual bytes as stred in memry Nt intended fr human cnsumptin Prgramming prcedure What features f the prcessr are mst imprtant t the assembly-language prgrammer? Register set Memry rganizatin Instructin set Addressing mdes 10

11 Register set Memry Organizatin On chip memry ROM (12K bytes) Factry prgrammed, Special btstrap ROM RAM (512 bytes) Data, stack Can be used fr dwnladed cde Lw-pwer standby mde EEPROM (512 bytes) Prgrammed and erased n-chip Calibratin strage, diagnstic lg, critical data lgging, security data Can als be used fr dwnladed cde Off-chip memry EPROM Fr prttype develpment Windwed and ne-time prgrammable versins 11

12 Instructin set The instructin set specifies the kinds f data transfers and transfrmatins that can ccur in the machine Instructins can be gruped int 5 brad categries Data transfers: instructins that mve data t and between registers Lgical: instructins that perfrm lgic peratins n data -- AND, OR, etc. Arithmetic: additin, subtractin, increment, etc. Flw cntrl: instructins that change the sequence f executin f a prgram -- cnditinal and uncnditinal branches, stack peratins, etc. Input / Output peratins An instructin generally cnsists f an pcde and sme perand(s) HC11 instructins are f different lengths (1-5 bytes) Opcdes 1-byte pcdes Mst pcdes use just 1 byte Dwnward cmpatible with byte pcdes Mst 2- byte instructins deal with register Y, which was nt present in the 6800 prcessr It takes lnger t fetch and execute 2- byte pcdes New instructins use a "pre- byte", which signals that anther pcde byte fllws: $18, $1A, r $CD Ex: INX $08 INY $18 $08 Instructin frmat An instructin is made up f an pcde and a set f perands Opcde may be ne r tw bytes Instructins may use 0, 1, 2, r 3 perands Operands may be 1 r 2 bytes Instructin lengths range frm 1 t 5 bytes Example (assume this is stred at address $E000): LDAA #$ FF; lad ACCA with the value $FF 12

13 Machine cde: $E000 $86 $E001 $FF Fetch/execute peratin Addressing mdes An instructin specifies the lcatin f the data that it is ging t prcess by using ne f the existing addressing mdes. M68HC11 has the fllwing six different addressing mdes, which are discussed in detail in Chapter 2: Inherent addressing Immediate addressing Extended addressing Direct addressing Indexed addressing Relative addressing 13