Chapter 7. Storage Components

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1 7. Storage Components 7- Chapter 7. Storage Components ntroduction Storage components store data and perform simple data transformations, such as counting and shifting. Registers, counters, register files, memories, etc. Register: a group of binary cells (FFs) suitable for holding binary information. n addition to the FFs, a register may have combinational gates that control when and how new information is transferred into the register. Counter: a register that goes through a predetermined sequence of states upon the application of input pulses. The gates in a counter are connected in such a way as to produce a prescribed sequence of binary states in the register. Memory unit: a collection of storage cells together with associated circuits needed to transfer information in and out of storage. For example, SRM & RM. Registers register can be viewed as a bitwise extension of a FF. The simplest of the storage components: n inputs, n outputs, and a clock signal. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

2 7. Storage Components 7- ll the n FFs are driven by the common clock signal. Registers are readily available as MS circuits, it becomes convenient at times to employ a register as part of the sequential circuit. The combinationalcircuit part of the sequential circuit can be implemented by any of the methods discussed in Chapters 4 & 5. -FFs are normally used for registers. The register may be enhanced by asynchronous Preset and Clear () signals, which are not controlled by the clock signal. Register (a) Graphic symbol (b) Register schematic Figure : 4-bit register [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

3 7. Storage Components 7- preet clear Register (a) Graphic symbol preset clear (b) Register schematic Figure : 4-bit register with asynchronous Preset and Clear [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

4 7. Storage Components 7-4 To be able to control when the data will be entered into a register, and for how long it will be stored there before being sent to the output, we add the Load (nable) input to form a parallel-load register. Load Register Present state Load Next state No change (a) Graphic symbol (b) Operation table Load Y Y Y Y (c) Register schematic Figure : Register with parallel load [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

5 7. Storage Components 7-5 Shift Registers shift register can shift the stored data right and/or left. Shift L Shift Register Present Next state state Shift No change L (a) Graphic symbol (b) Operation table L Shift Y Y Y Y (c) Register schematic Present state Operation S S Next state S S R L Shift Register No change Load input Shift left R Shift right L (a) Graphic symbol (b) Operation table L R S S Y Y Y Y (c) Register schematic Figure 4: Shift registers [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

6 7. Storage Components 7-6 Counters counter is a special type of register that counts upward, downward, or in any prespecified sequence. Clear Counter Operations No change Count i C i C i+ i (a) Graphic symbol (b) Operation table (c) H truth table C4 C C C C H H H H Clear Output carry (d) Counter schematic i C i C i+ i Up/own Counter Clear Operations No change Count up Count down (a) Graphic symbol (b) Operation table (c) HS truth table C 4 C C C C HS HS HS HS Clear Output carry (d) Logic schematic Figure 5: Binary up and up/down counters [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

7 7. Storage Components 7-7 Load Operations Load Up/own Counter No change Count up Count down Load the input (a) Graphic symbol (b) Operation table HS HS HS HS Load Output carry Y Y Y Y (c) Register schematic Figure 6: Binary up/down counter with parallel load [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

8 7. Storage Components 7-8 BC Counter BC counter counts in the sequence,,,, 4, 5, 6, 7, 8, 9,,... " " " " "" "" "" "" "" Load Up/own Counter "" Load Up/own Counter (a) BC up counter (b) BC up/down counter Figure 7: BC counters [Gajski]. synchronous Counter n asynchronouscounter counts without an incrementer or decrementer its FFs are not clocked by the same signal. Counting without an incrementer/decrementer is achieved by toggling each FF at half the frequency of the preceding FF. FF i changes state only half as often as FF i. FF i changes state only when FF i goes from to, but not from to. T-FF is very convenient for such an asynchronous counter design. The counting frequency (speed) will be limited by the number of FFs due to the linear growth of the clock-to-output delay. To speed up the counting process, we can use the mixed-mode counter. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

9 7. Storage Components 7-9 Clear syn. Counter (a) Graphic symbol T T T T Clear FF FF FF FF (b) Logic schematic t t t t t 4 t 5 t 6 t 7 (c) Timing diagram Figure 8: synchronous up-counter [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

10 7. Storage Components 7- nable syn. Counter syn. Counter Clear Clear (a) Synchronous counter with 4 bit asynchronous slices nable Syn. Counter Syn. Counter Clear Clear (b) synchronous counter with 4 bit synchronous slices Figure 9: Mixed-mode up-counter [Gajski]. Register Files register file has n registers of m FFs each. The registers are arranged as a -dimensional array of register-file cells (s). n addition, it has read/write decoders and output driving logic. Writing is controlled by the Write-nable (W) signal. t any time, we can write into only one register (row), unless it has multiple write ports. Reading is controlled by the Read-nable (R) signal. t any time, we can read from only one register, unless it has multiple read ports. Reading from and writing into the same register at the same time normally is not allowed. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

11 7. Storage Components 7- The primary advantage of a register file is regularity, which reduces routing (wiring) complexity. Write select m nput Output W W n RF n m n R R Read select m (a) Register file cell O (b) Graphic symbol to 4 read decoder R R W W R W to 4 write decoder O O O O (c) Logic Schematic Figure : Register file with write port and read port [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

12 7. Storage Components 7- Write select m nput Out OutB W W n RF n x m n n R R RB RB (a) Register file cell Read select (port ) Read select (port B) m m B (b) Graphic symbol W W W RB RB R RB R R to 4 read decoder to 4 read decoder to 4 write decoder B B B B (c) Logic Schematic Figure : Register file with write port and read port [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

13 7. Storage Components 7- Random ccess Memories (RMs) RM is organized as an array of n rows with m bits stored in each row. The size of the RM is n m bits it has n address lines, m input data lines, and m output data lines (see Fig. ). The input data lines can be the same with the output data lines, i.e., the data lines can be bidirectional. For a commodity RM, 6» n»,andm =, 4, 8, 6, r. memory cell () can be considered as a clocked latch with an N gate and an output driver (see Fig. (a)). For a static RM (SRM), is constructed by 6 transistors, using cross-coupled inverters to serve as a latch, and implementing the input N gate and the output driver with one transistor each. For a dynamic RM (RM), is constructed by only transistor. The latch is implemented by a capacitor. t needs to be refreshed periodically. t has high density (therefore low cost). The RM also has a Chip-Select () input and a Read/Write Select () input (see Fig. (b)). The RW S input sometimes is denoted as R =W. Both SRM and RM are volatile memories, i.e., their content is lost if the power is shut down. ROM, PROM, PROM, PROM, and flash memories are nonvolatile. The delay time from address input to data output (t t in Fig. 4) is the memory access time. The address/data setup time and hold time are shown in Fig. 4. We can connect several memory chips to get one of longer words (Fig. 5), or connect several memory chips to get one with more words (Fig. 6). cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

14 7. Storage Components 7-4 Memory address Memory content Binary ecimal n n m bits (a) Memory address and content m n n n x m RM n x m RM O m O O /O m /O /O (b) Graphic symbols Figure : Random-access memory (RM) [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

15 7. Storage Components 7-5 Row select nput Output C Write enable (a) Memory cell to 4 address decoder Write enable O O O O (b) Memory schematic Figure : RM organization [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

16 7. Storage Components 7-6 ddress Valid address ata Output enable time Valid data Output disable time ccess time Output hold time t t t t t 4 t 5 (a) Read cycle timing ddress Valid address ata Valid data ddress setup time ata setup time Write pulse width ddress hold time ata hold time t t t t t 4 t 5 (b) Write cycle timing Figure 4: RM timing [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

17 7. Storage Components 7-7 nput bus M M M M O O O O Output bus Figure 5: 6K RM design using 6K 8 RMs [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

18 7. Storage Components 7-8 nput bus 4 to 4 ecoder M O M O M O M O Output bus Figure 6: 64K 8 RM design using 6K 8 RMs [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

19 7. Storage Components 7-9 *Push-own Stacks push-down stack (or simply stack) is a memory component with limited access data can be accessed through only one location (i.e., the top of the stack). When data is to be stored, it is pushed on the stack and stays on top of others. When data is to be fetched, it has to be in the top position before it can be popped out of the stack. stack can be implemented by shift registers, with an up-down counter to detect full/ stack as shown in Fig. 8. t can also be implemented by a RM less expensive for a large stack, but need two pointers (implemented by counters) as shown in Fig Top Top 4 Top Top (a) Stack content before 45 is pushed down (b) Stack content after 45 is pushed down (c) Stack content after 45 is popped up Figure 7: Push-down stack operations [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

20 7. Storage Components 7- Push/Pop (a) Operation table Shift register controls Counter Counter controls outputs nable Operations No change Push Push/Pop nable S S Pop (b) Control table mpty (c) Output table Full N "" S S L SRwPL R N m "" OUT S S L SRwPL R Push/Pop OUT m nable Control logic Set Up own Counter mpty Output logic Full (d) Stack schematic Figure 8: 4-word stack implemented by shift registers [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

21 7. Storage Components 7- data data Top Top Push/Pop Memory Counter control controls controls nable Operations Push/Pop nable S No change Push Pop (a) Symbolic design (a) Operation table (b) Control table Top Set Top Push/Pop S nable K RM Control logic /O bus Output logic mpty Full (c) Stack schematic Figure 9: 4-word stack implemented by RM [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

22 7. Storage Components 7- *First-in-First-out ueue first-in-first-out (FFO) queue (or simply queue or FFO) is a memory component with limited access data can be written through only the head (front) of the queue and read (and removed) through only the tail (back) of the queue. queue can be implemented by shift registers, with an up-down counter to detect full/ queue as shown in Fig.. t can also be implemented by a RM less expensive for a large queue, but need two pointers (implemented by counters) as shown in Fig.. 45 Top Top 45 Top Top 4 (a) ueue content before 45 is stored (b) ueue content after 45 is stored (c) ueue content after is read Figure : FFO queue operations [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

23 7. Storage Components 7- Read/Write nable Operations Read/Write nable S S No change Read Write (a) Operation table (b) Control table N S S L SRwPL R N m Read/ Write nable Control logic "" S S Set L SRwPL R Up own Counter S S S S OUT OUT m Full Output logic mpty (c) ueue schematic Figure : 4-word queue implemented by shift registers [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

24 7. Storage Components 7-4 data data... data Front Back Read/Write nable Operations No change Read Write Read/Write nable S (Front) (Back) (a) Symbolic design (b) Operation table (c) Control table Front Back Comparator < = > S nable Read/Write K RM /O bus mpty Full (d) Schematic Figure : 4-word queue implemented by RM [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

25 7. Storage Components 7-5 Simple atapaths atapaths are used in all standard CPU and SC implementations to perform complex numerical computation or data manipulations; a datapath consists of temporary storage in addition to arithmetic, logic, and shift units. xample ssume we want to perform the summation of numbers: sum = P i= x i: We can use the datapath as shown in Fig. to implement the following algorithm: sum=; for(i=; i<=; i++) sum=sum+x[i]; nput O 8 S M S S LU B 4 S S L ccumulator R (a) atapath schematic nput select LU controls Shift values ccumulator controls Out enable (b) Control word Figure : Simple datapath with one accumulator [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

26 7. Storage Components 7-6 nport 9 S M S S LU Operations W W R R Bus 8 x m Register File Bus B RB RB complement N OR OR decrement add subtract inrement (b) Table of LU operations M S S S S S L LU Shifter B "" "" R S S S Shift Operations pass pass not used not used shift left rotate left shift right rotate right Result Bus (c) Table of shifter operations Outport (a) atapath schematic Write address Read address Read address B LU operation Shifter operation O (d) Control word Figure 4: atapath with -port register file [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

27 7. Storage Components 7-7. ata := nport. Ocount :=. Mask := while ata := repeat 4. Temp := ata N Mask 5. Ocount := Ocount + Temp 6. ata := ata >> end while 7. Outport := Ocount (a) Basic algorithm for one s count R: ata R: Mask R: Ocount R4: Temp (b) Register assignment Control Words Write address Read address Read address B LU operation Shifter operation O R R add pass R4 R R R R R R R4 N add add pass pass shift right } Repeated while ata = R increment pass 7 none R add pass (c) Control words for one s counter Figure 5: One s-count algorithm [Gajski]. cfl Cheng-Wen Wu, Lab for Reliable Computing (LaRC),, NTHU 5

UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents Memory: Introduction, Random-Access memory, Memory decoding, ROM, Programmable Logic Array, Programmable Array Logic, Sequential programmable