Radiation hard design in CMOS image sensors. Bart Dierickx, Caeleste CPIX Workshop sept 2014, Bonn

Transcription

1 Radiation hard design in CMOS image sensors Bart Dierickx, Caeleste CPIX Workshop sept 2014, Bonn

2 Outline Introduction Total dose Total ionizon dose TID Displacement damage DD Single events SEU single event upset SEL single event latch-up Take home message 16 September 2014 radhard design in CMOS image sensors 2

3 Introduction TID total ionizing dose DD displacement damage SEU single event [upset...] SEL single event latch-up Take home message Introduction About us Background in Radhard CMOS design 16 September 2014 radhard design in CMOS image sensors 3

4 About us Founded 2006 Mechelen, Belgium 17p Mission and business model Supplier of Custom designed Beyond State of the Art Image sensors space X-ray scientific TOF specialties 16 September 2014 radhard design in CMOS image sensors 4

5 Caeleste radhard background Where we come from Historical contribution to radhard and cryo design for space (ISOPHOT..., OISL, STAR250, HAS...) Background in design for particle physics and X-ray integrating and photon counting detectors Close relationships with foundry technologists Expertise in circuit & device physics & technology Present Routine radhard design (TID, TnID, SE, SEL) Proton & SE hard pixels ROICs and image sensors 16 September 2014 radhard design in CMOS image sensors 5

6 Heritage OISL 2000 first >10Mrad QX 2010 Analog domain 2- energy color X- ray photon counting ISOPHOT FIR ROIC 1989 SEU hard wo TR 1989 XYW event detector 1992 RD-19 SOI-CMOS STAR250/ September 2014 radhard design in CMOS image sensors 6

7 Disclaimer This paper focuses on design countermeasures, while understanding the damage mechanism itself This is not a design course. Details of actual designs are not shown Technology countermeasures, temperature effects, annealing not treated No guarantee on effectiveness of techniques, nor of IP freedom 16 September 2014 radhard design in CMOS image sensors 7

8 Introduction TID total ionizing dose DD displacement damage SEU single event [upset...] SEL single event latch-up Take home message TID total ionizing dose also referred to as IEL ionizing energy loss 16 September 2014 radhard design in CMOS image sensors 8

9 TID Radiation: Primarily X, γ, but essentially all particles Dominant effect : Creation of positive space charge in the SiO2 (SiN) dielectric layers Also: increase of interface states at Si-SiO2 interface Effect on CMOS circuits: Moderate shift of Vth, μ degradation and 1/f noise increase Parasitic S-D leakage via STI/field in nmosfets resulting in large dissipation and malfunction 16 September 2014 radhard design in CMOS image sensors 9

10 TID Effect on CMOS pixels: Moderate offset shift and 1/f noise increase Lateral shunting between pixels Lower gain and increased PRNU Increased average I dark and DNSU Most publications are describing this last effect 16 September 2014 radhard design in CMOS image sensors 10

11 Design countermeasures Buried diodes as the general way to reduce dark current Avoiding the parasitic source-drain leakage in nmosfets Several case-by-case other measures 16 September 2014 radhard design in CMOS image sensors 11

12 TID-hard CMOS Regular transistor Leaks when STI/field inverts Annular transistor: No path over STI/field H-gate transistor: Leakage path over STI/field is blocked by P-implant 16 September 2014 radhard design in CMOS image sensors 12

13 The CES ASIC Fully radhard & cryo 77K UMC018 Digital: DARE library Analog: CaelesteRH >>1Mrad, not tested yet ESA consortium Caeleste+Easics+Selex September 2014 radhard design in CMOS image sensors 13

14 4 SAR ADCs, detail 16 September 2014 radhard design in CMOS image sensors 14

15 Digital logic, detail 16 September 2014 radhard design in CMOS image sensors 15

16 Caeleste RH library CaelesteRH as compared to SotA Available in 3 technologies, porting is standardized Full analog & mixed mode Very high TID & TnID hardness Very high SEL hardness Very high SEU hardness wo TR <20% increased Cin and power <50% area increase Normal Caeleste mixed mode Caeleste RH 16 September 2014 radhard design in CMOS image sensors 16

17 Idark [e-/s] TID Gamma Radhard pixels LAP2010 device Tower TSL Gamma TID TID of gamma 60 Co Compared to published SotA TID [kgy] innocent1 2009innocent2 2009innocent (HAS) 2000bogaert/dierickx 2002dierickx (STAR250) LAP default LAP DS LAP DX 10 LAP XS September 2014 radhard design in CMOS image sensors 17

18 e-/h+/α range or photon absorption [µm] factor increase Idark [] TID Gamma Electrons 100 LAP2010 device Tower TSL devices; many pixels per device 1E E+07 1E+06 1E+05 1E+04 1E+03 1E+02 1E E+00 1E-01 Silicon electrons protons e- PPD photons [krad 70 Si] 80 alpha 1E-02 1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09 1E+10 initial energy [ev] TID of 300keV electrons 1.2/1.3 MeV gamma 60 Co Effect on Buried PPD Surface FD 16 September 2014 radhard design in CMOS image sensors 18 e- FD γ PPD γ FD

19 DD Introduction TID total ionizing dose DD displacement damage SEU single event [upset...] SEL single event latch-up Take home message displacement damage also referred to as NIEL non-ionizing energy loss 16 September 2014 radhard design in CMOS image sensors 19

20 DD Radiation: HE particles: protons and heavier Dominant effect : Non-elastic displacement of Si atoms Often creating an initial vacancy+interstitial Effect on CMOS pixels: Point-wise heavily leaking diodes, hot pixels Often blinking RTS dark current pixels 16 September 2014 radhard design in CMOS image sensors 20

21 Photodiode redundancy? Proton/Neutron/other_particle displacement damage in the photodiode creates hot or RTS pixel SE creates flash No way to remove or calibrate this? Suppose we split the pixel in parts. The defect will reside in only one Redundancy? Readout all, remove the defect part s signal and average. Take a weighted maximum voltage by winner take all circuit or sourcefollower 16 September 2014 confidential 21

22 RESET Photodiode redundancy RESET RESET SELECT SELECT PPD/2 PPD/2 FD FD/2 PPD TG TG FD/2 Column PPD/2 Column US patent US

23 SEU Introduction TID total ionizing dose DD displacement damage SEU single event [upset...] SEL single event latch-up Take home message single event [upset] Also SEE, SEFI, SET, SEGR, SEB... () SEL is separately treated 16 September 2014 radhard design in CMOS image sensors 23

24 SEU Radiation Sometimes X, γ, e-, but rather much heavier particles Dominant effect : Creation of instantanous + or charge packet sufficient to toggle a latch Effect on CMOS and CMOS pixels: register or memory loosing information flash seen by the photodiode 16 September 2014 radhard design in CMOS image sensors 24

25 SEU The loss of bits in SRAM cells or Flip-flops electrons September 2014 radhard design in CMOS image sensors 25

26 SEU Mechanism Particle deposited charge packet charges one node of a latch to the oppisite logic value 16 September 2014 radhard design in CMOS image sensors 26

27 Flipping the 0 VDD 3.3V VSS 3.3V 0V

28 Flipping the ns VDD 3.3V 2V VSS V Hole drift/diffusion Electrons drift/diffusion + + +

29 SEU countermeasures Shield against particles Make vulnerable volume small Make vulnerable node capacitance large Triple (and other froms of) redundancy Detectability, read-back, re-upload 16 September 2014 radhard design in CMOS image sensors 29

30 SEL Introduction TID total ionizing dose DD displacement damage SEU single event [upset...] SEL single event latch-up Take home message single event latch-up SEL

31 SEL Radiation Protons and rather even heavier particles Dominant effect : Creation of instantanous + or charge packet sufficient to initiate a PNPN latch-up Effect on CMOS: Circuit collapsing and potential destruction due to excessive supply current 16 September 2014 radhard design in CMOS image sensors 31

32 Bulk CMOS has an annoying thyristor VDD VSS PNP NPN

33 Bulk CMOS has an annoying thyristor VDD VSS PNP NPN

34 Attention: these two resistors are physically partly the same This external element model is imperfect! Thyristor = 2 * BJT VSS NPN VDD Q PNP Threshold for ignition: Q, C Conditions for sustaining:, R 16 September 2014 radhard design in CMOS image sensors 34

35 Modeling SEL Quantitative compact (=SPICE) model? Much better: a 3D device simulator. What lacks: value for series resistances Series resistances in E, B, C. Can estimate it from techology data. Pay attention that resistance applies to majority carriers. Base resistance is thus over/underestimated and partly uncorrelated Emitter and Base resistances partly overlap: Emitter current increases IR drop of Base. What lacks: models of the parasitic BJTs : must eventually measure that. Start with default value ( ) for qualitative estimate. 16 September 2014 radhard design in CMOS image sensors 35

36 Design countermeasures Avoid ignition minimize sensitive volume maximize C/Q: increase node capacitances Avoid sustaining Maximally reduce the series resistance in the thyristor Between the nwell and pwell: guard rings metallically tied to VDD/VSS Avoid proliferation nwells (actually the well not being the substrate) should be fragmented. So that the latchup remains confined: when one section latches, the general supply voltage does not collapse. 16 September 2014 radhard design in CMOS image sensors 36

37 Design style Classic CMOS design style Metal guardring around wells Rails in the middle VDD=nWELL VDD=nWELL VSS=substrate VDD=nWELL VSS=substrate VSS=substrate 16 September 2014 radhard design in CMOS image sensors 37

38 VSS=substrate VDD=nWELL VDD=nWELL VSS=substrate Mirrored rails VDD=nWELL VSS=substrate VSS=substrate VDD=nWELL 16 September 2014 radhard design in CMOS image sensors 38

39 Technology measures Avoid the thyristor SOI, FinFET Reduce the bipolar feedback Poor BJTs Trenches Low sheet resistances Epi wafers (p- on p++ or n- on n++): reduces 1 Base resistor Increased recombination reduces minority current and increases I dark Reduce the pick-up Small charge collecting volume in the Bases 16 September 2014 radhard design in CMOS image sensors 39

40 Triple well... The number of possible thryristors increases 16 September 2014 radhard design in CMOS image sensors 40

41 Good to know nmos-only or pmos-only circuit parts cannot latchup. A standalone BJT does not latchup 16 September 2014 radhard design in CMOS image sensors 41

42 SEL and vulnerable nodes How much charge is deposited on a vulnerable node 16 September 2014 radhard design in CMOS image sensors 42

43 Vulnerable 0 VDD VSS

44 Vulnerable 0 +10ps VDD VSS + -

45 Vulnerable ns VDD VSS recombination

46 electrons Net node charge as function of time the nwell case Substrate electrons diffuse into depletion layer then drift into nwell Electrons diffuse to nwell VDD tie Holes in nwell diffuse into depletion layer then drift into substrate Event Holes drift out of depletion layer to substrate Electrons drift into nwell ~10ps ~1ns time

47 How to estimate Q? LET linear energy transfer Heavy ions are commonly described by amount of energy lost per unit track length = Linear Energy Transfer Linear Energy Transfer Energy loss per unit path length de/dx= MeV/cm Divide by material density = MeV.cm 2 /mg LET of 100 MeV.cm 2 /mg corresponds to charge deposition of 1pC/μm = 6E6 e-/h+ How does LET spectrum relate to the real space environment? A measure for the heaviest ions/events that can be expected Says nothing about number of particles or probability 16 September 2014 radhard design in CMOS image sensors 47

48 [e-h+/µm] e-h+ pairs per µm 100 MeV.cm 2 /mg = 1pC/µm = 6Me-h+/µm This is a linear function, thus 50 MeV.cm 2 /mg is still 3 million charges/µm. For reference /µm α: 4E6 eh, H+: eh, β (and γ): <5000 e-h+ 1,E+06 1,E+05 1,E+04 deposited e-h+/µm in Silicon e: e-/µm h+: e-/µm alfa: e-/µm More energy: less charges! 1,E+03 1,E+02 1,E+04 1,E+05 1,E+06 1,E+07 1,E+08 1,E+09 1,E+10 actual energy [ev] 16 September 2014 radhard design in CMOS image sensors 48

49 Voltage drop assuming instantanous charge deposition Minimal junction size and capacitance 1fF & 1µm: 6000 e- = 1V Electrons (hence gamma) cannot create V forward Protons can (marginally) ignite LU Proton SEL hard junction? 5fF & 1µm: e- = 1V. Yet, shallow angle? 16 September 2014 radhard design in CMOS image sensors 49

50 electrons Net node charge as function of time Maximum effect alfa LET 100 MeV.cm 2 /mg Maximum effect proton Worst case threshold for SEL ~10ps Maximum effect electron / gamma <1GeV ~1ns time

51 Introduction TID total ionizing dose DD displacement damage SEU single event [upset...] SEL single event latch-up Take home message Take home message conclusions 16 September 2014 radhard design in CMOS image sensors 51

52 Take home CMOS imagers can be made hard against TID, SEL, SEU etc by design TID: avoid field leakage SEL: reduce bipolar feedback SEU: vulnerable volume & circuit redundancy Photodiode hardening for SE and displacement damage remains a question Photodiode redundancy? 16 September 2014 radhard design in CMOS image sensors 52

53 Thank you 16 September 2014 radhard design in CMOS image sensors 53