OTP & MTP/FRP Non-Volatile Memory IP for Standard Logic CMOS

Transcription

1 OTP & MTP/FRP Non-Volatile Memory IP for Standard Logic CMOS NSCore, Inc.

2 Outlines 1. Corporate Overview 2. Program, Read & Erase Mechanism 3. OTP IP Lineups 4. New MTP Technologies

3 Corporate Overview

4 Company Profile Head Quarter: Fukuoka, Japan Sales Office: Kanagawa, Japan California, U.S.A. Texas, U.S.A. Paris, France Herzliya, Israel Hsinchu, Taiwan Seoul, Korea Company Name Head Quarter Foundation Management Team Advisory Financing NSCore, Inc. Fukuoka, Japan 2004 CEO: T. Horiuchi CTO: K. Noda Prof. Chenming Hu (UC Berkeley) USD6.8M from VC USD5.2M from Gov t

5 Embedded Logic NVM Technology Applications Program Code Security Code Analog Trimming SRAM Repair Gamma Correction Non-Volatile Memory IP on CMOS Process Platforms Benefits to LSI Design: Reduced Cost Reliability Improved Security Level

6 Track Record of License Over 1.5 billion units of licensed products have been shipped. Gamma table for LCD display Power IC for mobile phone Sensor IC for mobile phone Product TAG Firmware storage of WiFi chip NSCore inside major smart phone

7 NSCore Technology Position Memory Capacity 100Kbit-10Mbit 100bit-10Kbit OTP MTP FRP (Flash Replacement Programmable) NSCore OTP PermSRAM Kilopass Sidense ememory NSCore MTP/FRP TwinBit TM Synopsys 1 time 1K-10K times OTP MTP Write/Erase Cycle

8 Program, Read and Erase Mechanism

9 Programming Mechanism When nmosfet turns ON, hot-electrons are generated and trapped in sidewall spacer. SiO 2 5-7V Si 3 N 4 Hot electron Common sidewall spacer structure Source Ec Electrons Electrons Drain 5-7V LDD implant is masked to accelerate impact ionization. Impact Ionization

10 In Read Operation Source and Drain are reversed from Program Operation V Trapped electron Drain 0.5-1V Electrons Source Ec Conduction band without electron trapping Trapped electron bends the conduction band to form a barrier. Channel current is reduced.

11 Erase Mechanism for TwinBit/PolarBit (MTP) When Gate is negatively biased, hot-holes are injected into the spacer and recombine with the trapped electrons V Hot-Hole Injection and Recombination Source Drain 0V 5-7V Band-to-Band tunneling current generates hotcarriers.

12 Similarity with SONOS Memory Our OTP Cell Tr. SONOS NVM Cell Tr. Gate Si 3 N 4 Gate Source - Drain SiO 2 Source - Drain Program mechanism in Our OTP is similar to SONOS memory, which has strong track record as embedded Flash memories. Both memories uses electron trapping in Si 3 N 4 layer. Our OTP does not need any extra process, while SONOS requires special gate structure.

13 NSCore utilizes Charge-Trap in Si 3 N 4 Film MOSFETs in most of the foundry processes have Sidewall Si 3 N 4 /SiO 2 structure even down to 28nm node, including SOI processes. - ~2 ev TSMC 40nm node TSMC 28nm node p-si SiO 2 Si 3 N 4

14 Excellent Retention Characteristics The cell current was drastically reduced and has been stable even after baking for 100 hours at 200ºC, which is equivalent to over 30 years at 125ºC. 0.18µm process ID[A] program Baking

15 Program Operation Program current flows in one transistor in a cell and generate hot-carriers. WL0 OTP bit cell High On Driver & Pre-Amplifier L H Off Drain Current Hot-Carrier Effect Gate Voltage WL1 Low Bit Ex. High Bit

16 Read Operation Both bit-lines are pre-charged and current flows through selected cell transistors. Sense amplifier senses current difference and latches. Hot Carrier Trapped Tr. Driver & Pre-Amplifier H H L Amplifying Latch WL0 High Ion0 Ion1 Ion0 << Ion1 WL1 Low Bit Low Bit

17 Erase Operation in TwinBit TM Driver & Pre-Amplifier L L SWL0 Negative SWL1 Negative Bit Ex. High Bit

18 OTP IP Lineup

19 Availability in Foundry Processes TSMC 0.18µm TSMC 0.13µm TSMC 0.11µm TSMC 90nm TSMC 65nm IBM 0.18µm Toshiba 65nm TowerJazz 0.18µm UMC 0.11µmAE UMC 0.11µmE SMIC 0.13µm GF 0.13µm Silterra 0.18µm Silterra 0.13µm Silterra 0.11µm LFoundry 0.15µm LFoundry 0.11µm IP9000 Full Qual., Volume Production IP9000 Full Qual., Volume Production Silicon Verified Silicon Verified IP9000 Full Qual., Volume Production Ready-for-IBM, Volume Production Full Qualification, Volume Production Full Qualification, Volume Production Silicon Verified Silicon Verified Silicon Verified Silicon Verified In Silicon Verification In Silicon Verification In Silicon Verification Silicon Verified In Silicon Verification

20 New MTP Technologies

21 TwinBit for Automotive in TSMC0.18um (1.8V+5.0V)

22 Cell Current Distribution after 10K Cycle and Baking

23 Retention Lifetime Estimation after 10K Cycles True/Bar Ratio[%] Program Time: 1 [ms] Sigma Bake time at 200c [h] CEA Split L [µm] W [µm] σ % 13.64% 22.73% 45.83% 3.0σ % 12.00% 20.00% 42.31% 2.0σ % 8.70% 14.81% 37.04% 1.0σ % 4.76% 11.54% 29.63% 5 Asymmetric Before Baking 0.0σ % 4.35% 8.00% 23.08% 0.0σ % 4.35% 8.00% 23.08% -1.0σ % 4.00% 4.35% 18.52% -2.0σ % 3.85% 3.85% 13.79% -3.0σ % 3.57% 3.57% 10.34% -3.6σ % 3.45% 3.45% 7.14% Worst Bit Lifetime of the worst bit = 8.86 years at 200 C

24 Retention Lifetime Estimation after 10K Cycles Assuming Ea = 1.0 ev, Cell Failure Rate = 1ppm. Temp.( C) Lifetime (hours) Lifetime (years) , , , ,905, Assuming Ea = 1.0 ev, Cell Failure Rate = 1ppb. Temp.( C) Lifetime (hours) Lifetime (years) 200 8, , , ,

25 TwinBit in Fujitsu55nmDDC (0.9V+3.3V)

26 Endurance & Retention for 55nm (1) 32Kbit: 10K cycle pre-bake 32Kbit: 10K cycle post-bake Clear Gaussian distribution No tailing behavior Operational window for date retention

27 Endurance & Retention for 55nm (2) 32Kbit: 10K cycle pre-bake 32Kbit: 10K cycle post-bake Over 5-sigma window remaining even after baking.

28 TwinBit TM Cell Structure Cross-point Cell Structure 0.25µm Bit Cell (0.1µm 2 ) in 55nm node

29 MTP Comparison Table Vendor Type Bit Cell Poly HV OX Extra Mask Max Capacity Temp Range Prog./Erc. Time Read Current Access Time Endurance Data Retention Company-A Floating Gate 1.5 Tr./Cell 3 Layers ~12V Core/IO/HV +13 2M Byte -40 to +125 C 10us/4ms 60uA/MHz <25ns 100K cycles 10Y@ C Company-B Floating Gate 3 Tr. + /Cell 1 Layer ~15V Core/IO 0 512Kb -40 to +125 C 50us/220ms 100uA/MHz <40ns 1K cycles 10Y@ C NSCore Charge-Trap 2 Tr./Cell 1 Layer 5-6V Core/IO 0 2M Byte -40 to +150 C 10us/100ms 30uA/MHz <20ns 100K cycles 100Y@175 C

30 Thank you!