Garnet2.0: A Detailed On-Chip Network Model Inside a Full-System Simulator
|
|
- Nora Pearson
- 6 years ago
- Views:
Transcription
1 Garnet2.0: A Detailed On-Chip Network Model Inside a Fll-System Simlator Tshar Krishna gem5 workshop ARM Research Smmit September 11, 2017 Assistant Professor School of ECE and CS Georgia Institte of Technology tshar@ece.gatech.ed
2 Overview What are Networks-On-Chip (NoCs)? Why model NoCs accrately Garnet2.0 Configration Topology Roting Flow-Control Roter Microarchitectre System Integration Network Interface Network Parameters Rnning Garnet with Rby Rby Garnet Standalone Otpt Stats Extensions and FAQs 2
3 Overview What are Networks-On-Chip (NoCs)? Why model NoCs accrately Garnet2.0 Configration Topology Roting Flow-Control Roter Microarchitectre System Integration Network Interface Network Parameters Rnning Garnet with Rby Rby Garnet Standalone Otpt Stats Extensions and FAQs 3
4 Networks-on-Chip 4
5 Introdction to NoCs Core + L1$ Core + L1$ Core + L1$ Core + L1$ A Core + L1$ Core + L1$ LD (A) R1 Req Rsp On-Chip Network Fwd L2$ L2$ L2$ L2$ L2$ L2$ 5
6 Modern NoCs Core L1 D$ L2$ L1 I$ Network Interface L3$/Directory Roter Network Interface converts cache messages (ctrl or data) into packets. Packets get broken down into one or more flits depending on NoC link width Tile 6
7 Network Architectre Topology Roting Flow Control Roter Microarchitectre 7
8 Topology: How to connect nodes with links ~Road Network 8
9 Roting: Which path shold a message take ~Series of road segments from sorce to destination 9
10 Flow Control: When does a message stop/proceed ~Traffic Signals / Stop signs at end of each road segment 10
11 Roter Microarchitectre: How to bild the roters ~Design of traffic intersection (nmber of lanes, algorithm for trning red/green) 11
12 Overview What are Networks-On-Chip (NoCs)? Why model NoCs accrately Garnet2.0 Configration Topology Roting Flow-Control Roter Microarchitectre System Integration Network Interface Network Parameters Rnning Garnet with Rby Rby Garnet Standalone Otpt Stats Extensions and FAQs 12
13 Why model NoCs accrately? Case Stdy I: Directory vs. Broadcast Protocols Case Stdy II: Private vs. Shared L2 1.6 Fll-state Directory HyperTransport Token Coherence 1.2 Shared L2 Private L2 Normalized Rntime Baseline NoC (Intel SCC) FANOUT + FANIN NoC (Krishna et al, MICRO 2011) SMART NoC (Krishna et al, HPCA 2013) 64-core CMP with different NoC Microarchitectres Normalized Rntime Baseline NoC (Intel SCC) SMART NoC (Krishna et al, HPCA 2013) 64-core CMP with different NoC Microarchitectres Different NoC Microarchitectres may lead to different microarchitectral decisions and new design optimization opportnities 64-core CMP rnning PARSEC workloads in fll-system gem5. Average rntime plotted. 13
14 Overview What are Networks-On-Chip (NoCs)? Why model NoCs accrately Garnet2.0 Configration Topology Roting Flow-Control Roter Microarchitectre System Integration Network Interface Network Parameters Rnning Garnet with Rby Rby Garnet Standalone Otpt Stats Extensions and FAQs 14
15 Garnet2.0 Detailed NoC Model Crrently part of Rby Memory System in gem5 Original version (5-stage pipeline) released in 2009 Developed by Niket Agarwal (crrently at Google) and myself New version (1-stage pipeline, more configrability) released in 2016 Resorces Sorce: src/mem/rby/network/garnet2.0 gem5 wiki page: Dev patches + practice labs: 15
16 Topology Each topology is a python file in configs/topologies/ Core + L1$ L2$ DMA Dir ExtLink (bi-directional) R R IntLink (ni-directional) Core + L1$ R R Dir Core + L1$ L2$ L2$ R R Step 1: Instantiate roters and connect to controllers via Ext Links Step 2: Instantiate Int Links and connect to roters in desired topology This is an example of MeshDirCorners_XY.py L2$ L2$ L2$ Core + L1$ Dir Core + L1$ Dir Core + L1$ 16
17 Topology Configrable Parameters Roter roter_latency (in cycles) Can be set per roter Defined in src/mem/rby/network/basicroter.py Link link_latency (in cycles) Can be set per link Defined in src/mem/rby/network/basiclink.py weight (i.e., link weight) To bias roting algorithm [later slides] src_otport (string) and dst_inport (string) Port direction (e.g., East ) Helps with readability of Config file + Adaptive roting algorithms bw_mltiplier (vale) Used by Rby s simple network model, NOT by Garnet Link bandwidth is set inside Garnet via the ni_flit_size parameter [later slides] 17
18 Defalt Topologies Spported Pt2Pt Crossbar Mesh Mesh_XY Mesh_westfirst MeshDirCorners_XY Clster 18
19 Roting Roting table Atomatically poplated based on topology All messages se shortest path In case of mltiple options, the path with the smaller weight is chosen Deterministic Roting Cstom Users can leverage otport/inport direction names associated with each port to implement cstom algorithms (say adaptive) 19
20 Deadlock Avoidance Deadlock: A condition in which a set of agents wait indefinitely trying to acqire a set of resorces D 0 1 x A C 3 w 2 v B Packet A holds bffer (in 1) and wants bffer v (in 2) Packet B holds bffer v (in 2) and wants bffer w (in 3) Packet C holds bffer w (in 3) and wants bffer x (in 0) Packet D holds bffer x (in 0) and wants bffer (in 1) 20
21 Deadlock-free Roting Algorithms Deadlocks may occr if the trns taken form a cycle Removing some trns can make the roting algorithm deadlock free XY Model West-First Trn Model 21
22 Deadlock-free Roting Algorithms Assign weights to bias which links sed first (to ensre no cyclic dependence) XY Roting: Always go X first, then Y DC DA DB SA SB SC Mesh_XY 22
23 Deadlock-free Roting Algorithms Assign weights to bias which links sed first (to ensre no cyclic dependence) West-first Roting: Go W first, then N/S DC DA DB SA SB SC Mesh_westfirst 23
24 Flow Control Virtal Channels Coherence Protocol reqires certain nmber of virtal networks / message classes to avoid protocol deadlocks This is the minimm nmber of VCs reqired Within each vnet, there can be more than one VC for boosting network performance Credits In Garnet, only one packet can se a VC inside a roter at a time VCs in vnets carrying control messages are 1-flit deep VCs in vnets carrying data (cacheline) messages are 4-5 flit deep Each VC conveys its bffer availability by sending credits to its pstream roter 24
25 Conventional VC Roter Microarch FLIT V N 0 V N 1 Rote Compte VC 0 VC 1 VC n Inpt Bffers VC 1 VC 2 VC Allocator SW Allocator BW: Bffer Write RC: Rote Compte VA: VC Allocation Inpt VCs arbitrate for otpt VCs (Inpt VCs at next roter) SA: Switch Allocation Inpt ports arbitrate for otpt ports BR: Bffer Read VC n Inpt Bffers Crossbar Switch ST: Switch Traversal LT: Link Traversal BW RC VA SA BR ST LT 25
26 Single-Cycle Roter Implementation Roter.ccàwakep() Network Link.cc InptUnit.cc àwakep() SwitchAllocator.cc àwakep() * Arbitrate inports has_free_vc() OtptUnit.cc àwakep() Credit Link.cc VN0 VC 0 VC 1 VN1 VC 2 VC 3 VirtalChannel.cc * Bffer Write * Rote Compte 4 * Arbitrate otports * VC Allocate * send credit (schedle creditlink wakep next cycle) * Bffer Read (send flit to switch) select_free_vc() OtVCState.cc * Rcv Credit * Update State CreditLink.cc For mlti-cycle roter, add delay in flit before it can do SA CrossbarSwitch.ccàwakep() * Switch Traversal: Psh winner flits on link qee * Schedle otpt link wakep for next cycle NetworkLink.cc 26
27 Overview What are Networks-On-Chip (NoCs)? Why model NoCs accrately Garnet2.0 Configration Topology Roting Flow-Control Roter Microarchitectre System Integration Network Interface Network Parameters Rnning Garnet with Rby Rby Garnet Standalone Otpt Stats Extensions and FAQs 27
28 System Organization Rby Memory System GarnetNetwork.cc Coherence Protocol Network Interface Network Link Interface is MessageBffers from Rby Roter Roter Stats Credit Link 28
29 Network Interface Msg_size decides nmber of flits Can add additional info in flit Core + L1$ Dir NI Core + L1$ <VN, msg> Flitisize VC Select credit L2$ DMA NI NI NI R R NI R R NI L2$ Cache Controller VN0 VN1 VC 0 VC 1 VC 2 VC 3 Ingress To/From Roter L2$ Core + L1$ NI NI NI Dir NI Core + L1$ NI L2$ Egress NetworkInterface.cc àwakep() 29
30 Garnet Configrable Parameters ni_flit_size Defalt = 16B (128b) à 1-flit ctrl, 5-flit data This sets the bandwidth of each physical link vcs_per_vnet Total VCs in each inport = nm_vnets * vcs_per_vnet bffers_per_data_vc Defalt = 4 bffers_per_ctrl_vc Defalt = 1 roting_algorithm Weight-based table or cstom Defined in: src/mem/rby/network/garnet2.0/garnetnetwork.py 30
31 Command Line Parameters src/mem/rby/network/ BasicRoter.py BasicLink.py Network.py garnet2.0/garnetnetwork.py Definitions and Defalt Vales rby/rby.py configs/ common/options.py network/network.py example/garnet_synth_test.py - Overrides defalt vales in Rby - All parameters in in these.py files can be specified from command line 31
32 Rnning Garnet with Rby Bild Rby Coherence Protocol scons bild/x86_moesi_hammer/gem5.opt PROTOCOL=MOESI_hammer Protocol determines nmber of message classes/virtal networks reqired Invoke garnet2.0 from command line with appropriate network parameters./bild/x86_moesi_hammer/gem5.opt configs/example/fs.py --network=garnet2.0 --topology=mesh_xy... 32
33 Rnning Garnet Standalone Bild the Garnet_standalone protocol scons bild/null/gem5.debg PROTOCOL=Garnet_Standalone Dmmy protocol jst for traffic injection via Garnet Synthetic Traffic tester (next slide) 3 Virtal Networks: vnet 0 and vnet 1 inject ctrl (1-flit) packets, vnet 2 injects data (5-flit) packets Rn ser-specified synthetic traffic./bild/null/gem5.debg configs/example/garnet_synth_traffic.py --network=garnet2.0 --topology=... \ --synthetic=niform_random \ --injectionrate=0.01 \ --nm-packets-max=100 \ 33
34 Garnet Synthetic Traffic Dmmy CPU Model [only works with Garnet_standalone protocol] src/cp/testers/garnet_synthetic_traffic Inject packets for ser-specified traffic pattern at ser-specified injection rate niform_random tornado bit_complement bit_reverse bit_rotation neighbor shffle transpose Ability to inject continosly or fixed nmber of packets, and/or for fixed time, and/or from fixed sorce and/or to fixed destination in one/more vnets Heavy cstomization very sefl for debgging All parameters described here: 34
35 Overview What are Networks-On-Chip (NoCs)? Why model NoCs accrately Garnet2.0 Configration Topology Roting Flow-Control Roter Microarchitectre System Integration Network Interface Network Parameters Rnning Garnet with Rby Rby Garnet Standalone Otpt Stats Extensions and FAQs 35
36 Sample Simlation./bild/NULL/gem5.debg configs/example/garnet_synth_traffic.py --topology=mesh_xy --nm-cps=16 --nm-dirs=16 --mesh-rows=4 m5ot/config.ini 36
37 Otpt Stats m5ot/stats.txt Packet and Flit stats (#injected, #received, qeeing latency at NIC, and network latency) per VN and overall More stats can be added via GarnetNetwork.cc 37
38 Overview What are Networks-On-Chip (NoCs)? Why model NoCs accrately Garnet2.0 Configration Topology Roting Flow-Control Roter Microarchitectre System Integration Network Interface Network Parameters Rnning Garnet with Rby Rby Garnet Standalone Otpt Stats Extensions and FAQs 38
39 Extensions and FAQs System Level Modeling How can I integrate Garnet into my own simlator (or with the gem5 classic memory system)? This shold not be too hard - wold jst reqire some changes to the NI code on how it receives its inpts. If anyone wants to try it, I wold love to give pointers. How do I print a network trace? Yo can add some code to the NI. I have a patch on my website for reference. Can garnet read a network trace? Yo can rn Garnet in a standalone mode, and have it inject traffic from a trace instead of a fixed synthetic pattern. Alternately, try to se cp/testers/traffic_gen Does Garnet report NoC area and power nmbers? The otpt of Garnet can be fed into DSENT (Sn et al, NOCS 2012) which is present in ext/dsent. We will add an atomatic stats.txt parser for it soon. Can we model mltiple clock domains? The entire Rby memory system (inclding Garnet inside it) is one clock domain. To mimic a mlti-clock domain design, yo can schedle wakeps of slow roters intelligently at some mltiples of the clock rather than every cycle. 39
40 Extensions and FAQs Topology How do we model mltiple BW links in Garnet? Inherently, that wold reqire spport in the roter to manage mltiple flit sizes. Instead, yo can add mltiple links between the same nodes if yo want to model higher bandwidth. If they have the same weight, Garnet will randomly send over the two. Can we model a heterogeneos CPU-GPU system? Yes. The crrent AMD GPU model models a clster of CPUs connected to a GPU. Can we model indirect networks sch as Clos? Yes, there can be additional roters that are not connected to any controller and act prely as switches. Can we model large-scale HPC networks? Garnet can model any sized network. Yo can rn 256-node standalone simlations easily. However, beyond that gem5 cannot instantiate more directories (which it ses as destination nodes). I have a patch to rn node synthetic sims on my website. Bt these rn qite slowly. 40
41 Extensions and FAQs Roting How do we model an adaptive roting algorithm? If yo want to se internal NoC metrics (sch as nmber of credits at an otpt port) for making roting decisions, do not se table-based roting. Instead, set the roting-algorithm to cstom, and implement yor own roting fnction inside RotingUnit.cc. See otportcomptexy() for reference. Flow Control Can we implement alternate deadlock avoidance schemes (sch as escape VCs or dateline)? Yo can pdate the vc selection scheme inside SwitchAllocator to control which VCs get allocated. Microarchitectre Can we model variable nmber of VCs in each roter? Crrently the codebase is very tied to the global vcs_per_vnet parameter. If yo want to model variable nmber of VCs, one hack cold be to have everyone instantiate the same nmber of VCs, bt modify the VC select to never allocate certain VCs 41
42 Conclsions Garnet2.0 is an open-sorce research vehicle Use it and contribte to it! Being actively maintained by the following people Georgia Tech: Tshar Krishna AMD Research: Brad Beckmann, Onr Kayiran, Jieming Yin, Matt Porembas If yo have any qestions, on gem5-sers or gem5-dev mailing lists Wold love to have it integrated with the classic memory model Usefl Resorces: Thank yo! 42
Unit Testing with VectorCAST and AUTOSAR
Unit Testing with VectorCAST and AUTOSAR Vector TechDay Software Testing with VectorCAST V1.0 2018-11-15 Agenda Introdction Unit Testing Demo Working with AUTOSAR Generated Code Unit Testing AUTOSAR SWCs
More informationSCORPIO: 36-Core Shared Memory Processor
: 36- Shared Memory Processor Demonstrating Snoopy Coherence on a Mesh Interconnect Chia-Hsin Owen Chen Collaborators: Sunghyun Park, Suvinay Subramanian, Tushar Krishna, Bhavya Daya, Woo Cheol Kwon, Brett
More informationWhat s New in AppSense Management Suite Version 7.0?
What s New in AMS V7.0 What s New in AppSense Management Site Version 7.0? AppSense Management Site Version 7.0 is the latest version of the AppSense prodct range and comprises three prodct components,
More informationIsilon InsightIQ. Version 2.5. User Guide
Isilon InsightIQ Version 2.5 User Gide Pblished March, 2014 Copyright 2010-2014 EMC Corporation. All rights reserved. EMC believes the information in this pblication is accrate as of its pblication date.
More informationLecture 12: SMART NoC
ECE 8823 A / CS 8803 - ICN Interconnection Networks Spring 2017 http://tusharkrishna.ece.gatech.edu/teaching/icn_s17/ Lecture 12: SMART NoC Tushar Krishna Assistant Professor School of Electrical and Computer
More informationLecture 13: System Interface
ECE 8823 A / CS 8803 - ICN Interconnection Networks Spring 2017 http://tusharkrishna.ece.gatech.edu/teaching/icn_s17/ Lecture 13: System Interface Tushar Krishna Assistant Professor School of Electrical
More informationLecture 3: Topology - II
ECE 8823 A / CS 8803 - ICN Interconnection Networks Spring 2017 http://tusharkrishna.ece.gatech.edu/teaching/icn_s17/ Lecture 3: Topology - II Tushar Krishna Assistant Professor School of Electrical and
More informationEMC ViPR. User Guide. Version
EMC ViPR Version 1.1.0 User Gide 302-000-481 01 Copyright 2013-2014 EMC Corporation. All rights reserved. Pblished in USA. Pblished Febrary, 2014 EMC believes the information in this pblication is accrate
More informationIllumina LIMS. Software Guide. For Research Use Only. Not for use in diagnostic procedures. Document # June 2017 ILLUMINA PROPRIETARY
Illmina LIMS Software Gide Jne 2017 ILLUMINA PROPRIETARY This docment and its contents are proprietary to Illmina, Inc. and its affiliates ("Illmina"), and are intended solely for the contractal se of
More informationLecture 3: Flow-Control
High-Performance On-Chip Interconnects for Emerging SoCs http://tusharkrishna.ece.gatech.edu/teaching/nocs_acaces17/ ACACES Summer School 2017 Lecture 3: Flow-Control Tushar Krishna Assistant Professor
More informationLecture 16: On-Chip Networks. Topics: Cache networks, NoC basics
Lecture 16: On-Chip Networks Topics: Cache networks, NoC basics 1 Traditional Networks Huh et al. ICS 05, Beckmann MICRO 04 Example designs for contiguous L2 cache regions 2 Explorations for Optimality
More informationLecture 7: Flow Control - I
ECE 8823 A / CS 8803 - ICN Interconnection Networks Spring 2017 http://tusharkrishna.ece.gatech.edu/teaching/icn_s17/ Lecture 7: Flow Control - I Tushar Krishna Assistant Professor School of Electrical
More informationCS 153 Design of Operating Systems Spring 18
CS 153 Design of Operating Systems Spring 18 Lectre 12: Deadlock Instrctor: Chengy Song Slide contribtions from Nael Ab-Ghazaleh, Harsha Madhyvasta and Zhiyn Qian Deadlock the deadly embrace! Synchronization
More informationMembership Library in DPDK Sameh Gobriel & Charlie Tai - Intel DPDK US Summit - San Jose
Membership Library in DPDK 17.11 Sameh Gobriel & Charlie Tai - Intel DPDK US Smmit - San Jose - 2017 Contribtors Yipeng Wang yipeng1.wang@intel.com Ren Wang ren.wang@intel.com John Mcnamara john.mcnamara@intel.com
More informationCS 153 Design of Operating Systems
CS 153 Design of Operating Systems Spring 18 Lectre 3: OS model and Architectral Spport Instrctor: Chengy Song Slide contribtions from Nael Ab-Ghazaleh, Harsha Madhyvasta and Zhiyn Qian Last time/today
More informationEllucian ODS9.0 Upgrade Migrating from OWB to ODI. Amir Saleem Centennial College May 17, 2017
Ellcian ODS9.0 Upgrade Migrating from OWB to ODI Amir Saleem Centennial College May 17, 2017 Topics OWB Spport Oracle Data Integrator (ODI) ODI Architectre Upgrade paths General Gideline for ODS infrastrctre
More informationCS 153 Design of Operating Systems Spring 18
CS 153 Design of Operating Systems Spring 18 Lectre 2: Historical Perspective Instrctor: Chengy Song Slide contribtions from Nael Ab-Ghazaleh, Harsha Madhyvasta and Zhiyn Qian Last time What is an OS?
More informationAn Introduction to GPU Computing. Aaron Coutino MFCF
An Introdction to GPU Compting Aaron Cotino acotino@waterloo.ca MFCF What is a GPU? A GPU (Graphical Processing Unit) is a special type of processor that was designed to render and maniplate textres. They
More informationEXAMINATIONS 2010 END OF YEAR NWEN 242 COMPUTER ORGANIZATION
EXAINATIONS 2010 END OF YEAR COPUTER ORGANIZATION Time Allowed: 3 Hors (180 mintes) Instrctions: Answer all qestions. ake sre yor answers are clear and to the point. Calclators and paper foreign langage
More informationStandard. 8029HEPTA DataCenter. Because every fraction of a second counts. network synchronization requiring minimum space. hopf Elektronik GmbH
8029HEPTA DataCenter Standard Becase every fraction of a second conts network synchronization reqiring minimm space hopf Elektronik GmbH Nottebohmstraße 41 58511 Lüdenscheid Germany Phone: +49 (0)2351
More informationAgate User s Guide. System Technology and Architecture Research (STAR) Lab Oregon State University, OR
Agate User s Guide System Technology and Architecture Research (STAR) Lab Oregon State University, OR SMART Interconnects Group University of Southern California, CA System Power Optimization and Regulation
More informationSynchronized Progress in Interconnection Networks (SPIN) : A new theory for deadlock freedom
ISCA 2018 Session 8B: Interconnection Networks Synchronized Progress in Interconnection Networks (SPIN) : A new theory for deadlock freedom Aniruddh Ramrakhyani Georgia Tech (aniruddh@gatech.edu) Tushar
More informationEMC AppSync. User Guide. Version REV 01
EMC AppSync Version 1.5.0 User Gide 300-999-948 REV 01 Copyright 2012-2013 EMC Corporation. All rights reserved. Pblished in USA. EMC believes the information in this pblication is accrate as of its pblication
More informationDSCS6020: SQLite and RSQLite
DSCS6020: SQLite and RSQLite SQLite History SQlite is an open sorce embedded database, meaning that it doesn t have a separate server process. Reads and writes to ordinary disk files. The original implementation
More informationVirtuOS: an operating system with kernel virtualization
VirtOS: an operating system with kernel virtalization Rslan Nikolaev, Godmar Back SOSP '13 Proceedings of the Twenty-Forth ACM Symposim on Oper ating Systems Principles 이영석, 신현호, 박재완 Index Motivation Design
More informationChapter 5 Network Layer
Chapter Network Layer Network layer Physical layer: moe bit seqence between two adjacent nodes Data link: reliable transmission between two adjacent nodes Network: gides packets from the sorce to destination,
More informationLecture 2: Topology - I
ECE 8823 A / CS 8803 - ICN Interconnection Networks Spring 2017 http://tusharkrishna.ece.gatech.edu/teaching/icn_s17/ Lecture 2: Topology - I Tushar Krishna Assistant Professor School of Electrical and
More informationLecture 13: Traffic Engineering
Lectre 13: Traffic Engineering CSE 222A: Compter Commnication Networks Alex C. Snoeren Thanks: Mike Freedman, Nick Feamster, and Ming Zhang Lectre 13 Overview Dealing with mltiple paths Mltihoming Entact
More informationThe final datapath. M u x. Add. 4 Add. Shift left 2. PCSrc. RegWrite. MemToR. MemWrite. Read data 1 I [25-21] Instruction. Read. register 1 Read.
The final path PC 4 Add Reg Shift left 2 Add PCSrc Instrction [3-] Instrction I [25-2] I [2-6] I [5 - ] register register 2 register 2 Registers ALU Zero Reslt ALUOp em Data emtor RegDst ALUSrc em I [5
More informationCS 153 Design of Operating Systems Spring 18
CS 153 Design of Operating Systems Spring 18 Lectre 8: Threads Instrctor: Chengy Song Slide contribtions from Nael Ab-Ghazaleh, Harsha Madhyvasta and Zhiyn Qian Processes P1 P2 Recall that Bt OS A process
More informationReview. A single-cycle MIPS processor
Review If three instrctions have opcodes, 7 and 5 are they all of the same type? If we were to add an instrction to IPS of the form OD $t, $t2, $t3, which performs $t = $t2 OD $t3, what wold be its opcode?
More informationCAPL Scripting Quickstart
CAPL Scripting Qickstart CAPL (Commnication Access Programming Langage) For CANalyzer and CANoe V1.01 2015-12-03 Agenda Important information before getting started 3 Visal Seqencer (GUI based programming
More informationEC 513 Computer Architecture
EC 513 Computer Architecture On-chip Networking Prof. Michel A. Kinsy Virtual Channel Router VC 0 Routing Computation Virtual Channel Allocator Switch Allocator Input Ports VC x VC 0 VC x It s a system
More informationCS 153 Design of Operating Systems Spring 18
CS 53 Design of Operating Systems Spring 8 Lectre 2: Virtal Memory Instrctor: Chengy Song Slide contribtions from Nael Ab-Ghazaleh, Harsha Madhyvasta and Zhiyn Qian Recap: cache Well-written programs exhibit
More informationMaking Full Use of Multi-Core ECUs with AUTOSAR Basic Software Distribution
Making Fll Use of Mlti-Core ECUs with AUTOSAR Basic Software Distribtion Webinar V0.1 2018-09-07 Agenda Motivation for Mlti-Core AUTOSAR Standard: SWC-Split MICROSAR Extension: BSW-Split BSW-Split: Technical
More informationThomas Moscibroda Microsoft Research. Onur Mutlu CMU
Thomas Moscibroda Microsoft Research Onur Mutlu CMU CPU+L1 CPU+L1 CPU+L1 CPU+L1 Multi-core Chip Cache -Bank Cache -Bank Cache -Bank Cache -Bank CPU+L1 CPU+L1 CPU+L1 CPU+L1 Accelerator, etc Cache -Bank
More informationThe extra single-cycle adders
lticycle Datapath As an added bons, we can eliminate some of the etra hardware from the single-cycle path. We will restrict orselves to sing each fnctional nit once per cycle, jst like before. Bt since
More informationLow-Power Interconnection Networks
Low-Power Interconnection Networks Li-Shiuan Peh Associate Professor EECS, CSAIL & MTL MIT 1 Moore s Law: Double the number of transistors on chip every 2 years 1970: Clock speed: 108kHz No. transistors:
More informationLecture 22: Router Design
Lecture 22: Router Design Papers: Power-Driven Design of Router Microarchitectures in On-Chip Networks, MICRO 03, Princeton A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip
More informationCS 153 Design of Operating Systems Spring 18
CS 153 Design of Operating Systems Spring 18 Midterm Review Midterm in class on Friday (May 4) Covers material from arch spport to deadlock Based pon lectre material and modles of the book indicated on
More informationLecture 23: Router Design
Lecture 23: Router Design Papers: A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks, ISCA 06, Penn-State ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip
More informationMaster for Co-Simulation Using FMI
Master for Co-Simlation Using FMI Jens Bastian Christoph Claß Ssann Wolf Peter Schneider Franhofer Institte for Integrated Circits IIS / Design Atomation Division EAS Zenerstraße 38, 69 Dresden, Germany
More informationCS 153 Design of Operating Systems Spring 18
CS 153 Design of Operating Systems Spring 18 Lectre 9: Synchronization (1) Instrctor: Chengy Song Slide contribtions from Nael Ab-Ghazaleh, Harsha Madhyvasta and Zhiyn Qian Cooperation between Threads
More informationDPDK on Microsoft Azure
DPDK on Microsoft Azre Daniel Firestone Madhan Sivakmar DPDK Smmit - San Jose 2017 #DPDKSmmit Agenda Microsoft Azre The need for DPDK in the Clod NFV Accelerated Networking in Azre Enhancements to DPDK
More informationBasic Low Level Concepts
Course Outline Basic Low Level Concepts Case Studies Operation through multiple switches: Topologies & Routing v Direct, indirect, regular, irregular Formal models and analysis for deadlock and livelock
More information5 Performance Evaluation
5 Performance Evalation his chapter evalates the performance of the compared to the MIP, and FMIP individal performances. We stdy the packet loss and the latency to restore the downstream and pstream of
More informationComputer User s Guide 4.0
Compter User s Gide 4.0 2001 Glenn A. Miller, All rights reserved 2 The SASSI Compter User s Gide 4.0 Table of Contents Chapter 1 Introdction...3 Chapter 2 Installation and Start Up...5 System Reqirements
More informationTDT Appendix E Interconnection Networks
TDT 4260 Appendix E Interconnection Networks Review Advantages of a snooping coherency protocol? Disadvantages of a snooping coherency protocol? Advantages of a directory coherency protocol? Disadvantages
More informationNetworks An introduction to microcomputer networking concepts
Behavior Research Methods& Instrmentation 1978, Vol 10 (4),522-526 Networks An introdction to microcompter networking concepts RALPH WALLACE and RICHARD N. JOHNSON GA TX, Chicago, Illinois60648 and JAMES
More informationOpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel
OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel Hyoukjun Kwon and Tushar Krishna Georgia Institute of Technology Synergy Lab (http://synergy.ece.gatech.edu) hyoukjun@gatech.edu April
More informationDPDK s Best Kept Secret: Micro-benchmarks. M Jay DPDK Summit - San Jose 2017
DPDK s Best Kept Secret: Micro-benchmarks M Jay Mthrajan.Jayakmar@intel.com DPDK Smmit - San Jose 2017 Legal Information Optimization Notice: Intel s compilers may or may not optimize to the same degree
More informationOn the Computational Complexity and Effectiveness of N-hub Shortest-Path Routing
1 On the Comptational Complexity and Effectiveness of N-hb Shortest-Path Roting Reven Cohen Gabi Nakibli Dept. of Compter Sciences Technion Israel Abstract In this paper we stdy the comptational complexity
More informationEMC M&R (Watch4net ) Installation and Configuration Guide. Version 6.4 P/N REV 02
EMC M&R (Watch4net ) Version 6.4 Installation and Configration Gide P/N 302-001-045 REV 02 Copyright 2012-2014 EMC Corporation. All rights reserved. Pblished in USA. Pblished September, 2014 EMC believes
More informationContent Safety Precaution... 4 Getting started... 7 Input method... 9 Using the Menus Use of USB Maintenance & Safety...
STAR -1- Content 1. Safety Precation... 4 2. Getting started... 7 Installing the cards and the Battery... 7 Charging the Battery... 8 3. Inpt method... 9 To Shift Entry Methods... 9 Nmeric and English
More informationdss-ip Manual digitalstrom Server-IP Operation & Settings
dss-ip digitalstrom Server-IP Manal Operation & Settings Table of Contents digitalstrom Table of Contents 1 Fnction and Intended Use... 3 1.1 Setting p, Calling p and Operating... 3 1.2 Reqirements...
More informationNetSpeed ORION: A New Approach to Design On-chip Interconnects. August 26 th, 2013
NetSpeed ORION: A New Approach to Design On-chip Interconnects August 26 th, 2013 INTERCONNECTS BECOMING INCREASINGLY IMPORTANT Growing number of IP cores Average SoCs today have 100+ IPs Mixing and matching
More informationL EGAL NOTICES. ScanSoft, Inc. 9 Centennial Drive Peabody, MA 01960, United States of America
L EGAL NOTICES Copyright 2002 by ScanSoft, Inc. All rights reserved. No part of this pblication may be transmitted, transcribed, reprodced, stored in any retrieval system or translated into any langage
More informationProf. Kozyrakis. 1. (10 points) Consider the following fragment of Java code:
EE8 Winter 25 Homework #2 Soltions De Thrsday, Feb 2, 5 P. ( points) Consider the following fragment of Java code: for (i=; i
More informationComparison of memory write policies for NoC based Multicore Cache Coherent Systems
Comparison of memory write policies for NoC based Mlticore Cache Coherent Systems Pierre Gironnet de Massas, Frederic Petrot System-Level Synthesis Grop TIMA Laboratory 46, Av Felix Viallet, 38031 Grenoble,
More informationInterconnection Networks: Topology. Prof. Natalie Enright Jerger
Interconnection Networks: Topology Prof. Natalie Enright Jerger Topology Overview Definition: determines arrangement of channels and nodes in network Analogous to road map Often first step in network design
More informationCS 153 Design of Operating Systems Spring 18
CS 153 Design of Operating Systems Spring 18 Lectre 15: Virtal Address Space Instrctor: Chengy Song Slide contribtions from Nael Ab-Ghazaleh, Harsha Madhyvasta and Zhiyn Qian OS Abstractions Applications
More informationEnhanced Memory Management
Enhanced Memory Management DPDK Smmit - San Jose 2017 #DPDKSmmit Challenges The world is changing Adapt to varying application reqirements Performance, Secrity, Footprint, Robstness? Native, Containers,
More informationrte_security: enabling IPsec hw acceleration
rte_secrity: enabling IPsec hw acceleration Boris Pismenny (Mellanox) Declan Doherty (Intel) Hemant Agrawal (NXP) DPDK Smmit - San Jose 2017 #DPDKSmmit Introdction Framework for management and provisioning
More informationLocal Run Manager Generate FASTQ Analysis Module
Local Rn Manager Generate FASTQ Analysis Modle Workflow Gide For Research Use Only. Not for se in diagnostic procedres. Overview 3 Set Parameters 3 Analysis Methods 5 View Analysis Reslts 5 Analysis Report
More informationOpenSMART: An Opensource Singlecycle Multi-hop NoC Generator
OpenSMART: An Opensource Singlecycle Multi-hop NoC Generator Hyoukjun Kwon and Tushar Krishna Georgia Institute of Technology Synergy Lab (http://synergy.ece.gatech.edu) OpenSMART (https://tinyurl.com/get-opensmart)
More informationwebinar series
Ethernet@Atomotive webinar series Moving Forward: Tool Spported Development for Atomotive Ethernet in Time Sensitive Networks V1.06 2016-07-04 Agenda Introdction 3 Recap: Physical layers, network topology
More informationA Case for Low Frequency Single Cycle Multi Hop NoCs for Energy Efficiency and High Performance
A Case for Low Frequency Single Cycle Multi Hop NoCs for Energy Efficiency and High Performance Monodeep Kar and Tushar Krishna School of Electrical and Computer Engineering Georgia Institute of Technology
More informationLDAP Configuration Guide
LDAP Configration Gide Content Content LDAP directories on Gigaset phones............................................... 3 Configration.....................................................................
More informationCS 153 Design of Operating Systems Spring 18
CS 153 Design of Operating Systems Spring 18 Lectre 11: Semaphores Instrctor: Chengy Song Slide contribtions from Nael Ab-Ghazaleh, Harsha Madhyvasta and Zhiyn Qian Last time Worked throgh software implementation
More informationToday s Lecture. Software Architecture. Lecture 27: Introduction to Software Architecture. Introduction and Background of
Today s Lectre Lectre 27: Introdction to Software Architectre Kenneth M. Anderson Fondations of Software Engineering CSCI 5828 - Spring Semester, 1999 Introdction and Backgrond of Software Architectre
More informationThis chapter is based on the following sources, which are all recommended reading:
Bioinformatics I, WS 09-10, D. Hson, December 7, 2009 105 6 Fast String Matching This chapter is based on the following sorces, which are all recommended reading: 1. An earlier version of this chapter
More informationIncorporating DMA into QoS Policies for Maximum Performance in Shared Memory Systems. Scott Marshall and Stephen Twigg
Incorporating DMA into QoS Policies for Maximum Performance in Shared Memory Systems Scott Marshall and Stephen Twigg 2 Problems with Shared Memory I/O Fairness Memory bandwidth worthless without memory
More informationEMC VNX Series. Problem Resolution Roadmap for VNX with ESRS for VNX and Connect Home. Version VNX1, VNX2 P/N REV. 03
EMC VNX Series Version VNX1, VNX2 Problem Resoltion Roadmap for VNX with ESRS for VNX and Connect Home P/N 300-014-335 REV. 03 Copyright 2012-2014 EMC Corporation. All rights reserved. Pblished in USA.
More informationChapter 4: Network Layer
Chapter 4: Introdction (forarding and roting) Reie of qeeing theor Roting algorithms Link state, Distance Vector Roter design and operation IP: Internet Protocol IP4 (datagram format, addressing, ICMP,
More informationEEC 483 Computer Organization
EEC 483 Compter Organization Chapter 4.4 A Simple Implementation Scheme Chans Y The Big Pictre The Five Classic Components of a Compter Processor Control emory Inpt path Otpt path & Control 2 path and
More informationPipelined van Emde Boas Tree: Algorithms, Analysis, and Applications
This fll text paper was peer reviewed at the direction of IEEE Commnications Society sbject matter experts for pblication in the IEEE INFOCOM 007 proceedings Pipelined van Emde Boas Tree: Algorithms, Analysis,
More informationTdb: A Source-level Debugger for Dynamically Translated Programs
Tdb: A Sorce-level Debgger for Dynamically Translated Programs Naveen Kmar, Brce R. Childers, and Mary Lo Soffa Department of Compter Science University of Pittsbrgh Pittsbrgh, Pennsylvania 15260 {naveen,
More informationBIS - Basic Package V4.6
Engineered Soltions BIS - Basic Package V4.6 BIS - Basic Package V4.6 www.boschsecrity.com The Bilding Integration System (BIS) BIS is a flexible, scalable secrity and safety management system that can
More informationLecture 11: IPv6. CSE 123: Computer Networks Alex C. Snoeren. HW 2 due FRIDAY
Lectre 11: IPv6 CSE 123: Compter Networks Alex C. Snoeren HW 2 de FRIDAY IP Address Problem (1991) Address space depletion In danger of rnning ot of classes A and B Why? Class C too small for most organizations
More informationTDT4255 Friday the 21st of October. Real world examples of pipelining? How does pipelining influence instruction
Review Friday the 2st of October Real world eamples of pipelining? How does pipelining pp inflence instrction latency? How does pipelining inflence instrction throghpt? What are the three types of hazard
More informationNEtwork-on-Chip (NoC) [3], [6] is a scalable interconnect
1 A Soft Tolerant Network-on-Chip Router Pipeline for Multi-core Systems Pavan Poluri and Ahmed Louri Department of Electrical and Computer Engineering, University of Arizona Email: pavanp@email.arizona.edu,
More informationLecture 13: Interconnection Networks. Topics: lots of background, recent innovations for power and performance
Lecture 13: Interconnection Networks Topics: lots of background, recent innovations for power and performance 1 Interconnection Networks Recall: fully connected network, arrays/rings, meshes/tori, trees,
More informationThe Disciplined Flood Protocol in Sensor Networks
The Disciplined Flood Protocol in Sensor Networks Yong-ri Choi and Mohamed G. Goda Department of Compter Sciences The University of Texas at Astin, U.S.A. fyrchoi, godag@cs.texas.ed Hssein M. Abdel-Wahab
More informationUltra-Fast NoC Emulation on a Single FPGA
The 25 th International Conference on Field-Programmable Logic and Applications (FPL 2015) September 3, 2015 Ultra-Fast NoC Emulation on a Single FPGA Thiem Van Chu, Shimpei Sato, and Kenji Kise Tokyo
More informationThe single-cycle design from last time
lticycle path Last time we saw a single-cycle path and control nit for or simple IPS-based instrction set. A mlticycle processor fies some shortcomings in the single-cycle CPU. Faster instrctions are not
More information(2, 4) Tree Example (2, 4) Tree: Insertion
Presentation for se with the textbook, Algorithm Design and Applications, by M. T. Goodrich and R. Tamassia, Wiley, 2015 B-Trees and External Memory (2, 4) Trees Each internal node has 2 to 4 children:
More informationEMC NetWorker Module for SAP
EMC NetWorker Modle for SAP Version 8.2 Installation Gide P/N 302-000-390 REV 02 Copyright 2009-2014 EMC Corporation. All rights reserved. Pblished in USA. Pblished Agst, 2014 EMC believes the information
More informationLecture 4: Routing. CSE 222A: Computer Communication Networks Alex C. Snoeren. Thanks: Amin Vahdat
Lectre 4: Roting CSE 222A: Compter Commnication Networks Alex C. Snoeren Thanks: Amin Vahdat Lectre 4 Overview Pop qiz Paxon 95 discssion Brief intro to overlay and active networking 2 End-to-End Roting
More informationBIS - Basic Package V4.4
Engineered Soltions BIS - Basic Package V4.4 BIS - Basic Package V4.4 www.boschsecrity.com Integration of Bosch and third party systems via open interfaces and SDK All relevant information in one ser interface
More informationLecture 12: Interconnection Networks. Topics: communication latency, centralized and decentralized switches, routing, deadlocks (Appendix E)
Lecture 12: Interconnection Networks Topics: communication latency, centralized and decentralized switches, routing, deadlocks (Appendix E) 1 Topologies Internet topologies are not very regular they grew
More informationBIS - Basic package V4.2
Engineered Soltions BIS - Basic package V4.2 BIS - Basic package V4.2 www.boschsecrity.com Integration of Bosch and third party systems throgh deployment of OPC All relevant information in one ser interface
More informationBIS - Basic package V4.3
Engineered Soltions BIS - Basic package V4.3 BIS - Basic package V4.3 www.boschsecrity.com Integration of Bosch and third party systems throgh deployment of OPC All relevant information in one ser interface
More informationIntro To VLANS on the CRS Joshua Gray, Brian Vargyas Baltic Networks MUM 2016 CRS VLans
Intro To VLANS on the CRS Josha Gray, Brian Vargyas Baltic Networks Josha.gray@balticnetworks.com 1 Josha Bio Josha Gray Network Engineer Since 2008 Finishing masters degree in Network Engineering and
More informationNextSeq 550. System Guide. For Research Use Only. Not for use in diagnostic procedures. Document # v04 May 2018 ILLUMINA PROPRIETARY
NextSeq 550 System Gide Docment # 15069765 v04 May 2018 For Research Use Only. Not for se in diagnostic procedres. ILLUMINA PROPRIETARY NextSeq 550 System Gide This docment and its contents are proprietary
More informationLecture 26: Interconnects. James C. Hoe Department of ECE Carnegie Mellon University
18 447 Lecture 26: Interconnects James C. Hoe Department of ECE Carnegie Mellon University 18 447 S18 L26 S1, James C. Hoe, CMU/ECE/CALCM, 2018 Housekeeping Your goal today get an overview of parallel
More informationExceptions and interrupts
Eceptions and interrpts An eception or interrpt is an nepected event that reqires the CPU to pase or stop the crrent program. Eception handling is the hardware analog of error handling in software. Classes
More informationIoT-Cloud Service Optimization in Next Generation Smart Environments
1 IoT-Clod Service Optimization in Next Generation Smart Environments Marc Barcelo, Alejandro Correa, Jaime Llorca, Antonia M. Tlino, Jose Lopez Vicario, Antoni Morell Universidad Atonoma de Barcelona,
More informationAddressing in Future Internet: Problems, Issues, and Approaches
Addressing in Ftre Internet: Problems, Isses, and Approaches Mltimedia and Mobile commnications Laboratory Seol National University Jaeyong Choi, Chlhyn Park, Hakyng Jng, Taekyong Kwon, Yanghee Choi 19
More informationReview Multicycle: What is Happening. Controlling The Multicycle Design
Review lticycle: What is Happening Reslt Zero Op SrcA SrcB Registers Reg Address emory em Data Sign etend Shift left Sorce A B Ot [-6] [5-] [-6] [5-] [5-] Instrction emory IR RegDst emtoreg IorD em em
More informationEECS 570. Lecture 19 Interconnects: Flow Control. Winter 2018 Subhankar Pal
Lecture 19 Interconnects: Flow Control Winter 2018 Subhankar Pal http://www.eecs.umich.edu/courses/eecs570/ Slides developed in part by Profs. Adve, Falsafi, Hill, Lebeck, Martin, Narayanasamy, Nowatzyk,
More information