USB 3.2 PHY and Link Spec

Transcription

1 USB 3.2 PHY and Link Spec Howard Heck PHY WG Chair Huimin Chen Link WG Chair (Sponsored by Intel Corporation) USB Developer Days 2017 Taipei, Taiwan October 24 25,

2 USB 3.2 Goals Recap Doubling the BW with two lane bonding on Type C Focus on PHY/link layer with minimal impact to other layers PHY design reuse is a high priority both Gen1 (5Gbps) and Gen2 (10Gbps) supported Just works with existing software (OS/drivers) Maintaining parity with regard to USB 3.1 performance BER Channel loss budget Link power efficiency Preserving scalability for technology extensibility Retimer/active cable friendly

3 Introduction Scope x2 operation Requirements for active cables Organization Group requirements into a new section (6.13) wherever possible. Not Changed Data rates (Gen 1, Gen 2) Tx eye spec Loss & jitter budgets Rx JTOL Updates Lane numbering Data striping Data scrambling Ordered Sets & Lane Polarity Inversion Compliance Patterns Rx Detection Rx loopback LFPS Ux Exit SKP rules Test Points 3

4 Outline x2 Capability Determination Lane Numbering Data Striping Data Requirements Scrambling Ordered Sets Lane Polarity Inversion Lane-Lane Skew Compliance Patterns Functional Requirements Rx Detect Rx Loopback LFPS Ux Exit Clock Offset Compensation Test Points 4

5 PHY Capability Data rate Reserved # of lanes Reserved x2 Capability Determination (6.13.2) Uses the PHY Capability LBPM during Polling.Portmatch ( ). b0 b1 b2 b3 b4 b5 b6 b7 Gen 1x Gen 2x Gen 1x Gen 2x Polling.LFPSPlus SCD2.LFPS handshake Polling.PortMatch SCD1.LFPS handshake timeout timeout Polling Polling.LFPS Polling.LFPS handshake or timeout Polling.RxEQ TSEQ Ordered Sets Transmitted Polling.Active TS1 handshake PHY Capability LBPM handshake timeout Polling.Configuration Polling.PortConfig TS2 Handshake PHY Ready LBPM handshake timeout Polling.Idle Idle Symbol Handshake [b3:b2] = 00 : 5G = 01 : 10G [b6] = 0 : 1 lane = 1 : 2 lanes directed Exit to U0 5

6 Capability Matching & Fallback Defined in Match to least common capability. Fallback in order shown. USB 3.2 DFP Gen 1x1 Gen 1x2 Gen 2x1 Gen 2x2 Gen 1x1 Gen 1x1 Gen 1x1 Gen 1x1 Gen 1x1 USB 3.2 UFP Gen 1x2 Gen 1x1 Gen 1x2 Gen 1x1 Gen 1x2 Gen 2x1 Gen 1x1 Gen 1x1 Gen 2x1 Gen 2x1 Gen 2x2 Gen 1x1 Gen 1x2 Gen 2x1 Gen 2x2 Fallback Order 6

7 Lane Numbering (6.13.3) Lane 0 (Plug A2/A3 + B11/B10) is the Configuration Lane. Single-lane operation uses Lane 0 for backward compatibility. Configuration Lane SSTX1 SSRX1 Lane 0 SSTX1 SSRX1 CC1 CC wire CC1 Host USB USB D+/ USB D+/ Device USB CC Logic & VCONN Switch CC2 SSTX2 SSRX2 Lane 1 CC2 SSTX2 SSRX2 CC Logic 7

8 Lane Numbering (6.13.3) Lane 0 (Plug A2/A3 + B11/B10) is the Configuration Lane. Single-lane operation uses Lane 0 for backward compatibility. SSTX1 SSRX1 SSTX1 SSRX1 CC1 CC1 Host USB USB D+/ USB D+/ Device USB CC Logic & VCONN Switch CC2 CC2 CC Logic SSTX2 SSRX2 SSTX2 SSRX2 8

9 Data Striping (6.13.4) Data blocks are striped & aligned to lane 0. Data striping starts after SDS OS. Block headers are duplicated on both lanes. Start of packets may be initiated on either lane. 9

10 Data Requirements Scrambling per lane operation (6.13.5) Gen 1 seeds: lane 0 = FFFFh Gen 2 seeds: lane 0 = 1DBFBCh lane 1 = 8000h lane 1 = 0607BBh Ordered Sets (6.13.6) TS1, TS2, TSEQ, SDS, SKP, SYNC are transmitted simultaneously on all lanes. TS1, TS2 Tx and Rx requirements shall be satisfied for all negotiated lanes before transitioning from Polling.Active to the next state. Upon receiving TS1 on any negotiated lane during U0, enter recovery and begin transmitting TS1 on all negotiated lanes. Lane Polarity Inversion (6.13.7) Detection and correction shall be done on per lane basis for x2 operation. 10

11 Lane-Lane Skew Defined in Applies to Gen 1x2 & Gen 2x2 Comprehends skew sources: interconnect - PCB traces, PCB vias, package traces, circuit loading, connectors, cables re-timers on Tx and Rx boards requires deskew active cables - up to 50m optical Specs Test Point Max Skew (ps) Description TP Tx Si Output TP Tx Product Output/Cable Input TP Cable Output/Rx Product Input TP Rx Si Input TP1Ro, TP3Ro 1300 Output from Re-timer TP1Ri, TP3Ri 4800 Input to Re-timer 11

12 Compliance Patterns (6.13.9) No new patterns. Compliance patterns shall be transmitted independently on each lane. Transmit same pattern on each lane. CP0 and CP9 use the scrambler seeds defined in Advance to next CP upon receiving Ping.LFPS on either lane (refer to section 6.4.4). 12

13 Functional Requirements Rx Detect ( ) Performed only on the configuration lane (lane 0) Same LTSSM flow as for x1 Rx Loopback ( ) Performed on per lane basis All lanes exit from loopback upon receiving LFPS LFPS ( ) Transmit on the configuration lane Includes: Polling.LFPS (including SCD1/SCD2), LPBM, Ping.LFPS, Warm Reset, Loopback exit Ux Exit ( ) Ux exit functionality is enabled in the configuration lane Rx 13

14 Clock Offset Compensation SKP Insertion/Removal (6.13.6) Performed on a per-lane basis Transmitter rules ( ) x1 rules remain unchanged for Gen 1 and Gen 2 x2 rules Gen 1: follow Gen 1x1 rules AND multiply the # of SKP OS by the # of re-timers detected during re-timer presence announcement (E ) Gen 2x2: follow Gen 2x1 rules 14

15 TP1 TP1Ri TP1Ro TP2 TP3 TP3Ri TP4 Re-timer Mated Connector Mated Connector Re-timer Test Points Defined in (6.2.1) TP2 mid-point: defined to be after the mated receptacle/plug on the plug side with the plug test board with the traces de-embedded TP3 mid-point: defined to be after the mated receptacle/plug on the receptacle side with the USB Type-C cable test fixture Test Point TP1 TP2 TP3 TP4 TP1Ro, TP3Ro TP1Ri, TP3Ri Description Transmitter silicon pad Transmitter port connector mid-point Receiver port connector mid-point Receiver silicon pad Re-timer transmitter silicon pad Re-timer receiver silicon pad PCB Si Pkg + - Txp Txn Rxp Rxn + - PCB Si Pkg 15

16 Test Points: TP1 (Tx Silicon Pad) Application: Informative Tx jitter budget in Table 6-16 (6.5.1) Informative Tx specs in Table 6-19 (6.7.1) Tx lane-lane skew (6.13.8) Rx JTOL stressed source (swing, TxEQ, jitter) in Table 6-28 (6.8.5) Active cable input stressed source (swing, TxEQ, jitter) 16

17 Mated Connector Mated Connector Test Points: TP2 (Tx Connector Mid-point) Application: Tx SSC (6.5.3) Tx RJ (6.7.3) LFPS & LBPM (6.9) Active cable input stress signal Table 6-18 parameters (6.7.1) TxEQ (6.7.5) Lane-Lane Skew (6.13.8) TP1 TP2 TP1 TP2 TP1 TP Pkg Rx0n Rx0p Tx0n Tx0n Rx1n Rx1p Tx1n Tx1p Si Rx0n Tx1p Rx0p Tx1n Tx0n Rx1p Tx0p Full Breakout Rx1n Device Si Pkg + - Txp Txn Host Si Pkg + - Txp Txn compliant cable 17

18 Test Points: TP3 (Rx Connector Mid-point) Application: lane-lane skew (6.13.8) active cable output swing, TxEQ TP1 TP2 TP Rx0n Rx0p Rx1n Rx1p Tx0n Tx0p Tx1n Tx1p Si Rx0n Rx0p Rx1n Rx1p HF-1C Rx0p Rx0n Rx1p Rx1n CLB Pkg 18

19 Mated Connector Mated Connector Test Points: TP4 (Rx Silicon Pad) Application: Tx eye measurement (host, hub, active cable) eye height TJ (using RJ TP2) In practice, signal is TP2 Cable & CLB are embedded by Sigtest Pkg Device Rx0n Rx1p Rx1n Rx1n Tx0p Tx0n Tx1p Tx1n TP1 Si Si Pkg + - TP1 Txp Txn TP1 TP2 Rx0p Rx0n Rx1p Rx1n TP2 TP2 HF-1C compliant cable TP4 Rx0p Rx0n Rx1p Rx1n TP4 TP4 CLB Scope Host Si Pkg + - Txp Txn compliant cable Scope 19

20 Mouse Range (ft) Radio Frequency Interference Wifi Impact Wireless Mouse Sensitivity Impact Noise (dbm/100khz) SuperSpeed data traffic can degrade wireless data throughput & reliability. 20

21 Noise Coupled (dbm/100khz) USB-C System RFI Test Specification Compliance Test Setup Frequency (GHz) *Noise level specified is after correction for preamplifier gain Fixture System RFI spec & compliance test ensures coexistence with wireless links. 21

22 Design for RFI Coupling Major noise coupling path: mating interface between the receptacle & plug, cables Resources Connector selection: USB Type-C Cable and Connector Specification, Section System design: Resources are available for designing your system to meet RFI requirements. 22

23 Link Layer/Re-timer Update What s New PHY Capability LBPM enhanced Re-timer presence announcement Introduction to USB 3.2 Re-timer x2 re-timer requirement Link delay impact to Gen 2x2 performance Increase Rx Header Buffer Credit PM_LC_TIMER/PM_ENTRY_TIMER Polling.LFPS 60-us LFPS EI ECR No change to LTSSM and link layer framework 23

24 PHY LBPM Definition Backwards compatible Added new functions in PHY Ready LBPM b6: for re-timer to determine port orientation to host DFP or device UFP b7: for host to determine if re-timers need to be addressed LBPM message is state dependent 24

25 Re-timer Presence Announcement Time DFP DFP DFP DFP PHY Ready LPBM[b7:b0] Re-timer Re-timer 1 Re-timer 1 Re-timer 2 Re-timer 2 Re-timer Re-timer Re-timer 2 Re-timer Re-timer 3 Re-timer 3 Re-timer Re-timer 4 Re-timer 4 Re-timer Re-timer UFP PHY Ready LPBM[b7:b0] UFP UFP UFP x2 only Defined for re-timer to announce its presence Port may insert SKP OS based on the number of retimers Preserve a mechanism in future revisions for host to discover and configure retimer Re-timer to increment b[4:2] when forwarding LBPM b[4:2] of the LBPM from host will be the re-timer index for future addressing 25

26 Re-timer Presence Announcement in Polling.PortConfig Case #1: no host addressing to re-timer Bit 7 de-asserted Re-timer presence announcement DFP completes PHY Ready LBPM handshake tpollinglbpmlfpstimeout DFP Polling.PortMatch TSEQ Four PHY Ready LBPMS sent after receiving two Polling.PortConfig (DFP) Polling.PortConfig (UFP) Four PHY Ready LBPMS sent after receiving two UFP Polling.PortMatch TSEQ tpollinglbpmlfpstimeout PHY Ready LBPM Re-timer presence announcement UFP completes PHY Ready LBPM handshake Re-timer shall get both ports ready before forwarding the LBPM Re-timer may delay by one LBPM before forwarding To allow re-timer to update b[4:2] 26

27 Re-timer Presence Announcement in Polling.PortConfig Case #2: host addressing to re-timer PHYReady LBPM handshake for re-timer addressing Bit 7 asserted DFP completes PHY Ready LBPM handshake Bit 7 de-asserted DFP completes PHY Ready LBPM handshake DFP tpollinglbpmlfpstimeout continue Polling.PortMatch tpollinglbpmlfpstimeout reset tpollinglbpmlfpstimeout Re-start TSEQ Polling.PortConfig (DFP) Polling.PortConfig (UFP) UFP Polling.PortMatch TSEQ tpollinglbpmlfpstimeout continue (tpollinglbpmlfpstimeout reset) PHY Ready LBPM UFP completes PHY Ready LBPM handshake UFP detects bit 7 de-asserted from DFP UFP completes PHY Ready LBPM handshake DFP enters re-timer addressing stage after first PHY Ready LBPM handshake Timeout handled by upper layer USB 3.2 re-timer passes LBPM as is Upon completing re-timer addressing, DFP initiates PHY Ready LBPM and proceeds to exit Minimum implementation required to allow USB 3.2 re-timer forward compatible 27

28 Scenario analysis of re-timer addressing RT1 host RT1 RT2 RT3 RT4 device Host/device achieve PHY_Ready LBPM handshake with bit-7 in host PHY_Ready LBPM asserted all host/device/re-timers remain in Polling.PortConfig Host is not aware of RT s capability, and starts addressing RT1 RT1 passes thru RTConfig LBPM (to be defined in future revision) RT2, upon detecting RTConfig LBPM addressing its preceding RT1, drops RTConfig LBPM Host times out and declares RT1 non addressable RT3/RT4/Device remain in Polling.PortConfig RT (non-addressable) RT (addressable)

29 Scenario analysis of re-timer addressing RT2-RT4 host RT1 RT2 RT3 RT4 device RT (non-addressable) Host starts addressing RT2 RT1 passes RTConfig LBPM RT2 decodes RTConfig LBPM and acknowledge RT3/RT4/Device remain Polling.PortConfig Upon completion of RT2 configuration, host addresses RT3 RT3 passes LBPM and RT4 discarded it Host times out and concludes RT3 non addressable and starts addressing RT4 After RT4 config, host issues PHY_Ready LBPM with bit-7 deasserted All RT pass the PHY_Ready LBPM and monitor the exit handshake Device upon detecting PHY_Ready LBPM, participates the exit handshake Upon completing the exit handshake, host/dev/rt enter Polling.RxEQ RT (addressable)

30 Scenario analysis of re-timer addressing RT1~RT4 host RT1 RT2 RT3 RT4 device All retimers are not addressable 1. Host starts addressing RT1 2. RT1~RT4 passes RTConfig LBPM 3. Device detect RTConfig LBPM and discarded 4. Host times out and declares RT1 non-addressable Host repeats step 1~4 until it concludes all RT nonaddressable Host issues PHY_Ready LBPM with bit-7 de-asserted All RT pass the PHY_Ready LBPM and monitor the exit handshake Device upon detecting PHY_Ready LBPM, participate the exit handshake Upon completing the exit handshake, host/dev/rt enter Polling.RxEQ RT non-(addressable) RT (addressable)

31 Introduction to USB 3.2 Re-timer Rx[1:0] Tx[1:0] Rx Tx Symbol Recovery Symbol Recovery RTSSM Scrambler Sync Scrambler Sync LTSSM EB EB Protocol intercept RD monitor Descramble Data striping Deskew Deskew Deskew Deskew RTSM Data striping Descramble RD monitor Protocol intercept EB EB Scrambler Sync Scrambler Sync LTSSM Symbol Recovery Symbol Recovery Lane to lane de-skew OS boundary shall be maintained when switching from local to received TS1/2 OS preserve Tx lane to lane skew De-skew can be performed based TS1/2 OS, SKP OS, or SYNC OS Tx Rx Tx[1:0] Rx[1:0] Lane to lane de-skew adds propagation delay in EB Two-lane bonding with lane to lane deskew Only SRIS re-timer is defined for x2 operation Re-timer SKP OS Gen 1x2: based on re-timer presence announcement (new) Gen 2x2: same as Gen 2x1, option to reduce based on re-timer presence announcement tdre-timer budget Gen 1x2: 300 ns Gen 2x2: 150 ns 31

32 x2 Re-timer Lane to Lane De-skew and EB Depth SKP OS insertion rule same as x1 per lane based Packets transmitted on two-lanes EB depth reduced Gen 1: 5-SI [(354 +(1056/2)x5e-3] Gen 2: 6-SI [(40+68/2)x16x5e-3] Rx data path skew Half-full Gen 1x1 EB De-skew buffer depth: z = x + y RxD 8-SI 8-SI TxD Max input skew 4.8ns x SI RxCLK TxCLK Gen 1: x = 3-SI Gen 2: x = 6-SI Max Rx data path skew y SI Half-full Gen 1x2 EB w. De-skew Implementation specific Want z < 8 if use TS1 OS to perform de-skew RxD0 RxCLK0 TxD0 TxCLK If z > 8 Use SKP OS in Gen 1 (354 SI delay) RxD1 RxCLK1 5-SI z-si 5-SI TxD1 TxCLK Use SYNC OS in Gen 2 (32 block delay) 32

33 Link delay impact to Gen 2x2 performance Problem statement Proposed tdre-timer, and tdhpresponse have added significant delay that may degrade throughput performance in Gen2x2 operation tdre-timer = 150nS, tdhpresponse = 1255ns (tdpacket:~460ns; SKPs: 20ns; HP process time: ~480ns) Total Roundtrip delay to return LCRD: ~2.2us (150x ) Rx Header Buffer Credit LCRD_x = 4 per each traffic class Allow 4 outstanding packets 4 max. Gen2 x2 = 4 x 450nS (34 blocks) ~1.8uS After burst 4 DP, the port has to wait 400ns for returned LCRD before starting another transfer 400ns of IS between the two burst Effective throughput (1.8/2.2)x20Gbps 16Gbps (max) Want round-trip delay < burst duration to sustain the throughput

34 Proposal Apply to Gen2 x2 only Increase the number of credits available from 4 to 7 LCRD A,B,C,D,E,F,G. (for both Type 1 and Type 2) Allow upto 7 outstanding packets max burst duration is ~3.2us Enough to cover max roundtrip delay up to 3uS and continue the burst No change in header sequence numbers, LGOOD 0 15 Spec changes: Change the link command word in Gen 2x2 b3 -> Credit Series (0 = LCRD1_x, 1 = LCRD2_x) b[2:0] -> Rx Header buffer credit ( > LCRD A to G; 111-> Reserved)

35 Additional Timing Adjustment in x2 Operation PM_LC_TIMER/PM_ENTRY_TIMER doubled in x2 operation 35

36 Gen 2x2 Block Header Errors 36

37 Polling.LFPS 60us LFPS EI ECR Proposed to address legacy device passing compliance but not compliant to spec USB 3.1 Gen 1 devices found to not exit from Polling.LFPS even after completing the Polling.LFPS handshake Exit only after DFP has stopped sending Polling.LFPS The above behavior leads to USB 3.1 Gen 2 capable DFP, after falling back to SS operation, will NOT achieve the timeout condition of the 60-us LFPS EI timer 37

38 Q&A 38