Communication Protocols

Transcription

1 Communication Protocols

2 Communication Protocols Layering Lower levels provide services to higher level Easier to design Physical layer Lowest level in hierarchy Medium to carry data from one actor (device or node) to another Protocols: real-time or best effort Parallel Serial Wireless

3 Parallel communication Multiple data, control, and power wires One bit per wire High data throughput with short distances Typically used when connecting devices on same IC or same circuit board Bus must be kept short long parallel wires result in high capacitance values which requires more time to charge/discharge Data misalignment between wires increases as length increases Higher cost, bulky

4 Parallel Protocols: PCI Bus PCI Bus (Peripheral Component Interconnect) High performance bus designed by Intel in the 1990 s Interconnects CPUs, expansion boards, memory Data transfer rates up to 1GBs for 64 bit addresses Synchronous bus architecture Multiplexed data/address lines PCI express Serial, point-to-point protocol Source:

5 Parallel Protocols: ARM Bus ARM Bus Designed and used internally by ARM Corporation Interfaces with ARM line of processors Many IC design companies have own bus protocol Data transfer rate is a function of clock speed 32-bit addressing

6 Serial Communication Single data wire transmit one bit at a time Higher data throughput with long distances Less average capacitance, so more bits per unit of time Complex protocol and interfacing logic Sender needs to decompose word into bits Receiver needs to recompose bits into word Control signals often on the same wire -> increasing protocol complexity

7 Serial Communication Parameters: Baud (bit) rate. Number of bits per character. Parity/no parity. Even/odd parity. Length of stop bit (1, 1.5, 2 bits). no char start bit 0 bit 1... bit n-1 stop time

8 Serial Protocol: 8251 UART Universal asynchronous receiver transmitter Takes parallel data and transmits serially at up to max 450 Kbps 8251 chip functions are integrated into standard PC interface chip. status (8 bit) CPU 8251 data (8 bit) xmit/ rcv serial port

9 Serial Protocols: I 2 C I 2 C (Inter-IC) Two-wire serial bus protocol developed by Philips Semiconductors ~20 years ago Enables peripheral ICs to communicate using simple communication hardware appropriate for peripherals where simplicity and low manufacturing cost are more important than speed Normal mode: 100 Kbps with 7-bit address Fast mode: 3.4 Mbpbs with10-bit address Common devices capable of interfacing to I 2 C bus: EPROMS, Flash, and some RAM memory, real-time clocks, watchdog timers, and microcontrollers Raspberry PI

10 Serial Protocols: USB USB (Universal Serial Bus) Easier connection between PC and peripherals USB 1.1 has 2 data rates: 12 Mbps for increased bandwidth devices 1.5 Mbps for lower-speed devices (joysticks, game pads) USB 2.0 runs at 480 Mbps; USB 3.1 up to 10 Gbps Tiered star topology can be used One USB device (hub) connected to PC Up to 127 USB devices can be connected to hub USB host controller Manages and controls bandwidth and driver software required by each peripheral Dynamically allocates power downstream according to devices connected/disconnected

11 Source: PCI Express (PCIe) Serial, point-to-point protocol Bandwidth is very scalable: 1x-16x links Max 6.4GBps in either direction on x16 Switches for connecting different devices

12 Real-Time Communication & Protocol Examples

13 Class Overview What ve covered until now in SW: Real-time scheduling, RTOS, RTIO started Where we are going today: RTIO, HW/SW codesign Due today: Article on RTIO Upcoming: HW2 assigned Individual project part 2 deadline extended to end of the day Sunday, 2/19

14 Real-time Comm. Requirements Real-time behavior Efficient, economical (e.g. centralized power supply) Appropriate bandwidth and communication delay Robustness Fault tolerance Maintainability Diagnosability Security Safety

15 Field bus: Real-time IO A family of industrial computer network protocols used for real-time distributed control Carrier-sense multiple-access/collision-detection (CSMA/CD); used in Ethernet & CAN Alternatives: Token rings, token busses Carrier-sense multiple-access/collision-avoidance: CSMA/CA Each partner gets an ID (priority). After each bus transfer, all partners try setting their ID on the bus; partners detecting higher ID disconnect themselves from the bus. Highest priority partner gets guaranteed response time; others communicate only if they are given a chance.

16 Event vs. time triggered Event Triggered (ET): Computation/communication triggered by an external event Events are primarily generated by changes in the environment Efficient only do things when they need to be done; rest and save energy/cpu time/bandwidth High peak-load if multiple events happen at once Hard to analyze due to asynchronous nature of events Time Triggered (TT): Computation/communication triggered by the system clock Events happen according to a fixed schedule: Inefficient does things periodically, whether needed or not Enhanced analizability due to easily characterizable load, predictable interaction sequences, bus use, etc.

17 Time division multiple access Each assigned a fixed time slot: Master sends sync Some waiting time Each slave transmits in its time slot Variations (truncating unused slots, several slots per slave) exist

18 Advantages of TDMA-busses over priority-driven schemes Can provide QoS guarantees TDMA resources support temporal composability, by separating resource access of different subsystems TDMA resources have a very deterministic timing behavior Can be made fault tolerant Support for error detection Support for error contention a faulty subsystem does not affect the correct behavior of the remaining system [Ernesto Wandeler Lothar Thiele: Optimal TDMA Time Slot and Cycle Length Allocation for Hard Real-Time Systems, ASP-DAC, 2006]

19 Field busses: Profibus Process Field Bus (Profibus): PROFIBUS DP (Decentralized Peripherals) is used to operate sensors and actuators via a centralized controller in factory automation apps; runs at 9.6kbps 12 Mbps; RS485 allows max 126 devices, but expansion is possible ROFIBUS PA (Process Automation) is used to monitor measuring equipment via a process control system in process automation apps; runs at 31.2 kbps; same message format as DP Focus on safety; 20% market share for field busses. Integration with Ethernet via Profinet. [

20 Profibus: Application & Data Layers Application layer: DP-V0 for cyclic exchange of data and diagnosis DP-V1 for acyclic data exchange and alarm handling DP-V2 for slave2slave comm and data exchange broadcast Data link: FDL (Field bus Data Link) combines token passing with a master-slave method for Profibus-DP Each byte uses even parity and is transferred asynchronously with a start and stop bit Master signals the start of a new telegram with a SYN pause of at least 33 bits Various messages possible: Token Variable data length Fixed data length No data Brief ack OSI-Layer PROFIBUS 7 Application DPV0 DPV1 DPV2 6 Presentation 5 Session 4 Transport 3 Network 2 Data Link FDL 1 Physical EIA-485 Optical MBP -- Management

21 Controller area network (CAN) Designed by Bosch and Intel in 1981; Key concept: every device can be connected by a single set of wires, and every device that is connected can freely exchange data with any other device Originally designed for cars; now used also for: elevator controllers, copiers, telescopes, production-line control systems, and medical instruments Binary countdown arbitration (CSMA/CD) Start from MSB, transmit each bit of priority Highest priority wins Throughput:10kbit/s - 1 Mbit/s Low and high-priority signals maximum latency of 134 µs for high priority

22 Aircraft communication systems Information exchange information many bytes of data: e.g. digital map, flight plan, etc. exchange : a response is expected, at min acknowledgment higher speed data link needed Control platform: sampling and data transmission data : digital value of an analog parameter: e.g. speed; height etc. No response is expected, but: Time, integrity and availability are the key drivers. The stability of the flight relies on this transmission Aeronautical response : ARINC 429 protocol

23 ARINC 429 overview Developed by Aeronautical Radio, Incorporated (ARINC) Commonly used standard for the aircraft Electrical and data format standard for a 2-wire serial bus with one sender and many listeners. Each data is individually identified (by a label) and sent Application label data Transport Network DataLink/MAC Physical connection A bit label data parity

24 Information system requirements Ensure that the information is transmitted without any error. Data needs to be acknowledged Messages can be sent again in case of error Past aircraft uses A429 but added acknowledgement. Application Transport A429 williamsburg Network DataLink/MAC Physical connection A429

25 ARINC 629 Multi-transmitter protocol where many units share the same bus; originally designed for Boeing 777. Based on "waiting room" protocol: Each node is assigned a unique number of mini slots that must elapse with silence on the channel before the data transmission begins Three (groups of) time-out parameters: SG synchronization gap controlling access to the waiting room TGi terminal gap, the personal time-out of node I TI transmit interval preventing monopolization of channel TI > SG > max{tgi }

26 TTP (Time-Triggered Protocol) TTP more than just a protocol Network protocol Operating system scheduling philosophy Fault tolerance approach Time-Triggered approach Simple to implement Stable time base Cyclic schedules Sources: Dr. Insup Lee & H. Kopetz

27 TTP versions TTP/A (Automotive Class A = soft real time) A scaled-down version of TTP A cheaper master/slave variant Distributed master slave is expensive TTP/C (Automotive Class C = hard real time) A full version of TTP A fault-tolerant distributed variant

28 Protocol Layer in TTP/A

29 Operation TTP/A: Polling Master polls the other nodes (slaves) Non-master nodes transmit messages when they are polled Inter-slave communication through the master

30 Polling Tradeoffs Advantages Simple protocol to implement Historically very popular Bounded latency for real-time applications Disadvantages Single point of failure from centralized master Polling consumes bandwidth Network size is fixed during installation Master can also discover nodes during reconfiguration

31 TTP/C TTP/C A time-triggered communication protocol for safetycritical (fault-tolerant) distributed real-time control systems Based on a TDMA media access strategy Clock synchronization: Each node measures the difference between the expected and the observed arrival time of a message to calculate the difference between the sender s & receiver s clocks Fail Silence A subsystem is fail-silent if it either produces correct results or no results at all, i.e., it is quiet in case it cannot deliver the correct service

32 TTP/C Protocol Layer Host Layer FTU CNI Fault tolerance unit Communication Network Interface (CNI) FTU Layer Basic CNI RM Layer SRU Layer Smallest Replaceable Unit Data Link/Physical Layer Application software in host FTU Membership Redundancy Management (RM) SRU Membership Clock Synchronization Media Access: TDMA FTU Layer Group two or more nodes into FTUs RM Layer Provide the mechanisms for the cold start of a TTP/C cluster SRU Layer Store the data fields of the received frames Data Link/Physical Layer Provide the means to exchange frames between the nodes

33 FTU Configuration Examples in TTP/C (a) Two active nodes, two shadow nodes (b) Triple modular redundancy: three active nodes with one shadow (c) Two active nodes without a shadow node

34 Controller to run protocol DPRAM (dual ported RAM) Used for memory-mapped network interface BG (Bus Guard) Hardware watchdog to ensure fail silent HW must use highly accurate time sources Dual redundant crystal oscillators are used for Boeing 777

35 TTP/C Frame I-Frames used for initialization N-Frames used for normal messages

36 Cycle in TTP/C TDMA Cycle One FTU sends results twice Then next FTU sends results And so on, until back to the next message from the first FTU Cluster Cycle Cluster cycle involves scheduling all messages and tasks

37 TTP/A vs. TTP/C Service TTP/A TTP/C Clock Synchronization Central Multimaster Mode Switches yes yes Distributed, Fault-Tolerant Communication Error Detection Parity 16/24 bit CRC Membership Service simple full External Clock Synchronization yes yes Time-Redundant Transmission yes yes Duplex Nodes no yes Duplex Channels no yes Redundancy Management no yes Shadow Node no yes

38 Pros and Cons of TTP Advantages Simple protocol to implement Deterministic response time No wasted time for master polling messages Disadvantages Wasted bandwidth when some nodes are idle Stable clocks Fixed network size during installation

39 FlexRay Robust, scalable, deterministic, and fault-tolerant digital serial bus system designed for use in automotive applications Developed by consortium: BMW, Ford, Bosch,Daimler-Chrysler Specified in SDL; finalized in 2009 Built as extension to TTP and Byteflight protocols. Improved error tolerance and time-determinism Meets requirements with transfer rates >> CAN initially targeted for ~ 10Mbit/sec; design allows much higher data rates TDMA (Time Division Multiple Access) protocol: Fixed time slot with exclusive access to the bus Cycle subdivided into a static and a dynamic segments

40 TDMA in FlexRay Exclusive bus access enabled for short time in each case. Dynamic segment for transmission of variable length information. Fixed priorities in dynamic segment: minislots for each potential sender. Bandwidth used only when it is actually needed.

41 Structure of Flexray networks Bus Guardian (BG) protects the system against failing processors by gating access to Bus Driver (BD)

42 Comparison of real-time protocols FIP = Flexible time triggered protocol; statically scheduled with centralized arbitration LON = for building automation, uses TDMA with CSMA/CA and dynamically varies the number of slots per device for each schedule

43 Wireless communication Infrared (IR) Frequencies just below visible light spectrum Diode emits infrared light to generate signal Infrared transistor detects signal Cheap to build but need line of sight, limited range Data transfer rate of 9.6 kbps and 4 Mbps Radio frequency (RF) Electromagnetic wave frequencies in radio spectrum Analog circuitry and antenna needed on both sides Line of sight not needed, transmitter power determines range

44 RFID Use of EM field to transfer data, for identifying and tracking tags attached to objects; no need for line of sight Active vs. passive tags Active transmits ID, they are low power (~10-100uA) but higher cost ($10- $200/unit retail) Passive can be read by RF - no intrinsic power consumption (powered by EM induction) and cheaper ($ ) Readers $100+ to $1000s, range from read and report to smart tracking, etc. Using RFID for real-time location systems (RTLS) Only active tags work with range 100m+ in line of sight, or 1-20m obstructed Battery - up to years on a single <1Hz transmission rate Location accuracy as close as 30cm with reader presence

45 Bluetooth BLE ZigBee Bluetooth, BLE, Zigbee IEEE Developed and licensed by the Bluetooth Special Interest Group (SIG) Adopted into Bluetooth specification Bluetooth Low Energy Technology IEEE Maintained and published by the ZigBee Alliance

46 Side By Side Comparison Bluetooth BLE ZigBee Band 2.4GHz 2.4GHz 2.4GHz, 868MHz, 915MHz Antenna/HW Shared Independent Power 100 mw ~10 mw 30 mw Battery Life Days months 1-2 years 6 months 2 yrs Range m 10 m m Data Rate 1-3 Mbps 1 Mbps Kbps Network Topologies Time to Wake and Transmit Ad hoc, point to point, star Ad hoc, point to point, star 3s 3ms 15ms Mesh, ad hoc, star Security 128-bit encryption 128-bit encryption 128-bit encryption

47 Wireless Protocols: IEEE Standard for wireless LANs Specifies parameters for PHY and MAC layers of network PHY layer handles transmission of data between nodes data transfer rates up to 600 Mbit/s for n operates in 2.4 / 5 GHz frequency band (RF) MAC layer medium access control layer protocol responsible for maintaining order in shared medium collision avoidance/detection

48 Summary Interfacing: on & off chip Real-time IO Profibus CAN ARINC TTP/A & TTP/C FlexRey Wireless IR, BLE, ZigBee, RFID,

49 Hardware/Software Codesign Tajana Simunic Rosing Department of Computer Science and Engineering University of California, San Diego.

50 ES Design Hardware components Hardware Verification and Validation

51 HIGH DENSIT Y System Architecture: Yesterday PCB design Processor Cache/DRAM Controller Cache VRAM DRAM Audio Motion Video Add-in board VRAM DRAM PCI Bus SCSI/ IDE LAN I/O External Bus Graphics DRAM VRAM 3M ISA/EISA

52 LAN Interface Encryption/ Decryption Motion I/O Interface A System Architecture: Today HW/SW Codesign of a SoC PCI Interface Processor Core Glue VRAM Glue DSP Processor Core Graphics Video SCSI MEMORY Cache/SRAM EISA Interface

53 DMA Interface System Design Problem Areas 1. Design environment, co-simulation constraint analysis. Interface Analog I/O 2. HDL Modeling Architectural synthesis Logic synthesis Physical synthesis 4. Test Issues Processor ASIC 3. Software synthesis, Optimization, Retargetable code gen., Debugging & Programming environ. Memory

54 HW-centric view of a Platform Pre-Qualified/Verified Foundation-IP* Hardware IP SW IP Programmable HW-SW Kernel MEM + Reference Design Application Space CPU FPGA Scaleable bus, test, power, IO, clock, timing architectures Processor(s), RTOS(es) and SW architecture Reconfigurable Hardware Region (FPGA, LPGA, ) IP can be: HW or SW hard, soft or firm (HW) source or object (SW) Foundry-Specific HW Qualification SW architecture characterisation Source: Grant Martin and Henry Chang, Platform-Based Design: A Tutorial, ISQED 2002, 18 March 2002, San Jose, CA.

55 RTOS Network Communication SW-Centric View of Platforms Application Software Platform API Software Platform Hardware Platform Input devices Output Devices Software Hardware I O network API Device Drivers BIOS Source: Grant Martin and Henry Chang, Platform-Based Design: A Tutorial, ISQED 2002, 18 March 2002, San Jose, CA.

56 HW/SW Codesign: Motivations Benefit from both HW and SW HW: SW Parallelism -> better performance, lower power Higher implementation cost Sequential implementation -> great for some problems Lower implementation cost, but often slower and higher power

57 Software or hardware? Decision based on hardware/ software partitioning

58 Hardware/software codesign Specification Mapping Processor P1 Processor P2 Hardware

59 System Partitioning process (a, b, c) in port a, b; out port c; { read(a); write(c); } Specification Capture Model Partition Synthesize Line () { a = detach } Processor Interface HW Good partitioning mechanism: 1) Minimize communication across bus 2) Allows parallelism -> both HW & CPU operating concurrently 3) Near peak processor utilization at all times

60 Determining Communication Level Application Program Operating System I/O driver Send, Receive, Wait Register reads/writes Interrupt service Application hardware (custom) I/O driver I/O bus Bus transactions Interrupts I/O bus Easier to program at application level (send, receive, wait) but difficult to predict More difficult to specify at low level Difficult to extract from program but timing and resources easier to predict

61 Partitioning Costs Software Resources Performance and power consumption Lines of code development and testing cost Cost of components Hardware Resources Fixed number of gates, limited memory & I/O Difficult to estimate timing for custom hardware Recent design shift towards IP Well-defined resource and timing characteristics

62 Software Functional Blocks Cost Analysis Calibration Feature Points Process Language Conversion Source Lines of Code (SLOC) Equivalent SLOC including reuse Software development effort Software maintenance effort Software schedule Software Development and Testing Cost

63 Hardware Gate Count S/G Ratio Cost Rent s Rule I/O Count Single-Chip- Package Cost Analysis Process Interconnect Length Feature Size Core Area I/O Format Die Area Number Up Wafer Characteristics Die Yield Wafer Fabrication and Sawing Cost Die Cost Chip Hardware Cost Tooling Cost Test Development Cost Productivity, reuse Design Cost

64 Hardware/Software Partitioning Simple architectural model: CPU + 1 or more ASICs on a bus memory ASIC Processor ASIC Properties of classic partitioning algorithms Single rate; Single-thread: CPU waits for ASIC Type of CPU is known; ASIC is synthesized

65 HW/SW Partitioning Styles HW first approach start with all-asic solution which satisfies constraints migrate functions to software to reduce cost SW first approach start with all-software solution which does not satisfy constraints migrate functions to hardware to meet constraints

66 Codesign Verification Run SW on the CPU Simulate HW (Verilog) Verilog Simulator Application-specific hardware Hardware Process 1 Hardware Process 1 Software process 1 Software process 2 Unix sockets Bus interface Verilog PLI

67 SpecC model

68 Foresight Co-Design System Requirements Capture Functional Behavior Block Diagram Minispecs Userdefined Reusables State Machines Library Elements Integrated Toolset Data Flow Monitors Architecture Block Diagram Resource Specification System Characteristics Derived from Foresight Gate Count Lines of Code Cost Analysis (Ghost) I/O Count HW Number Up Dev. Cost SW Dev. Schedule Die Size SCP Cost Fab. Cost Test Cost Maintenance Cost Outputs System Performance Metrics System Cost Co-Design Process

69 Industry Initiatives Seamless Co-Verification Environment-CVE Proridium (Foresight) Customers: Boeing, Microsoft, Raytheon, Oracle etc. CoWare (now in Synopsys) Cosimulation and IP integration One of founding members of SystemC (language) New FPGA synthesis tools incorporate CPUs Platform-based design Platform: predesigned architecture that designers can use to build systems for a given range of applications

70 ILP for HW/SW Partitioning Ingredients: Cost function Constraints Involving linear expressions of integer variables from a set X Cost function C a x with a R, x N (1) x X i Constraints: j J b x c with b, c (2) Def.: The problem of minimizing (1) subject to the constraints (2) is called an integer programming (IP) problem. If all x i are constrained to be either 0 or 1, the IP problem said to be a 0/1 integer programming problem. i i : i, j i j i, j j R x X i i i N R

71 FAQ on integer programming Maximizing the cost done by setting C =-C Integer programming is NP-complete. Running times increase exponentially with problem size Commercial solvers can solve for thousands of variables IP models are a good starting point for modelling even if in the end heuristics have to be used to solve them.

72 IP model for HW/SW partitioning Notation: Index set I denotes task graph nodes. Index set L denotes task graph node types e.g. square root, DCT or FFT Index set KH denotes hardware component types. e.g. hardware components for the DCT or the FFT. Index set J of hardware component instances Index set KP denotes processors. All processors are assumed to be of the same type T is a mapping from task graph nodes to their types T: I L Therefore: X i,k : =1 if node v i is mapped to HW component type k KH Y i,k : =1 if node v i is mapped to processor k KP NY l,k =1 if at least one node of type l is mapped to processor k KP

73 Constraints Operation assignment constraints i I 1 : X i, k Yi, k k KH k KP All task graph nodes have to be mapped either in software or in hardware. Variables are assumed to be integers. Additional constraints to guarantee they are either 0 or 1: i I i I : k KH :, 1 X i : k KP :, 1 Y i k k

74 Operation assignment constraints l L, i:t(v i )=c l, k KP: NY l,k Y i,k For all types l of operations and for all nodes i of this type: if i is mapped to some processor k, then that processor must implement the functionality of l. Decision variables must also be 0/1 variables: l L, k KP: NY l,k 1.

75 Resource & design constraints k KH, the cost for components of that type should not exceed its maximum. k KP, the cost for associated data storage area should not exceed its maximum. k KP the cost for storing instructions should not exceed its maximum. The total cost ( k KH ) of HW components should not exceed its maximum The total cost of data memories ( k KP ) should not exceed its maximum The total cost instruction memories ( k KP ) should not exceed its maximum

76 Scheduling v 1 v 2 v 3 v 4 e 3 e 4 Processor FIR 1 FIR 2 p 1 ASIC h 1 v 5 v 6 v 7 v 8 Communication channel c 1 v 9 v 10 FIR 2 on h 1 p 1 c 1 v v... 3 v 4... v... 7 v 8... e 3... e 4 or... v... 4 v 3 t or... v... 8 v 7 t or e 4 e 3 t

77 Scheduling / precedence constraints For all nodes v i1 and v i2 that are potentially mapped to the same processor or hardware component instance, introduce a binary decision variable b i1,i2 with b i1,i2 =1 if v i1 is executed before v i2 and = 0 otherwise. Define constraints of the type (end-time of v i1 ) (start time of v i2 ) if b i1,i2 =1 and (end-time of v i2 ) (start time of v i1 ) if b i1,i2 =0 Ensure that the schedule for executing operations is consistent with the precedence constraints in the task graph. Timing constraints need to be met

78 Example HW types H1, H2 and H3 with costs of 20, 25, and 30. Processors of type P. Tasks T1 to T5. Execution times: T H1 H2 H3 P

79 Operation assignment constraint T H1 H2 H3 P i I 1 : X i, k Yi, k k KH k KP X 1,1 +Y 1,1 =1 (task 1 mapped to H1 or to P) X 2,2 +Y 2,1 =1 X 3,3 +Y 3,1 =1 X 4,3 +Y 4,1 =1 X 5,1 +Y 5,1 =1

80 Operation assignment constraint Assume types of tasks are l =1, 2, 3, 3, and 1. l L, i:t(v i )=c l, k KP: NY l,k Y i,k Functionality 3 to be implemented on processor if node 4 is mapped to it.

81 Other equations Time constraint: Application specific hardware required for time constraints under 100 time units. T H1 H2 H3 P Cost function: C=20 #(H1) + 25 #(H2) + 30 # (H3) + cost(processor) + cost(memory)

82 Result For a time constraint of 100 time units and cost(p)<cost(h3): T H1 H2 H3 P Solution: T1 H1 T2 H2 T3 P T4 P T5 H1

83 Separation of scheduling and partitioning Combined scheduling/partitioning very complex; Heuristic: Compute estimated schedule Perform partitioning for estimated schedule Perform final scheduling If final schedule does not meet time constraint, go to 1 using a reduced overall timing constraint. Actual execution time t t specification approx. execution time Actual execution time New specification approx. execution time 1 st Iteration 2 nd Iteration

84 Summary HW/SW codesign is complicated and limited by performance estimates Algorithms are in research and development, much of the work is still done by expert designers

85 Sources and References Peter Marwedel, Embedded Systems Design, Giovanni De EPFL Vincent Gatech Nikil UCI

86 CMOS VLSI Trends Yesterday (1980s) memory processors gate arrays ASICs Today memory processors SoC reconfigurable struc. ASIC ASICs Tomorrow memory processors platform SoC struc. SoC custom SoC reconfigurable (no processor) struc. ASIC (no processor) ASICs

87 Increasing Customization Cost Example: Design with 80 M transistors in 100 nm technology Estimated Cost - $85 M -$90 M Top cost drivers Verification (40%) Architecture Design (26%) Embedded Design 1400 man months (SW) 1150 man months (HW) HW/SW integration months s, How to Slow the Design Cost Spiral, Electronics Design Chain, September 2002, www

88 Responses to Increasing Cost General purpose ISA Universality high volumes and reuse Abstraction compilation technologies and high application/development productivity Custom silicon for embedded platforms in sufficiently high volumes Domain specific ISAs, e.g., DSPs Application Specific Standard Products Reconfigurable hardware HW/SW Codesign

89 HW/SW Codesign Issues Task level concurrency management Which tasks in the final system? High level transformations Transformation outside the scope of traditional compilers Hardware/software partitioning Which operation mapped to hardware, which to software? Compilation Hardware-aware compilation Scheduling Performed several times, with varying precision Design space exploration Set of possible designs, not just one.

90 Partitioning Analysis Result of compilation is synthesizable HDL and assembly code for the processor Compiler & profiler determine dependence and rough performance estimates

91 HW & SW Foundries HW1 LSI Logic ASIC Wafer Foundry Data 0.18 mm feature size 8 inch wafers 6 layers TSMC 018 Wafer Processing HW2 Samsung Semiconductor ASIC Wafer Foundry Data 0.35 mm feature size 6 inch wafers 4 layers TSMC 035 Wafer Processing SW1 Nominal to High development effort SW2 Low to Nominal development effort

92 1000, No 1000, 20% 1000, 40% 10000, No 10000, 20% 10000, 40% , No , 20% , 40% Recurring Percent of Total Cost MIXED Implementation Using HW1 and SW1 100% Software development Testing 80% 60% 40% 20% Packaging Fabrication Tooling Design Reuse of: Gate-level IP Code 0% Production Quantity and Level of Reuse

93 Total Cost ($/chip) Total Cost Per Chip ,000 Units HW1/SW1 HW1/SW2 HW2/SW1 HW2/SW Percent Custom Hardware

94 Co-simulation for HW & SW Transistor-level accurate post layout SPICE model Gate-level accurate precise HDL gate delay model Cycle accurate correct transitions at clock edges timing information between edges is thrown away Bus accurate cycle accurate bus model behavioral model of processor, hardware Instruction set accurate instruction set simulator used for processors used for early design space exploration