Design of Reconfigurable Multiprocessor Architecture for Embedded System

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1 Internatinal Jurnal f Cmputer Applicatins ( ) Natinal Cnference n Recent Trends in Infrmatin Security (NCRTIS-2015) Design f Recnfigurable Multiprcessr Architecture fr Embedded System Archana Gmkar Ph.D. Schlar, Singhania University, Pacheri Bari ABSTRACT Embedded systems are the brains f tday s mst digital and industrial cntrl systems. In systems where mre than ne prcessr is incrprated, the need fr multiprcessr cmmunicatin ften arises. It fully utilizes micrcntrller features & embedded technlgy cncepts t minimize the cmplicatins f digital gates, size and cst t. Keywrds Multiprcessr Cmmunicatin, Prtcls, SPI, CAN, Interfacing Peripherals, Embedded System, Distributed Cmputing. 1. INTRODUCTION 1.1 Multiprcessing Multiprcessing, as generally defined, is the use f tw r mre central prcessing units (CPUs) within a single cmputer system. The term als refers t the ability f a system t supprt mre than ne prcessr and/r the ability t allcate tasks between them. There are many variatins n this basic theme, and the definitin f multiprcessing can vary with cntext, mstly as a functin f hw CPUs are defined. In present prject Multi prcessing refers t use f multiple peripheral devices. 1.2 Cmmunicatin Prtcl A cmmunicatins prtcl is the set f standard rules fr data representatin, signalling, authenticatin and errr detectin required t send infrmatin ver a cmmunicatins channel. An example f a simple cmmunicatins prtcl adapted t vice cmmunicatin is the case f a radi dispatcher talking t mbile statins. The cmmunicatin prtcls fr digital cmputer netwrk cmmunicatin have many features intended t ensure reliable interchange f data ver an imperfect cmmunicatin channel. Cmmunicatin prtcl is basically fllwing certain rules s that the system wrks prperly. Prblem statement: Micrcntrllers are versatile integrated circuits typically incrprating a micrprcessr, memry, and I/O prts n a single chip. These self-cntained units are central t embedded systems design where lw-cst, dedicated prcessrs are ften preferred ver general-purpse prcessrs. Sme embedded designs may incrprate several micrcntrllers, each with a specific task. Efficient cmmunicatin is central t such systems. Exchanging data in a system cmprising multiple micrcntrllers. Since each micrcntrller cntains a separate memry, a message passing system is designed. The hardware cnsists f lw-cst micrcntrllers serving as cmputing ndes and a netwrk cntrller t direct messages amng them. 2. BACKGROUND OVERVIEW We are aware f the fact that 40 pin micrcntrller prvide nly 4 prts fr external wrld. But fr ur cmplex requirement we need t interface a large number f peripheral devices which is nt pssible with a single micrcntrller. The limitatin f using single Cntrller is Limited cde memry. A very few peripheral devices can be interfaced. Cmplexity in design. Time cnsuming. Errr prbability. Sftware cmplexity mre. Debugging is difficult. 2.1 Existing System The slutin f abve defined Prblem is t use mre than ne cntrllers r multi cntrllers in a single prject. Nw cmmunicatin in different cntrllers can be dne mainly by tw ways i.e. by using I2C prtcl and SPI prtcl. 2.2 Drawbacks f Existing System Synchrnizatin f the clck is required. Data is transferred serially hence the system becmes slw. Master slave cnfiguratin is strictly maintained. Slaves cannt transfer data directly amng each ther As data transfer has t take place thrugh master itself. 2.3 Prpsed System We had used 8-bit parallel data lines t transfer the data and 3 bit parallel line fr handshaking signal. There will be n master Slave cnfiguratin. Each cntrller can cmmunicate r transfer data independently. Pririties can be set by the cntrllers IDs. We had develped that algrithm by which Up t 255 micrcntrllers can transfer their data t desire destinatin micrcntrller independently. Data transfer here means that any micrcntrller can get data frm any cntrller but with its permissin. Similarly any micrcntrller can send data frm itself t any destinatin cntrller. 14

2 Internatinal Jurnal f Cmputer Applicatins ( ) Natinal Cnference n Recent Trends in Infrmatin Security (NCRTIS-2015) The clck frequencies f these cntrllers can may r may nt be same but the prtcl will wrk efficiently. The same prgram will be burn in all the cntrllers withut any mdificatin. Additin and remval f any cntrller will nt affect the prtcl. 3. THE PROPOSED SYSTEM Micrcntrllers are versatile integrated circuits typically incrprating a micrprcessr, memry, and I/O prts n a single chip. These self-cntained units are central t embedded systems design where lw-cst, dedicated prcessrs are ften preferred ver general-purpse prcessrs. Sme embedded designs may incrprate several micrcntrllers, each with a specific task. Efficient cmmunicatin is central t such systems. Nw days, embedded systems are everywhere. Tday they have crssed the bundary f nly industrial use. They are becming mre and mre cmplex t simplify ur lifestyle. Many features are being embedded in a single tiny system t fulfill ur everyday requirements. Thus mre & mre peripheral needs t be integrated in the single embedded system. This increases the design time f the system and als the prcessing lad is increased fr a single micrprcessr. This arises the need f such an arrangement f peripherals which can be interfaced in a netwrk instead f directly interfacing with the prcessing unit. This type f arrangement f peripherals will create a distributed interface f multiple peripherals. Distributed systems require prtcls fr cmmunicatin between micrcntrllers. Currently Serial Peripheral Interfaces (SPI) and Inter-Integrated Circuit (I2C) are tw f the mst cmmnly used such prtcls. Bth f them wrk as serial cmmunicatin link between the micrcntrllers. Here, in this thesis, a new methd fr cmmunicatin is prpsed fr an embedded system having multiple peripherals n the bard. The adapted arrangement is parallel and hence is mre faster way t cmmunicate. The fcus f this thesis is the design f a cmmunicatin layer and applicatin prgramming interface fr exchanging data in a system cmprising multiple micrcntrllers. Since each micrcntrller cntains a separate memry, a message passing system is designed. The hardware cnsists f lw-cst micrcntrllers serving as cmputing ndes and a netwrk cntrller t direct messages amng them. 3.1 Embedded System An embedded system is an electrnic/electr-mechanical system designed t perfrm a specific functin and is a cmbinatin f bth hardware and firmware (sftware). An embedded system is a cmputer system with a dedicated functin within a larger mechanical r electrical system, ften with real-time cmputing cnstraints. It is embedded as part f a cmplete device ften including hardware and mechanical parts. Embedded systems cntrl many devices in cmmn use tday. Mdern embedded systems are ften based n micrcntrllers (i.e. CPUs with integrated memry r peripheral interfaces) but rdinary micrprcessrs (using external chips fr memry and peripheral interface circuits) are als still cmmn, especially in mre cmplex systems. The key characteristic, hwever, is being dedicated t handle a particular task. Since the embedded system is dedicated t specific tasks. A general-purpse definitin f embedded systems is that they are devices used t cntrl, mnitr r assist the peratin f equipment, machinery r plant. Embedded reflects the fact that they are an integral part f the system. 4. NEED FOR PROPOSED SYSTEM Micrcntrllers are versatile integrated circuits typically incrprating a micrprcessr, memry, and I/O prts n a single chip. These self-cntained units are central t embedded systems design where lw-cst, dedicated prcessrs are ften preferred ver general-purpse prcessrs. Sme embedded designs may incrprate several micrcntrllers, each with a specific task. Efficient cmmunicatin is central t such systems. The fcus f this thesis is the design f a cmmunicatin layer and applicatin prgramming interface fr exchanging data in a system cmprising multiple micrcntrllers. Since each micrcntrller cntains a separate memry, a message passing system is designed. The hardware cnsists f lw-cst micrcntrllers serving as cmputing ndes and a netwrk cntrller t direct messages amng them. Cnsidering a case where the embedded system requirements are as fllws The system will be used fr SCADA purpse It must have multiple input fr varius sensrs It must display all the sensr infrmatin n LCD It must sent the sensr data t remte PC It must have a keypad fr sme user input It must have relays fr activating-deactivating actuatrs Als it must have prvisin fr adding mre features t it withut disturbing the riginal design like It can be upgraded fr strage device t stre the recrd It can be upgraded fr DAC t be used fr analg utput 15

3 Internatinal Jurnal f Cmputer Applicatins ( ) Natinal Cnference n Recent Trends in Infrmatin Security (NCRTIS-2015) It can be upgraded fr DC as well as stepper mtr cntrlling als. Etc. All the abve are a general verview that an embedded system may have. Our aim is t design such a flexible, recnfigurable, upgradable, distributed prcessing system; that can adapt any changes whenever required 5. EVALUATION OF COMMUNICATION OPTIONS The Atmel micrcntrllers cme with a small selectin f built in cmmunicatin ptins. In rder t select the best intercnnect, each f these ptins was evaluated against implementing an alternative cmmunicatin prtcl. The criteria fr evaluatin were scalability, number f pins required, and thrughput. The first ptin available n the Atmel chips is the serial peripheral interface (SPI). This interface requires at least fur cnductrs, prvides full duplex peratin and is synchrnus. SPI defines ne nde as a master and the ther ndes as slaves. Tw wires prvide the send and receive lines. The master is respnsible fr generating the clck signal n a dedicated line and sending a signal t a slave n its select line, thus initiating cmmunicatin. The clck frequency is limited t the main scillatr frequency divided by 4, r 16 MHz / 4 = 4 MHz. One bit can be sampled per SPI clck perid, thus allwing a maximum thrughput f 4 Mbits/sec / (8 bits/byte) = 500 KB/sec. Fr cnnecting tw micrcntrllers, SPI seems t be a gd chice. It prvides high thrughput and uses few prt pins. Since this is a byte-riented prtcl, thugh, there wuld need t be at least ne byte f verhead fr lgical addressing. This wuld effectively halve the transfer rate. Als, the scheme des nt scale well. Since there can be nly ne master, micrcntrllers must take turns initiating cmmunicatin. This can be implemented using a tken passing scheme, but this adds an extra line t infrm the next prcessr it can be the master. Als, as the number f micrcntrllers grws, the number f slave select lines increases per chip. An arbiter might be an alternative, but the bandwidth is still divided amng all micrcntrllers, making it a pr chice fr large netwrks. The next ptin is the universal synchrnus and asynchrnus serial receiver and transmitter (USART). This is a full duplex device with allws bth asynchrnus and synchrnus cmmunicatin. Data can be sized frm 5 t 9 bits in length. The transmissin rate can be adjusted frm 2400 bits/sec up t 2 Mbits/sec. Since frames require a start and stp bit, the maximum thrughput is 200 KB/sec. Additinally, in multiprcessr cmmunicatin mde, an address frame must be sent at the start f a transmissin. As was the case with SPI, this requirement halves the transmissin rate. If variable messages were allwed at the link layer, this wuld nt have as much f a negative impact, hwever. Still, the scalability prblems that preclude the use f SPI apply t the USART a well. The final hardware ptin prvided by the micrcntrllers is the tw-wire serial interface (TWI), which is cmpatible with the industry standard I2C interface. TWI prvides built in addressing and arbitratin fr systems with multiple masters. The clck signal is generated by the master initiating cmmunicatin and can reach frequencies up t 400 khz. Address packets are part f the TWI prtcl, as are variable length messages. Hwever, in rder t supprt arbitratin, all masters must use packets f the same length. In a byteriented netwrk, the verhead f 9-bit address and data packets effectively gives a maximum thrughput f 400 kbits/sec / (18 bits/byte) = 22.2 KB/sec. Due t the arbitratin built int the prtcl, a separate arbiter is unnecessary. Hwever, with many masters perating n the same bus, cntentin wuld becme prhibitive and the thrughput wuld be reduced cnsiderably. Since the abve methds all have significant drawbacks, alternative netwrk designs were implemented and evaluate in all three shared-bus interfaces discussed abve, serial transmissin reduces the thrughput cnsiderably. Thus, the first attempt at new netwrk architecture uses a parallel bus t address this prblem. Als, since cperative arbitratin can be slw and may indefinitely prevent a prcessr frm gaining the medium, a hardware arbitratin unit with a fairness guarantee is used when transmissin privileges ver a link are cntested. The first versin f the netwrk architecture utilizes a 4-wire shared bus t transfer a nibble (4-bit chunk) f data at a time. Fur additinal cntrl wires are used per nde t cmmunicate transmissin requests and acknwledgements between each nde and the bus cntrller. Fr the sftware side f the prject: The interface must allw variable length messages t be transmitted between micrcntrllers. The system must prvide a lgical addressing scheme. The interface shuld be easy t utilize in applicatins. The implementatin shuld fit int the limited amunt f n-chip memry and allw enugh free memry t implement client applicatins. The implementatin must prvide a gd balance between I/O and cmputatin. Additinally, the number f wires needed fr all cmmunicatin links is cnstrained by the number f pins n a single micrcntrller. Ideally, prt pin usage shuld be as lw as pssible (preferably, 1 I/O prt) t allw the micrcntrllers t have enugh I/O resurces t interface with external system cmpnents. These cnstraints will in part determine the netwrk tplgy that will be implemented using the micrcntrllers. The physical layer supprts the electrical r mechanical interface t the physical medium. The physical layer is aimed at cnslidating the hardware requirements f a netwrk t enable the successful transmissin f data. Netwrk engineers can define different bit-transmissin mechanisms fr the physical layer level, including the shapes and types f cnnectrs, cables, and frequencies fr each physical medium. The physical layer smetimes plays an imprtant rle in the effective sharing f available cmmunicatin resurces, and helps avid cntentin amng multiple users. It als handles the transmissin rate t imprve the flw f data between a sender and receiver. First, distributed-memry machines exhibit high perfrmance when a task is divided s that each prcessr can fit its wrking set int the lcal subset f main memry. Sharedmemry machines d nt suffer frm this since all main 16

4 Internatinal Jurnal f Cmputer Applicatins ( ) Natinal Cnference n Recent Trends in Infrmatin Security (NCRTIS-2015) memry accesses are equal. Hwever, since distributed memry machines d nt need t share the bus when wrking with lcal memry, the ptential perfrmance imprvement ver SMP systems is prprtinal t the number f separate memries. Secnd, withut a shared memry address space, ndes in a cluster must use intercnnect t explicitly send and receive messages instead f reading and writing a shared variable. This message-passing latency can be relatively lng cmpared t the cmmunicatin latency in tightly integrated systems. Thus it is imprtant t ptimize bth hardware cmmunicatin efficiency and sftware cmmunicatin verhead. The physical layer supprts the electrical r mechanical interface t the physical medium. The physical layer is aimed at cnslidating the hardware requirements f a netwrk t enable the successful transmissin f data. Netwrk engineers can define different bit-transmissin mechanisms fr the physical layer level, including the shapes and types f cnnectrs, cables, and frequencies fr each physical medium. The physical layer smetimes plays an imprtant rle in the effective sharing f available cmmunicatin resurces, and helps avid cntentin amng multiple users. It als handles the transmissin rate t imprve the flw f data between a sender and receiver. The physical layer prvides the fllwing services: Mdulates the prcess f cnverting a signal frm ne frm t anther s that it can be physically transmitted ver a cmmunicatin channel Bit-by-bit delivery Line cding, which allws data t be sent by hardware devices that are ptimized fr digital cmmunicatins that may have discreet timing n the transmissin link Bit synchrnizatin fr synchrnus serial cmmunicatins Start-Stp signalling and flw cntrl in asynchrnus serial cmmunicatin Circuit switching and multiplexing hardware cntrl f multiplexed digital signals Carrier sensing and cllisin detectin, whereby the physical layer detects carrier availability and avids the cngestin prblems caused by undeliverable packets Signal equalizatin t ensure reliable cnnectins and facilitate multiplexing Frward errr crrectin/channel cding such as errr crrectin cde Bit interleaving t imprve errr crrectin Aut-negtiatin Transmissin mde cntrl Examples f prtcls that use physical layers include: Digital Subscriber Line Integrated Services Digital Netwrk Infrared Data Assciatin Universal Serial Bus Bluetth Cntrller Area Netwrk Ethernet 6. CONCLUSIONS We had used 8-bit parallel data lines t transfer the data and 3 bit parallel line fr handshaking signal. There will be n master Slave cnfiguratin. Each cntrller can cmmunicate r transfer data independently. Pririties can be set by the cntrllers IDs... We had develped that algrithm by which Up t 255 micrcntrllers can transfer their data t desire destinatin micrcntrller independently. Data transfer here means that any micrcntrller can get data frm any cntrller but with its permissin. Similarly any micrcntrller can send data frm itself t any destinatin cntrller. The clck frequencies f these cntrllers can may r may nt be same but the prtcl will wrk efficiently. The same prgram will be burn in all the cntrllers withut any mdificatin. Additin and remval f any cntrller will nt affect the prtcl. 7. REFERENCES [1] Atmel ATmega32 and ATmega16 Datasheets. Rev. 2503H-03/05. Accessed March [2] aos a RTOS fr AVR. Accessed March [3] The Message Passing Interface (MPI) Standard. Accessed March [4] MPI-2: Extensins t the Message-Passing Interface. Accessed March 2006.< [5] Hennessy, Jhn L. and Pattersn, David A. Cmputer Architecture: A Quantitative Apprach, 3rd ed. Mrgan Kaufmann [6] Petersn, Larry L. and Davie, Bruce S. Cmputer Netwrks: A Systems Apprach, 3rd ed. Mrgan Kaufmann [7] A preemptive multitasking, OS fr Atmel Mega32 micrcntrllers. Accessed March x.html [8] Benny Akessn. Predictable and Cmpsable System-n- Chip Memry Cntrllers. PhD thesis, Eindhven University f Technlgy, February ISBN: [9] Benny Akessn, Kees Gssens, and Markus Ringhfer. Predatr: A Predictable SDRAM Memry Cntrller. In 17

5 Internatinal Jurnal f Cmputer Applicatins ( ) Natinal Cnference n Recent Trends in Infrmatin Security (NCRTIS-2015) Int'l Cnference n Hardware/Sftware Cdesign and System Syn-thesis (CODES+ISSS), pages 251{256. ACM Press New Yrk, NY, USA, September [10] G. Cte, B. Erl, M. Gallant, and F. Kssentini. H.263+: vide cding at lw bit rates.circuits and Systems fr Vide Technlgy, IEEE Transactins n, 8(7):849 {866, nv [11] Bernd Gird. Digital images and human visin. chapter What's wrng with mean-squared errr?, pages 207{220. MIT Press, Cambridge, MA, USA, [12] K. Gssens, J. Dielissen, and A. Radulescu. Aethereal netwrk n chip: cncepts, archi-tectures, and implementatins. Design Test f Cmputers, IEEE, 22(5): , sept.-ct [13] K. Gssens and A. Hanssn. The ethereal netwrk n chip after ten years: Gals, evlutin, lessns, and future. In Design Autmatin Cnference (DAC), th ACM/IEEE, pages , june

It has hardware. It has application software.

It has hardware. It has application software. Q.1 What is System? Explain with an example A system is an arrangement in which all its unit assemble wrk tgether accrding t a set f rules. It can als be defined as a way f wrking, rganizing r ding ne