SiP/3D Device Test Challenges using Ever Changing JTAG Standards

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2 Presentation Outline Overview of Current Standards Standards in SiP/3D Test Perspective Overview of SiP/3D Test Challenges Disturbing Thought / New Development Presentation Summary Q and A Selective References Page Hanyang University ERICA, All rights reserved

3 Presentation Outline Overview of Current Standards Standards in SiP/3D Test Perspective Overview of SiP/3D Test Challenges Disturbing Thought / New Development Presentation Summary Q and A Selective References Page Hanyang University ERICA, All rights reserved

The Beginning 1 st JTAG Meeting, 17 Sep.

5 IEEE Std The Original JTAG Test Access Port and Boundary-Scan Architecture Called Joint Test Action Group (JTAG) Referred to as DCJTAG to distinguish from ACJTAG (1149.6) : 1st release a-1993: added Boundary Scan Description Language (BSDL) b-1994: 1 st major clean up and clarification c-2001: add provisions for DFT circuit Active Standard Add provisions for dynamic test capabilities with new instructions and BSDL files P Active Working Group It is called TDRI or JTDRI IEEE P Page Hanyang University ERICA, All rights reserved

6 IEEE Std New to IEEE New IC level Instructions Three Instructions for initializing programmable IP connected to I/O pins INIT_SETUP INIT_SETUP_CLAMP INIT_RUN Standardized on-chip per domain system reset IC_RESET Unique per die identifier ECIDCODE Standardizes a method to hold and isolate I/O pins during in-situ test of an IC CLAMP_HOLD CLAMP_RELEASE TMP_STATUS Other updates No more BC_6 Support excludable register segments All (except TAP) pins may have additional observe-only cells Defined interface for design-specific TDR Power domain control Page Hanyang University ERICA, All rights reserved

IEEE Std 1149.4 IEEE Std 1149.6 1149.2: Withdrawn Extended Digital Serial Test Bus Subset Withdrawn during 1997, became part of 1149.1 1149.3: Withdrawn System Test Bus Withdrawn known Std. 1149.4-1999 AJTAG (Analog JTAG) Mixed Signal Test Bus 1999 standard superseded by 2010 1149.

7 IEEE Std IEEE Std : Withdrawn Extended Digital Serial Test Bus Subset Withdrawn during 1997, became part of : Withdrawn System Test Bus Withdrawn known Std AJTAG (Analog JTAG) Mixed Signal Test Bus 1999 standard superseded by Active Standard Jari Hannu et al., Current State of the Mixed-Signal Test Bus , J. of Electron Test (2012) 28: , DOI /s : Module Test and MTM Protocol VME backplane and system and it s a withdrawn, inactive standard Std ACJTAG (AC JTAG) Advanced I/O digital network test, known as ACJTAG Voltage-current measurement method principle with variable sense resistor IEEE Std Page Hanyang University ERICA, All rights reserved

8 IEEE Std cjtag Std cjtag (Compact JTAG) (or ajtag) Reduced-pin and Enhanced-functionality Test Access Port and Boundary Scan Architecture Purpose: cjtag is compatible with IEEE Std to provide an enhanced test and debug standard that meets the demands of modern systems. One unique feature is the reduced pin count interface for the TAP; it uses a two-wire interface, since it is compatible with , it also permits four- or five-wire implementation as well. Benefits. cjtag enables easier implementation of JTAG for SoC, SiP and PoP. It supports multi-die SiPs or PoPs and a star configuration of TAP. A key advantage is that it can be implemented on TSV to link each die through a via that connects the interface on each die to one another. IEEE Std TAP Capability Classes Page Hanyang University ERICA, All rights reserved

9 IEEE Std A Toggle Std : TJTAG (A Toggle JTAG) Boundary-Scan-Based Stimulus of Interconnections to Passive and/or Active Components Purpose: To regain test coverage on connectors and devices connected to boundary scan devices without the need for test points, uses a combination of boundary scan devices as signal driver and a noncontact signal sensing or vectorless sensor plate controlled by ICT to detect opens and shorts on connectors, sockets and semiconductor device pins. Benefit: There is already a working solution currently implemented in some ICTs using a noncontact signal sensing or vectorless sensor plate that detects open/shorted pins on nonboundary scan devices and connectors connected to boundary scan devices. Page Hanyang University ERICA, All rights reserved

10 IEEE Std 1450 STIL Std STIL Standard Test Interface Language (STIL) STIL is a common test data description language that can be used in various environments of semiconductor testing such as design, simulation, ATE testing and failure analysis Semicon Design Environ DC Level Spec Target Tester Spec P Test Flow Spec P Dropped, plan to restart after P Core Test Language P CTL for Memory Model P CTL for Scan Compression P Analog Mixed Signal P Design Information IEEE Std IEEE Std IEEE Std IEEE Std IEEE P IEEE P IEEE P IEEE P IEEE P IEEE P Page Hanyang University ERICA, All rights reserved

architecture. It also uses a core test language (CTL, IEEE Std. 1450.6-2005) to facilitate communication between core designers and integrators.

11 IEEE Std 1500 Core Test Std Embedded Core Test Photo Courtesy of Mentor Graphics Defines a mechanism for the test of cores within a system on chip, including a wrapper hardware architecture. It also uses a core test language (CTL, IEEE Std ) to facilitate communication between core designers and integrators. Defines standard components and general wrapper architecture, including wrapper parallel input and output ports, core functional inputs and outputs, wrapper serial input, and serial output for test Source: ASSET InterTech, Inc. All rights reserved Page Hanyang University ERICA, All rights reserved

12 IEEE Std 1532 ISC Std ISC In-System Configuration of Programmable Devices Superseded Superseded Active The IEEE Std was adopted in 2000 and updated in 2001 and 2002 to include a programming data file format and a method for implementing adaptive programming algorithms. Page Hanyang University ERICA, All rights reserved

13 IEEE Std 1581 mjtag Std mjtag (Memory) Static Component Interconnection Test Protocol and Architecture Purpose: Low-cost method for testing the interconnection of discrete, complex memory ICs where additional pins for testing are not available and JTAG is not feasible. Benefit: Improve interconnect test for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs. Limited to behavioral description of implementation, does not include the technical design of the test logic or test mode control circuitry Simple test logic implementation for memory devices (and possibly other complex, slave-type components) No extra pins are required Not relying on complex memory access cycles Fast test execution, small test vector set Usable with any access methodology (JTAG, functional, ICT) Page Hanyang University ERICA, All rights reserved

IEEE P1687 ijtag P1687 ijtag (Instrument): in vallot process.. Standard methodology for access to embedded test and debug features through IEEE Std. 1149.

Integrated into existing ICT 2. ICT system > P1687 test solution 3. P1687 test solution > functional test 4.

14 IEEE P1687 ijtag P1687 ijtag (Instrument): in vallot process.. Standard methodology for access to embedded test and debug features through IEEE Std This Standard provides a method of adding additional lines and functionality to the JTAG TAP to enable far greater levels of internal testing to be achieved using internal instrumentation 1. Integrated into existing ICT 2. ICT system > P1687 test solution 3. P1687 test solution > functional test 4. Integrated into existing functional test Key Differences between JTAG and ijtag Control of internal IP External interface to internal instrument and 3 rd -party IP JTAG Ad hoc method, vendor specific Need information from instrument vendor ijtag Standard protocol Plug-and-play and vendor independent Coolness Old and boring Fancy and New Instrument access through hierarchical logic structure Must be manually defined of the JTAG interface Register size Fixed per instruction Flexible Automated retargeting from TAP to instrument through logic hierarchy Page Hanyang University ERICA, All rights reserved

Analysis of IEEE P1687 network Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar

Symposium (ATS 2010), Shanghai, China, Dec.

Control data is transferred to the status register when the JTAG state machine does

15 Analysis of IEEE P1687 network Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson and Erik Larsson, Test Time Analysis for IEEE P1687, IEEE 19th Asian Test Symposium (ATS 2010), Shanghai, China, Dec The control data for the SIB is transported on the same wire as test data Control data is transferred to the status register when the JTAG state machine does apply and capture CUC : Apply Capture Update Cycle: 5 clock cycles in the FSM Page Hanyang University ERICA, All rights reserved

IEEE P1838 3D Test P1838 3D Device Test & DFT Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits Scope: The proposed standard is a die-centric

Test Wrapper hardware per die Description + description language Leverage existing DFT wherever Applicable/Appropriate Test access ports: utilize IEEE Std. 1149.

16 IEEE P1838 3D Test P1838 3D Device Test & DFT Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits Scope: The proposed standard is a die-centric standard; it applies to a die that is pre-destined to be part of a multi-die stack and such a die can be compliant (or not compliant) to the standard Two Standardized Components 3D Test Wrapper hardware per die Description + description language Leverage existing DFT wherever Applicable/Appropriate Test access ports: utilize IEEE Std x On-die design-for-test: utilize IEEE Std On-die design-for-debug: Utilize IEEE P1687 Web Page Page Hanyang University ERICA, All rights reserved

SJTAG Another JTAG. SJTAG (System JTAG) http://www.dft.co.

(single board) interconnect test In-system programming System interconnect test using chain configuration devices (bridges, scan

17 SJTAG Another JTAG. SJTAG (System JTAG) SJTAG deals with JTAG architectures and operations in a multi-board environment Typical SJTAG operations: Conventional (single board) interconnect test In-system programming System interconnect test using chain configuration devices (bridges, scan routers/multiplexors) Simple ijtag operations (single board, no hierarchy) Complex ijtag operations (through system and device hierarchies) Page Hanyang University ERICA, All rights reserved

18 IEEE-ISTO 5001 Debug Standards IEEE-ISTO 5001 TM Forum The Nexus standard defines classes of standard on chip features, auxiliary pins, transfer protocol, connectors and API for communication between an embedded instrumentation and a host computer Nexus 5001 IEEE-ISTO 5001 TM = IEEE-ISTO 5001 IEEE-ISTO 5001 TM Superseded IEEE-ISTO 5001 TM Active Spec Updates are ongoing SerDes IO for debug Aurora protocol Convergence with IEEE Std cjtag and P1867 ijtag Page Hanyang University ERICA, All rights reserved

EJTAG MIPS Debug MIPS EJTAG EJTAG (Extended JTAG) is a hardware/software subsystem that provides comprehensive debugging and performance tuning capabilities to MIPS microprocessors and to

19 EJTAG MIPS Debug MIPS EJTAG EJTAG (Extended JTAG) is a hardware/software subsystem that provides comprehensive debugging and performance tuning capabilities to MIPS microprocessors and to system-on-a-chip components having MIPS processor cores. The MIPS architecture has historically provided a set of primitives for debugging software, which includes A breakpoint instruction A set of trap instructions Dual optional watch registers An optional TLB-based MMU Source: MIPS Technologies, Inc. All rights reserved Page Hanyang University ERICA, All rights reserved

20 Presentation Outline Overview of Current Standards Standards in SiP/3D Test Perspective Overview of SiP/3D Test Challenges Disturbing Thought / New Development Presentation Summary Q and A Selective References Page Hanyang University ERICA, All rights reserved

21 Relationship between All Standards P1838 uses the largest number of standards to solve 3D test challenges Nexus 5001 IEEE IEEE P1687 IEEE P1838 SJTAG IEEE 1532 IEEE IEEE 1500 IEEE 1581 EJTAG Page Hanyang University ERICA, All rights reserved

My Best Picks for SiP/3D IC Test Work in progress SJTAG IEEE P1149.1.1 IEEE P1450.4 IEEE P1450.5 IEEE P1450.6-1 IEEE P1450.6-2 IEEE P1450.

22 My Best Picks for SiP/3D IC Test Work in progress SJTAG IEEE P IEEE P IEEE P IEEE P IEEE P IEEE P IEEE P IEEE P1687 IEEE Std 1581 IEEE P1838 Active Standards IEEE Std IEEE Std IEEE Std IEEE Std IEEE Std IEEE Std 1450 IEEE Std 1500 IEEE Std 1532 For SiP and 3D Test Most likely to be used Less likely to be used Active Standards IEEE Std IEEE Std IEEE Std IEEE Std EJTAG IEEE-ISTO 5001 Nexus 5001 Page Hanyang University ERICA, All rights reserved =

23 Presentation Outline Overview of Current Standards Standards in SiP/3D Test Perspective Overview of SiP/3D Test Challenges Disturbing Thought / New Development Presentation Summary Q and A Selective References Page Hanyang University ERICA, All rights reserved

Test Delivery and DFT Hierarchy Core-level DFT BIST, scan chain, scan data compression Die-level DFT Wrapper and test-access mechanism (TAM) SIC- level DFT Wrapper at

24 Test Delivery and DFT Hierarchy Core-level DFT BIST, scan chain, scan data compression Die-level DFT Wrapper and test-access mechanism (TAM) SIC- level DFT Wrapper at die boundary KGD: extra probe pads KGS: Known Good Stack Test Elevators Signal Switches Board-level DFT (JTAG) Page Hanyang University ERICA, All rights reserved

25 Test is Considered 3D Challenge No. 1 3D Testing Testing at individual die level Determine Known Good Die (KGD) for stacking Testing at 3D stack level Final stack test Individual die test options No Test Built-In-Self-Test (BIST) and Built-Out-Self-Test (BOST) Reduced-Pad-Count-Test (RPCT) 3D Testing assumptions Final, Post-stacking Test performed in ALL cases Test Bottom die Avoid stacking cost if die is faulty Scan chains in place on all stacked dice To be utilized in the Final, Post-stacking Test New issues and requirements IP and Test Security Near-field wireless communication Page Hanyang University ERICA, All rights reserved

Testing Differences Defect Mode Adopted from Wendy Chen, 3DS IC Test Cost Reduction Challenges Items SoC POP/PIP SIP 3D SIC 3D IC Functional Test DFT / BIST EDA Data

26 Testing Differences Defect Mode Adopted from Wendy Chen, 3DS IC Test Cost Reduction Challenges Items SoC POP/PIP SIP 3D SIC 3D IC Functional Test DFT / BIST EDA Data Mining Probe Access Point Wafer Handling KDG / PGD Burn In Supply Chain Don t Need Portion Same Enhance New Page Hanyang University ERICA, All rights reserved

Example 3D Test DFT Trends 1149.1, 1149.4, 1149.6, 1149.7 1149.8.

At-Speed Test Debug, Diagnosis, ICE Stephen Sunter, Mixed-signal testing, DFT, and BIST: Trends and

27 Example 3D Test DFT Trends , , , , 1500, 1581 P1687, P1838 Analog test bus, Loopback Parametric Test BIST and BOST Functional Test, At-Speed Test Debug, Diagnosis, ICE Stephen Sunter, Mixed-signal testing, DFT, and BIST: Trends and Principles, June 2010, Mentor Graphics Danger is to try to use all tricks even unapproved Standards Page Hanyang University ERICA, All rights reserved

28 Example Test Coverage Summary DFT and DFD are key for success Still some test issues unresolved Stéphane GUILHOT, DFT challenges and results for a 3D-IC including a WideIO memory, ST Ericsson Page Hanyang University ERICA, All rights reserved

29 Presentation Outline Overview of Current Standards Standards in SiP/3D Test Perspective Overview of SiP/3D Test Challenges Disturbing Thought / New Development Presentation Summary Q and A Selective References Page Hanyang University ERICA, All rights reserved

What about Non-Contact Probing Different Principles & Approaches Non contact coupling Capacitive / Inductive coupled high speed data communication Near field and Far field e.g., DFT Build-in transmitters with readout electronics in the probe card Laser direct testing But works only for passive networks Source: Marinissen et.

30 What about Non-Contact Probing Different Principles & Approaches Non contact coupling Capacitive / Inductive coupled high speed data communication Near field and Far field e.g., DFT Build-in transmitters with readout electronics in the probe card Laser direct testing But works only for passive networks Source: Marinissen et. al., DATE 09 Near field inductive coupling is the most powerful technique for stacked IC s Scalable solution from wafer, die, and to stack Can solve KGD, PGD and KGS BOST and other off-chip test and analysis support Contactless I/O Proximity I/O (Sun Micro Systems) and Scaimetrics: high-speed, low-power data communication (wireless test access port) Page Hanyang University ERICA, All rights reserved

31 Summary of Non Contact Data Communication Advantages of inductive near field coupling approaches Contactless & low chip to chip distances High interconnect RF and data speeds Many parallel links No probe force (except power) Low delay, area, power, higher speeds, more tolerant No ESD protection required Still High reliability (compared to the TSV challenges) Standard CMOS process less expensive then TSV process Limitations of inductive near field coupling approaches Dimensions of antenna >~200μm circumference Limited pitch e.g., 30μm with 20μm x 90μm antenna Controllable cross talk DC power must provided to DUT by additional electrical contact Thomas Thärigen, Stojan Kanev, 3D IC Test Challenges and Probing Concepts, DATE'10 Workshop on "3D Integration" Mar. 12, 2010, Dresden, Germany Page Hanyang University ERICA, All rights reserved

32 Presentation Outline Overview of Current Standards Standards in SiP/3D Test Perspective Overview of SiP/3D Test Challenges Disturbing Thought / New Development Presentation Summary Q and A Selective References Page Hanyang University ERICA, All rights reserved

33 Cartoon from Rich Rice, KGD and 2.5D & 3D IC Assembly - Building a Path to Success, ASE Group, Nov 15, 2012 Are you ready? Market gives Fair Test to Select The One to Survive! Page Hanyang University ERICA, All rights reserved

35 Selected References IEEEE 3D Test Working Group (3DF-WG) - Sematech WiKi 3D Standards - Kenneth P. Parker, 3D-IC Defect Investigation, provided report for the IEEE P1838 Defect Tiger Team, July 5, 2012 Tsutomu Takeya et al., A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines. IEEE Journal of Solid-state Circuit, Vol. 48, No. 3, Mar. 2013, pp Hsien-Hsin S. Lee and Krishnendu Chakrabarty, Test Challenges for 3D Integrated Circuits, IEEE Desgn & Test of Computer, Sep./Oct , vol. 26 no. 5, pp Nauman Khan, Soha Hassoun, Designing TSVs for 3D Integrated Circuits, Springer, ISBN , 2013 Sai-Wang Tam and Eran Socher, et al., RF-Interconnect for Future Network-On-Chip, Springer Low Power Networks-on-Chip, 2011, pp Chapter 9, IEEE P1687 IJTAG, N. Stollon, On-Chip Instrumentation: Design and Debug for Systems on Chip, 2011, DOI / _9, Springer Page Hanyang University ERICA, All rights reserved

New and Emerging JTAG Standards: Changing the Paradigm of Board Test (A tutorial)

New and Emerging JTAG Standards: Changing the Paradigm of Board Test (A tutorial) Artur Jutman November 23 th, 2010 Drammen, NORWAY Presentation Outline Introduction Overview of the standards IEEE 1149.7