8.3.4 The Four-Transistor (4-T) Cell

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1 전자회로 II 제 10 주 1 강

2 8.3.4 The Four-Transistor (4-T) Cell Static memory design has shorter access times than dynamic design 6-T static cell provides a to drive the sense amplifier Figure 8.19 : 4-T dynamic memory cell Compromised version between 6-T cell and 1-T cell The load devices are removed from the latch in the 6-T cell The information is stored on the capacitances 015 년 7 월 10 일

3 [8.3.4] The Four-Transistor (4-T) Cell (cont.) Figure 8.19 : 4-T cell (cont.) Automatic refreshing operation If BL, BL and word-line are all forced high MA1 and MA act as load device (Saturated load inverter..) The cell level is restored to original level 015 년 7 월 10 일

4 [8.3.4] Writing Data into the 4-T Memory Cell Figure 8.0 : Writing operation to 4-T cell Conditions Bit-lines are initialized with the data that is to be written into the cell Word-line is raised to V DD = 3V Access transistors M A1 and M A are turn-on Node D charges up to V DD V TN through M A1 (M N1 is OFF) Node D discharges to 0V through M A and M N 015 년 7 월 10 일

5 [8.3.4] Reading Data from the 4-T Memory Cell Figure 8.1 : Reading operation from 4-T cell Conditions Bit-lines are initialized with V DD / = 1.5V Initially M N1 is cut-off and M N is on Word-line is raised to V DD = 3V V BL Charge sharing occurs and is increasing V BL is decreasing through M A and M N Sense amplifier responds and drive the bit-lines to 0V and 3V 015 년 7 월 10 일

6 8.4 Sense Amplifiers The sense amplifier must do Detect the small currents that run through the access transistors of the memory cell (i 1, i ) Detect the small voltage difference ( V) that arises from charge sharing between bit-line capacitance and cell capacitance Rapidly amplify the bit-line signal up to full on-chip logic levels 015 년 7 월 10 일

7 8.4.1 A Sense Amplifier for the 6-T Cell Figure 8. : Memory array that includes a sense amplifier A basic sense amplifier consists of one latch and a pre-charge transistor M PC Main purpose of pre-charge transistor M PC Used to force the latch to operate at the unstable equilibrium point, V BL = V BL When M PC is on M PC is operated in linear region Then, bit-lines pre-charged to V BL = V BL =V DD / 015 년 7 월 10 일

8 [8.4.1] A Sense Amplifier for the 6-T Cell (cont.) Figure 8.3 : Bit-lines voltage waveform during the pre-charge operation M PC : cut-off Sense amplifier latch is operate in stable equilibrium point Two bit-lines have 0V or V DD M PC : turn-on Pre-charge transistor represents a low-resistance connection between the two bit-lines It requires about 30ns for the latch to reach the v O = v I 015 년 7 월 10 일

9 [8.4.1] A Sense Amplifier for the 6-T Cell (cont.) It requires long times about 30ns to pre-charge the bit-lines Pre-charge signal must remain active until the bitlines are equal If not, sensing errors may be occurred 015 년 7 월 10 일

10 Current & Power in the pre-charged Sense Amplifier Find the currents in the transistors in the sense amplifier Given condition V DD = 5V minimum size design : (W/L) ratio = /1 for NMOS K ' n N for PMOS K P ' p 5A / V 0.5 V, 10A / V, V FN, V 0.75 V, FP TON TOP 1V 0.6V 1V 0.6V 015 년 7 월 10 일

11 [Example 8.3] Current & Power in the pre-charged Sense Amplifier The pre-charge transistor M PC is turn-on The circuit has reached a steady-state condition The output voltages are the same V BL = V BL V D1 = V D = V O The current through M PC will be zero All transistors are operated in saturation region V GSN = V DSN in all NMOS devices V GSP = V DSP in all PMOS devices The drain currents must be identical on both sides of the latch I DP = I DN K ' p W L P ( V GSP V TP ) K ' n W L N ( V GSN V TN ) 015 년 7 월 10 일

12 [Example 8.3] Current & Power in the pre-charged Sense Amplifier K 3V ' p O W L V P 1 O ( V O ( V O 7 V DD 0 V 5 1), TP V ) O K ' n 510 W L 6.16V 1, N ( V O ( V O 1) V 4.16V TN ) Drain current : Power dissipation : I DP P I I DN D V DD (.16 1) A W 015 년 7 월 10 일

13 [Example 8.3] Current & Power in the pre-charged Sense Amplifier Discussion on power dissipation Power dissipation in one sense amplifier is small about μW If 10 (=104) bit-line exist, total power dissipation is about mW Too large power dissipation It must be minimized!!! To minimize power dissipation Reducing the time that the latches are remain in the pre-charge state More complex design 년 7 월 10 일

14 8.4. A Sense Amplifier for the 1-T Cell Figure 8.4 : Simple sense amplifier for the 1-T cell The same sense amplifier can be used for the Dynamic RAM 1-T cell in a manner shown in the left figure Dynamic RAM 1-T cell is connected to bitline BL 015 년 7 월 10 일

15 [8.4.] A Sense Amplifier for the 1-T Cell (cont.) Figure 8.5 : Single-ended sensing of the 1-T cell Pre-charging the bit-lines Turn-off the pre-charging signal Turn-off the M PC Raising the word-line voltage to high Accessing the data in the memory cell through access transistor M AC Charge sharing is occurs between C BL and C C Sense amplifier detect small voltage difference in bit-lines Generate almost full logic level in about 5ns Slow charge transfer 015 년 7 월 10 일

16 8.4.3 The Boosted Word-line Circuit Figure 8.7 : 1-T sensing with word-line voltage boosted to 5V Raising the word-line voltage to 5V instead of 3V Cell capacitance voltage V C can be increased higher than 3V ( 3.7V) It is possible to increase the amount of current supplied to the storage capacitors A much more rapid charge transfer is evident in the storage node 015 년 7 월 10 일

17 [8.4.3] The Boosted Word-line Circuit (cont.) Pre-charge signal is turn-off Word-line voltage is raised to 5V Access transistor M A is turn on Charge sharing is occurred between the C BL and the C C Charge sharing Sense amplifier detect small voltage difference in bit-lines Generate almost full logic level in about 15ns Rapid charge transfer 015 년 7 월 10 일