Optimizing Standby

Transcription

1 Optimizing Standby Memory Benton H. Calhoun Jan M. Rabaey

2 Chapter Outline Memory in Standby Voltage Scaling Body Biasing Periphery

3 Memory Dominates Processor Area SRAM is a major source of static power in ICs, especially for low-power applications Special memory requirement: need to retain state in standby Metrics for standby: 1. Leakage power 2. Energy overhead for entering/leaving standby 3. Timing/area overhead BL WL BL M3 M2 M1 Q QB M6 M5 M4

4 Reminder of Design-Time Leakage Reduction Design-time techniques (Chapter 7) also impact leakage High- V TH transistors Different precharge voltages Floating BLs This chapter: adaptive methods that uniquely address memory standby power

5 The Voltage Knobs Changing internal voltages has different impact on leakage of various transistors in cell Voltage changes accomplished by playing tricks with peripheral circuits Leakage reduction (ratio) NMOS -δ δ (DIBL) 0 C 0 B1 ΔVTH k( δ + 2ψ 2ψ ) ΔVTH δ B2 0 A2 VDD + δ -δ 0 A1 VDD 0 L = 90 nm, T = 2 nm 0 0 VDD = 1 V S = 100 mv/decade + δ K = 0.2 V 1/2, 2 ψ = 0.6 V λ = Offset voltage, δ (V) 1.0 [Ref: Y. Nakagome, IBM 03]

6 Lower in Standby H Active mode L Standby mode drowsy drowsy low _SRAM SRAM Example Basic Idea: Lower lowers leakage sub-threshold leakage GIDL gate tunneling Question: What sets the lower limit? [Ref: K. Flautner, ISCA 02]

7 Limits to Scaling: DRV Data Retention Voltage (DRV): Voltage below which a bit-cell loses its data nm CMOS 0.3 = 0.4 V V 2 ( V) 0.2 = 0.18 V That is, the supply voltage at which the Static Noise Margin (SNM) of the SRAM cell in standby mode reduces to zero [Ref: H. Qin, ISQED 04] V 1 ( V) VTC 1 VTC 2

8 Power savings of DRV 1.4 mm mm IP Module of 4 kb SRAM Leakage Current ( A) Measured DRV range Supply Voltage (V) Test chip in 130 nm CMOS technology with built-in voltage regulator [Ref: H. Qin, ISQED 04] More than 90% reduction in leakage power with 350 mv standby (100 mv guard band).

9 DRV and Transistor Sizes DRV (mv) Ma Mp Mn Model Width Scaling Factor Where Ma,, Mp and Mn are the access transistor, PMOS pull-up, and NMOS pull-down, respectively [Ref: H. Qin, Jolpe 06]

10 Impact of Process Balance Stronger PMOS or NMOS (S P, S N ) in subthreshold lowers SNM even for typical cell [Ref: J. Ryan, GLSVLSI 07]

11 Impact of Process Variations on DRV DRV varies widely from cell to cell Most variations random with some systematic effects (e.g., module boundaries) DRV histogram has long tail DRV histogram for 32 Kb SRAM 130 nm CMOS 4000 DRV Spatial Distribution [Ref: H. Qin, ISQED 04] DRV (mv)

12 Impact of Process Variations on DRV DRV distribution for 90 nm and 45 nm CMOS 0.10 IEEE Frequency nm tail 45 nm tail DRV (mv) Other sources of variation: Global variations, data values, temperature (weak), bitline voltage (weak ) [Ref: J. Wang, CICC 07]

13 DRV Statistics for an Entire Memory DRV distribution is neither normal nor log-normal CDF model of DRV distribution (F DRV (x ) = 1 P(SNM < 0, = x )) Worst DRV (mv) Model Normal Log-normal Monte-Carlo IEEE Memory size σ [Ref: J. Wang, ESSCIRC 07]

14 Reducing the DRV DRV (mv) Chip DRV 1. Cell optimization 2. ECC (Error-Correcting Codes) 3. Cell optimization + ECC

15 Lowering the DRV Using ECC Data In ECC Encoder Write D P Data Correction Read ECC Data Out Decoder Error Correction Challenges Maximize correction rate Minimize timing overhead Minimize area overhead Hamming [31, 26, 3] achieves 33% power saving Reed-Muller Reed Muller [256, 219, 8] achieves 35% power saving [Ref: A. Kumar, ISCAS 07]

16 Combining Cell Optimization and ECC 1K words DRV histogram 1K words DRV histogram 1K words DRV histogram Original DRV (mv) Optimized DRV (mv) Standard Optimized Optimized+ECC Optimized DRV with Error Correction (mv) Normalized SRAM leakage current [Ref: A. Kumar, ISCAS 07] Original SRAM Optimized SRAM w/ ECC 50X mV B mV 255mV 0.2 C 0 D (V) SRAM Standby A Standard 1V B C Standard Optimized DRV MAX +100 mv DRV MAX +100 mv Optimized D wtih ECC DRV ECC_MAX +100 mv A

17 How to Approach the DRV Safely? Adjustable Power Supply V CTRL voltages Reset Sub-V TH Controller Failure Detectors Core Cells Using canary cells to set the standby voltage in closed loop [Ref: J. Wang, CICC 07]

18 How to Approach the DRV Safely? Histogram Less power SRAM cell Failure Threshold More reliable Multiple sets of canary cells Canary Replica & test circuit IEEE 2007 DRV 128KbSRAM ARRAY Mean DRV of Canary Cells (V) V CTRL (V) 0.6% area overhead in 90 nm test chip [Ref: J. Wang, CICC 07]

19 Raising V SS Raise bit-cellv SS in standby (e.g., 0 to 0.5 V) Lower BL voltage in standby (e.g., 1.5 to 1 V) 0 is 0.5 V Lower voltage less gate leakage and GIDL Lower V DS less sub- V TH leakage (DIBL) Negative V BS reduces sub-v TH leakage [Ref: K. Osada, JSSC 03] 1.0 V WL = 0 V 1.0 V 1.5 V V

20 Body Biasing Reverse Body Bias (RBB) for leakage reduction Move FET source (as in raised V SS ) Move FET body Example: Whenever WL is low, apply RBB Active Standby BL V PB WL BLB WL 0 V,V SS 0 V 2 V SS V PB,V NB 0 V V NB - [Ref: H. Kawaguchi, VLSI Symp. 98]

21 Combining Body Biasing and Voltage Scaling Active Standby BL V PB WL BLB WL 0 V,V SS 0 V 2 V SS V PB,V NB 0 V V NB - [Ref: A. Bhavnagarwala, SOC 00]

22 Combining Raised V SS and RBB BL V PB WL BLB V NB V SS 28X savings in standby power reported [Ref: L. Clark, TVLSI 04]

23 Voltage Scaling in and Around the Bitcell Large number of reported techniques [1] K. Osada et al. JSSC 2001 [2] N. Kim et al. TVLSI 2004 [3] H. Qin et al. ISQED 2004 [4] K. Kanda et al. ASIC/SOC 2002 [5] A. Bhavnagarwala et al. SymVLSIC 2004 [6] T. Enomoto et al. JSSC 2003 [7] M. Yamaoka et al. SymVLSIC 2002 [8] M. Yamaoka et al. ISSC 2004 [9] A. Bhavnagarwala et al. ASIC/SOC 2000 [10] K. Itoh et al. SymVLSIC 1996 [11] H. Yamauchi et al. SymVLSIC 1996 [12] K. Osada et al. JSSC 2003 [13] K. Zhang et al. SymVLSIC 2004 [14] K. Nii et al. ISSCC 2004 [15] A. Agarwal et al. JSSC 2003 [16] K. Kanda et al. JSSC 2004

24 Periphery Breakdown Periphery leakage often not ignorable Wide transistors to drive large load capacitors Low- V TH transistors to meet performance specs Chapter 8 techniques for logic leakage reduction equally applicable, but Task made easier than for generic logic because of well-defined structure and signal patterns of periphery e.g., decoders output 0 in standby Lower peripheral can be used, but needs fast level-conversion to interface with array

25 Summary and Perspectives SRAM standby power is leakage-dominated Voltage knobs are effective to lower power Adaptive schemes must account for variation to allow outlying cells to function Combined schemes are most promising e.g., Voltage scaling and ECC Important to assess overhead! Need for exploration and optimization framework, in the style we have defined for logic

26 References Books and Book Chapters: K. Itoh, M. Horiguchi and H. Tanaka, Ultra-Low Voltage Nano-Scale Memories, Springer T. Takahawara and K. Itoh, Memory Leakage Reduction, in Leakage in Nanometer CMOS Technologies, S. Narendra, Ed, Chapter 7, Springer Articles: A. Agarwal, L. Hai and K. Roy, A single-v/sub t/low-leakage gated-ground cache for deep submicron, IEEE Journal of Solid-State Circuits, pp , Feb A. Bhavnagarwala, A. Kapoor, J. Meindl, Dynamic-threshold CMOS SRAM cells for fast, portable applications, Proceedings of IEEE ASIC/SOC Conference, pp , Sep A. Bhavnagarwala et al., A transregional CMOS SRAM with single, logic V/sub DD/and dynamic power rails, Proceedings of IEEE VLSI Circuits Symposium, pp , June L. Clark, M. Morrow and W. Brown, Reverse-body bias and supply collapse for low effective standby power, IEEE Transactions on VLSI, pp , Sep T. Enomoto, Y. Ota and H. Shikano, A self-controllable voltage level (SVL) circuit and its lowpower high-speed CMOS circuit applications, IEEE Journal of Solid-State Circuits, 38(7), pp , July K. Flautner et al., Drowsy caches: Simple techniques for reducing leakage power., Proceedings of ISCA 2002, pp , Anchorage, May K. Itoh et al., A deep sub-v, single power-supply SRAM cell with multi-vt, boosted storage node and dynamic load, Proceedings of VLSI Circuits Symposium, pp , June, K. Kanda, T. Miyazaki, S. Min, H. Kawaguchi and T. Sakurai, Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic Vdd control (RRDV) scheme, Proceedings of IEEE ASIC/SOC Conference, pp , Sep

27 References (cont.) K. Kanda, et al., 90% write power-saving SRAM using sense-amplifying memory cell, IEEE Journal of Solid-State Circuits, pp , June 2004 H. Kawaguchi, Y. Itaka and T. Sakurai, Dynamic leakage cut-off scheme for low-voltage SRAMs, Proceedings of VLSI Symposium, pp , June A. Kumar et al., Fundamental bounds on power reduction during data-retention in standby SRAM, Proceedings ISCAS 2007, pp , May N.Kim, K. Flautner, D. Blaauw and T. Mudge, Circuit and microarchitectural techniques for reducing cache leakage power, IEEE Transactions on VLSI, pp , Feb Y. Nakagome et al., Review and prospects of low-voltage RAM circuits, IBM J. R & D, 47(516), pp , Sep./Nov K. Osada, Universal-Vdd V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell, IEEE Journal of Solid-State Circuits, pp , Nov K. Osada et al., 16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-rayinduced multierrors, IEEE Journal of Solid-State Circuits, pp , Nov H. Qin, et al., SRAM leakage suppression by minimizing standby supply voltage, Proceedings of ISQED, pp , H. Qin, R. Vattikonda, T. Trinh, Y. Cao and J. Rabaey, SRAM cell optimization for ultra-low power standby, Journal of Low Power Electronics, 2(3), pp , Dec J. Ryan, J. Wang and B. Calhoun, "Analyzing and modeling process balance for sub-threshold circuit design Proceedings GLSVLSI, pp , Mar J. Wang and B. Calhoun, Canary replica feedback for Near-DRV standby VDD scaling in a 90 nm SRAM, Proceedings of Custom Integrated Circuits Conference (CICC), pp , Sep

28 References (cont.) J. Wang, A. Singhee, R. Rutenbar and B. Calhoun, Statistical modeling for the minimum standby supply voltage of a full SRAM array, Proceedings of European Solid-State Circuits Conference (ESSCIRC ), pp , Sep M. Yamaoka et al., 0.4-V logic library friendly SRAM array using rectangular-diffusion cell and delta-boosted-array-voltage scheme, Proceedings of VLSI Circuits Symposium, pp , June M. Yamaoka, et al., A 300 MHz 25 μa/mb leakage on-chip SRAM module featuring processvariation immunity and low-leakage-active mode for mobile-phone application processor, Proceedings of IEEE Solid-State Circuits Conference, pp , Feb K. Zhang et al., SRAM design on 65 nm CMOS technology with integrated leakage reduction scheme, Proceedings of VLSI Circuits Symposium, 2004, pp , June 2004.