ENEE 359a Digital VLSI Design

Transcription

1 SLIDE 1 ENEE 359a Digital VLSI Design CMOS Memories and Systems: Part II, Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob , Wang 2003/4) as well as material taken from Keeth & Baker s DRAM Circuit Design.

2 SLIDE 2 Overview DRAM: DRAM systems DRAM circuits SRAM: SRAM systems SRAM circuits Register files

3 SLIDE 3 The Original 3T DRAM Cell Write columnline Read columnline Read rowline Write rowline M1 M3 M2 First generation DRAM cell MOSFET #2 is used as storage node (obvious to see why dynamic ) Read columnline precharged for read; line either pulled to GND or not.

4 SLIDE 4 Second Generation 1T1C Cell Digitline, columnline, or bitline Charge-sharing: Wordline or rowline V c C cell V b C V x bitline V b C b + V c C c V X = C b C c Wordline can be polysilicon; MOSFET formed by wordline over n+ active area To write full Vcc to storage capacitor, rowline (gate) must be driven to voltage Vccp > Vcc + Vth Bitline can be metal or polysilicon Charge-sharing: what potential should be at other side of storage capacitor? (e.g. V 0 = 0, V 1 = Vcc)

5 Wordline Bitlines Wordline SLIDE 5 Wordline Driver Row of DRAM Wordline presents large capacitive load; slow, limits t RC (time to open & close row) Use wordline driver: large FETs (remember scaling?) Polysilicon wordline usually topped with silicide ( polycide wordline); increases conductivity Additional drivers can be placed along length Wordline can be stitched with pieces of metal Typical organization: 512 wordlines x 512 bitlines

6 DRAM Array: Open Bitline SLIDE 6 BL3 WL0 WL1 WL2 WL3 BL2 BL1 BL0 Adjacent cells share connection to bitline Note change in orientation (rotated 90º)

7 Open Bitline Array & Cells WL0 WL1 WL2 WL3 WLA WLB WLC WLD BL3 BL2 BL3* BL2* SLIDE 7 BL1 BL1* BL0 BL0* Wordline drivers Sense Amps Wordline drivers 0 WL1 Wordline WL2 WL3 Bitline WL4 WL5 Capacitor Active area Bitline contact

8 SLIDE 8 Folded Bitline Array & Cell WL0,A WL1,B WL2,C WL3,D BL3* BL3 BL2 BL1 BL2* BL1* Routing BLX and BLX* together improves noise immunity (esp. in conjunction with bitline twisting ) BL0 BL0* Wordline drivers Sense Amps Wordline WL2 WL3 Bitline Active area Bitline contact Capacitor

9 SLIDE 9 Open vs. Folded Cell Areas Bitline pitch 2F Open bitline cell: 1F x 3F = 6F 2 Cell pitch 1/ /2 = 3F Folded bitline cell: 2F x 4F = 8F 2 Bitline pitch 2F Cell pitch (2 cells) 1/2+7+1/2 = 8F

10 Sensing I Recall behavior of nfet: Bitline Gate SLIDE 10 Wordline GND GND FET conducts when Gate = Vth FET conducts when Gate = Vth + Vcc Gate GND V b C b + V c C c V X = C b C c Scenario 1: nfet conducts when gate voltage exceeds min{source,drain} (GND) by Vth Scenario 2: nfet conducts when gate voltage exceeds min{source,drain} () by Vth

11 SLIDE 11 Sensing II V Wordline voltage V th Reading logic 1 V signal time V b C b + V c C c V X = C b C c V Wordline voltage Reading logic 0 V signal V signal = V c C c C b C c V th time Passing Logic 1: Capacitor begins to discharge when wordline exceeds bitline PRECHARGE voltage by Vth Passing Logic 0: Capacitor begins to discharge when wordline exceeds Vth

12 SLIDE 12 Sense Amplifiers I Circuit diagram: BL1 ACT NLAT* BL1* P sense-amp N sense-amp Initially, ACT at Vss (GND) and NLAT* held at (both BL1 and BL1* are at as well) To read: Wordline pulled to Vcc+Vth, BL1/* changes To sense: first, NLAT* is pulled towards ground Then ACT is pulled towards Vcc

13 Sense Amplifiers II Basic idea: BL1 SLIDE 13 ACT VCC NLAT* GND BL1* OR BL1 ACT GND NLAT* VCC BL1*

14 SLIDE 14 Sense Amplifiers III ACT BL1 NLAT* BL1* Vccp V Wordline voltage Vcc ACT NLAT* Vth BL1 BL1* time

15 SLIDE 15 Equilibration I ACT NLAT* Equal? BL1 BL1* Textbook s term: equalization

16 SLIDE 16 Equilibration II ACT NLAT* BL1 VCC/2 BL1* EQ LAYOUT: BL1 poly n active area BL1* EQ VCC/2

17 Bitline Twisting None SLIDE 17 Single Triple Complex this is just a small sample

18 Cells: Buried Capacitor Bitline SLIDE 18 Interlayer dielectric ONO dielectric Poly3 cellplate Bitline contact Wordline Field poly n+ n+ FOX n+ active p substrate Poly2 storage node

19 SLIDE 19 Cells: Buried Bitline/Digitline Interlayer dielectric ONO dielectric Poly3 cellplate Bitline Bitline contact Wordline n+ n+ n+ active p substrate Field poly Poly2 storage node Bitline FOX

20 SLIDE 20 Cells: Trench Capacitor Bitline Poly strap Bitline contact n+ active Wordline Field poly FOX Poly storage node ONO dielectric Heavily doped substrate region

21 Cells: Buried Capacitor SLIDE 21 Bitline Interlayer dielectric ONO dielectric Poly3 cellplate Bitline contact Wordline Field poly n+ n+ n+ active FOX p substrate Poly2 storage node

22 Cells: Buried Bitline/Digitline SLIDE 22 ONO dielectric Poly3 cellplate Interlayer dielectric Bitline Bitline contact Wordline n+ n+ active n+ p substrate Field poly Poly2 storage node Bitline FOX

23 SLIDE 23 Cells: Trench Capacitor Bitline Poly strap Bitline contact n+ active Wordline Field poly FOX Poly storage node ONO dielectric Heavily doped substrate region

24 Cells: edram (logic process) Bitline Wordline SLIDE 24 or to sense amp????????? Basic idea: replace funky capacitor structure (which requires special process technology to produce) with something that looks like logic DRAM is now embedded into a logic process: on same chip as CPU cores, etc. Question: do we still tie far side to VCC/2?

25 Cells: edram (logic process) SLIDE 25 Active Polysilicon Contact Metal The components

26 Cells: edram (logic process) SLIDE 26 to Sense Amp WL VDD to sense amp The cell WL VDD

27 SLIDE 27 Cells: edram (logic process) VDD VDD VDD BL i-1 BL i BL i+1 BL i+2 WL i-1 WL i WL i+1

28 Cells: edram (logic process) SLIDE 28 to Sense Amp WL VDD Via WL gate n+ n+ poly plate VDD channel M1 Bitline storage node Why is poly plate held at (global) VDD?

29 edram: 2-bit cell (CMU) SLIDE 29 Active area

30 edram: 2-bit cell (CMU) SLIDE 30 Poly I

31 edram: 2-bit cell (CMU) SLIDE 31 Poly II

32 edram: 2-bit cell (CMU) SLIDE 32 Via & Metal 1

33 edram: 2-bit cell (CMU) SLIDE 33