! Serial Access Memories. ! Multiported SRAM ! 5T SRAM ! DRAM. ! Shift registers store and delay data. ! Simple design: cascade of registers

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1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec 28: November 16, 2016 RAM Core Pt 2 Outline! Serial Access Memories! Multiported SRAM! 5T SRAM! DRAM Penn ESE 370 Fall 2016 Khanna (adapted from CMOS VLSI DESIGN, DM Harris) 2 Serial Access Memories! Serial access memories do not use an address " Shift Registers " Serial In Parallel Out (SIPO) " Parallel In Serial Out (PISO) " Queues (FIFO, LIFO) Shift Register! Shift registers store and delay data! Simple design: cascade of registers Din 8 Dout 3 4 Denser Shift Registers Serial In Parallel Out! Flip-flops aren t very area-efficient! 1-bit shift register reads in serial data! For large shift registers, keep data in SRAM instead! Move read/write pointers to RAM rather than data " After N steps, presents N-bit parallel output " Initialize read address to first entry, write to last " Increment address on each cycle Din Sin in counter counter readaddr writeaddr dual-ported SRAM out P0 0 out P1 1 out P2 2 out P3 3 reset Dout 5 6 1

2 Parallel In Serial Out! Load all N bits in parallel when shift = 0 " Then shift one bit out per cycle shift/load in P0 0 P1 in 1 in P2 2 inp3 3 Sout Queues! Queues allow data to be read and written at different rates.! Read and write each use their own clock, data! Queue indicates whether it is full or empty! Build with SRAM and read/write counters (pointers) WriteClk ReadClk WriteData FULL Queue ReadData EMPTY 7 8 FIFO, LIFO Queues Reminder: 6T SRAM Cell! First In First Out (FIFO) " Initialize read and write pointers to first element " Queue is EMPTY " On write, increment write pointer " If write almost catches read, Queue is FULL " On read, increment read pointer! Last In First Out (LIFO) " Also called a stack " Use a single stack pointer for read and write! Cell size accounts for most of array size " Reduce cell size at expense of complexity! 6T SRAM Cell " Used in most commercial chips " Data stored in cross-coupled inverters! Read: BL bit " Precharge BL, BL word " Raise WL WL! Write: " Drive data onto BL, BL " Raise WL bit_b BL 9 10 Multiple Ports Dual-Ported SRAM! We have considered single-ported SRAM " One read or one write on each cycle! Multiported SRAM are needed for register files! Examples: " Pipelined ALU register file: " add r1,r2,r3 " R3#R1+R2 " Requires two reads and one write! Simple dual-ported SRAM " Two independent single-ended reads " Or one differential write worda wordb bit bit_b

3 Dual-Ported SRAM! Simple dual-ported SRAM " Two independent single-ended reads " Or one differential write Multi-Ported SRAM! Adding more access transistors hurts read stability! Multiported SRAM isolates reads from state node! Single-ended bitlines save area worda wordb bit bit_b! Do two reads and one write by time multiplexing " Read during ph1, write during ph ! Initially " 1V " 0V! Close switch! Voltage at A? Initially " 1V " 0V! Q A =1V*C1=C1 Close switch! Q tot =V final *(C1+C0)! Charge conservation " Q A =Q tot! C1=V final *(C1+C0) V final = C1 C1+ C Consider (preclass 2)! Read: What happens to voltage at A when WL turns from 0$1? " Assume W access large " W access >> W pu =1 " BL initially 0 " A initially 1 Voltage After enable Word Line! Q BL = 0! Q A = (1V)(γ(2+W access )C 0 )! 100fF=C BL >>C A =(γ(2+w access )C 0 )! After enable W access (W access large) " Total charge Q BL +Q A unchanged " Charge conservation " Distributed over larger capacitance~=c BL " V A =V BL ~= C A /C BL

4 Voltage After enable Word Line! Q BL = 0! Q A = (1V)(γ(2+W access )C 0 ) Larger Resistance?! What happens if W access small? " W access < W pu! 100fF=C BL >>C A =(γ(2+w access )C 0 )! After enable W access (W access large) " Total charge Q BL +Q A unchanged " Charge conservation " Distributed over larger capacitance~=c BL C1 V final = C1+ C0 " V A =V BL ~= C A /C BL Larger Resistance? Simulation: W access =100! What happens if W access small? " W access < W pu! Takes time to move charge from A to BL! Moves more slowly than replenished by W pu Simulation! Conclude: charge sharing can pull down voltage

5 Consider (5T SRAM) Simulation W access =20! What happens to voltage at A when WL turns from 0$1? " Assume W access large " A initially 1 " BL initially Simulation W access =4! Conclude: charge sharing can lead to read upset " Charge redistribution adequate to flip state of bit How might we avoid? Charge to middle Voltage! Pre-charge bitlines to V dd /2 before begin read operation! Now charge sharing doesn t swing to opposite side of midpoint

6 Pre-Charge Simulation W access =20! Use one phase of clock to charge a node to some initial value before operation Precharge transistor can be large Compare Simulation W access =20 (precharge Vdd/2, reading 0)! Both W access =20; vary precharge Simulation W access =20 (with precharge Vdd/2) Pre-Charge V dd /2 Reference! Use one phase of clock to charge a node to some initial value before operation

7 DRAM 3-Transistor DRAM Cell! Smaller than SRAM! Require data refresh to compensate for leakage BL1 BL2 WWL WWL RWL RWL M1 X M3 M2 X BL1 V DD VDD-VT C S BL2 VDD-VT ΔV No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V WWL-V Tn 37 1-Transistor DRAM Cell WL CBL BL M1 C S WL X GND V DD BL VDD/2 C ΔV V BL V ( PRE V BIT V ) S = = PRE C S + C BL Write "1" Read "1" V DD V T sensing VDD/2 Write: CS is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance DRAM Cell Observations! 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out! DRAM memory cells are single ended in contrast to SRAM cells! The read-out of the 1T DRAM cell is destructive; read and refresh operation are necessary for correct operation! Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design! When writing a 1 into a DRAM cell, a threshold voltage is lost. This loss can be circumvented by bootstrapping the word lines to a higher value than V DD. Voltage swing is small; typically around 250 mv. Idea! Multiported SRAMS " Enable register file operation " Hurts read stability! 5T SRAM more sensitive to sizing than 6T SRAM! Serial access memories do not use an address " Shift Registers, Serial In Parallel Out (SIPO), Parallel In Serial Out (PISO), Queues (FIFO, LIFO)! DRAM memory " Smaller memory cell " Require data refresh " Bootstrap wordlines Admin! HW 7 due Friday! Project 2 out after class " taniak@seas.upenn.edu with project partners by Monday 11/21 " Don t work alone! " Extra credit for best performance (top 2 teams) " Extra credit for best written report (top 1 team)! Friday lecture " Detailed periphery circuits! Monday in Detkin Lab