EDA Past, Present & Future. Ernest S. Kuh Department of EECS University of California, Berkeley

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1 EDA Past, Present & Future Ernest S. Kuh Department of EECS University of California, Berkeley

2 DEDICATED TO Donald O. Pederson A. Richard Newton EDA Pioneers 2

3 The Beginning Circuit Simulation Circuit Simulators in the 60 s SPICE in the 70 s Circuit Layout (Physical Synthesis) Lee Maze Router 1962 Breuer book 1972 Design Automation of Digital Systems 3

4 CAD INDUSTRY Cadence Daisy Mentor Valid Avanti Cadence Mentor Synopsis Cadence Synopsis Mentor Magma Startups Applicon Calma Computervision

5 5 The Best of ICCAD Functional Verification System Design and Analysis Logic Synthesis Analog and Digital Circuit Design Physical Simulation and Analysis Physical Design Timing, Test and Manufacturing Industry Viewpoints

6 Physical Design Classical Problems Routing Placement Partitioning Floor-Planning (Sequence Pair) 6

7 Timing Issues Delay Signal Integrity Modeling and Timing Analysis Timing-Driven Placement Interconnect Delay Wire Placement? 7

8 Circuit Simulation Outline Cadence - Chi-Ping Hsu (Corp VP) Power issue Nannor - Wayne Dai (Chairman and Founder) DFM issue Conclusions 8

9 Circuit Simulation Story of SPICE Ron Rohrer: CANCER(Computer Analysis of Nonlinear Circuits Excluding Radiation) Don Pederson :SPICE(Simulation Program with Integrated Circuits Emphasis) Larry Nagel Rich Newton 9

10 SPICE Modified Nodal Analysis Dynamic Memory Management Multiple-Order Integration Method of Gear Time-Step Control Algorithm More Accurate MOS Models Secondary Effects for BJTs 10

11 SPICE Interactive Program Modular Version in C of SPICE 2 Graphic Display of Results Basis for New Circuit Simulation Developments at UC Berkeley 11

12 SUBSEQUENT SIMILATORS Semi-Implicit Integration MOTIS 1975 Relaxation SPLICE 1984 Waveform Relaxation RELAX 1984 Expondential Integration XPSIM 1988 Stepwise Constant Device Model SPEC 1989 Asymptotic Waveform Evaluation AWE 1990 Step Wise Equivalent Conductance SWEC

13 SWEC Digital MOS Circuits with Transmission Lines Key Features Stepwise Equivalent Conductance Model Event-Driven Approach Based on Slopes Pade Approximation and Recursive Convolution 13

14 Model Order Reduction Pade: Explicit Moment Matching Balanced Truncation Chebyshev Polynomial State Space: Krylov Subspace and Arnoldi Algorithm Congruent Transformation and Passivity Variational Interconnect Model and Stochastic Approach 14

15 Commercial Software Device and Interconnect Models Partitioning Model Order Reduction Multi-rate and Event driven Simulation Hierarchical Simulation 15

16 Commercial Software Star-Sim, Hsim, UltraSim Digital, Analog and Mixed Signal Power, Delay, Noise and Reliability Speed: faster than SPICE Unlimited Capacity 16

17 What is UltraSim? Fast SPICE Hierarchical Simulator Transistor-level full-chip dynamic simulator For SoC, Memory, Digital Logic & Mixed-signal 100 to 1,000 times faster than SPICE In flat mode Has capacity to handle multi-million transistors Circuit with accuracy that is within 2-3% of SPICE 1,000 to 1,000,000 times faster than SPICE In hierarchical mode Remains within 2-3% of SPICE 17

18 Circuit Analysis Research with UCSD Generalized Y-Delta Transformation for Circuit Reduction Integration Methods Alternating Direction Implicit Method (Two-way Partition) Exponential Operator Splitting Method (Multi-way Partition) Linear System Solutions Two-Stage Newton Raphson Iteration AMG for linear sub-circuits KLU for nonlinear sub-circuits Distributed Simulation 18

19 Distributed Simulation Process Distributed Circuit Partitioning Two-Stage Newton-Raphson Partition Domain Decomposition Distributed Device Loading Fast Parallel Matrix Solver Iterative Matrix Solver on Linear System Distributed Direct Solver on Partitioned Subcircuits Homotopy Nonlinear Solver Adaptive Time Step Control 19

20 Distributed Simulation PU 1 Direct Solver (KLU) PU 2 Direct Solver (KLU) PU k-1 Direct Solver (KLU) Nonlinear Sub-circuit Nonlinear Sub-circuit Nonlinear Sub-circuit Device Loading Device Loading Device Loading Equivalent Ckt Equivalent Ckt Equivalent Ckt Original Circuit Interface Linear-Nonlinear Iteration Equivalent Ckt Equivalent Ckt Equivalent Ckt linear Sub-circuit PU K Parallel AMG linear Sub-circuit PU K+j1 Parallel AMG linear Sub-circuit PU K+jm Parallel AMG 20 PU: Processing Unit

21 Simulation for the Future Mems (Kris Pister) Bio (Shankar Sastry) Optical Nano 21

22 Cadence Design Systems Global leader of design automation solutions Market Cap: $5.5B* 2006 Revenue: $1.5B WW offices: 57 North America 54% Europe 19% Asia 10% Japan 17% Employees: 5200 *February

23 Cadence Design Systems Enabling companies to play in trillion MISSION To be and be recognized as the indispensable partner to the electronics industry dollar markets COMPUTING COMMS CONSUMER AUTOMOTIVE INDUSTRIAL GOV/MIL 23

24 Semiconductor consumption driven by 3 Cs Consumer. Computing. Communications Total IC Market by System Type ($B) Source: SIA, IC Insights COMPUTING COMMS CONSUMER AUTOMOTIVE INDUSTRIAL GOV/MIL 24

25 Design chain orchestration EMS System Biggest investment in collaboration with your design chain partners Test chips Reference Flows Joint development Methodologies ISV Foundry Semi IP 25

26 Thought leadership Industry wide Common power format Si2 to facilitate standardization of the Common Power Format (CPF) through the IEEE 26

27 Process migration is creating new power management challenges Leakage Power Active Power Process Technology (nm) 27

28 Current design-based solutions are fragmented Logic is Connected Power is Not Connected Formal Analysis Parser Testbench Simulation Parser Hardware Parser Formal Analysis Parser Testbench Simulation Parser Hardware Parser Management Synthesis Management Synthesis Parser Parser Parser Parser SVP Parser Logic Information (Verilog) Equivalence Checking Parser SVP Parser Power Information (no consistency) (CPF) Equivalence Checking Parser Parser P+R Parser Test Parser P+R Parser Test IP Libraries IP Libraries Can be Automated Very Difficult to Automate 28

29 Basic Impacts of Advanced Low-power Techniques Power reduction technique Area optimization Multi-Vt optimization Clock gating Leakage Dynamic Timing Area power power penalty penalty 1.1X 6X 0X 10% 0% 20% 0% 0% 0% -10% Implement. impact None Logic design impact None 2 to Automated -2% Low in the None1990 snone <2% Low Low Verification impact None None Multi-supply voltage (MSV) 2X 40-50% 0% <10% Medium Medium Low Advanced Power shut-off (PSO) Dynamic and Adaptive Voltage Frequency Scaling (DVFS and AVS) 10-50X 2-3X ~0% 40-70% 4-8% 0% 5-15% <10% Encounter Medium-high Low Power Made Easy! High High High High High Substrate Biasing 10X - 10% <10% High Medium-High Medium 29

30 Si2 Low Power Coalition Forms to Unify Standardization Efforts LPC Members Announced (17) IBM Intel Texas Instruments STMicroelectronics AMD NXP Semiconductors LSI Logic Cadence Design Systems Magma Design Automation Sequence Design Apache Design Solutions Atrenta Azuro Virage Logic ChipVision Design Systems Golden Gate and others

31 DFM is Critical for Sub 90nm Design Yield Catastrophic Parametric Yield Loss is Increasing!!! Catastrophic yield loss Random particles (short/open fault), lithography (short/open hotspots), CMP (topography) Parametric yield loss Process variation, Lithography (statistics & systematic), CMP(parasitics) Both are increasing fast and the foundry are saying Yes, you need to do DFM at 65 nm. By 65 nm we cannot eliminate systematic yield losses with anything we can do in the foundry. It's up to the chip-design teams." -David Lan, TSMC North America 31

32 Sources of Yield Loss Lithography the feature sizes are decreasing faster than exposing wavelengths Layout geometries by the design tools Actual geometries on the wafer Random Particles Extra metal defects bridge faults Missing metal defects open faults Interconnects And more 32

33 Resolution Enhancement Techniques (RET) Resolution Enhancement Techniques (RET) Optical proximity correction Scattering bars Phase shift masks (PSM) However Determining the RET patterns is complex and contextdependent higher cost Increases the complexity of the geometry lower mask yield higher cost 33

34 Spacing/width Optimizations Wire spreading Move wires apart with an optional extra spacing Wire widening DFM guideline 34

35 Yield-preferred Vias Redundant-cut via: at least one redundant cut not required in functionality reduce via failure More metal coverage DFM guideline 35

36 Conventional Techniques Fails Fight with yield loss: Recommended DFM rules DFM guidelines Floorplan Placement Number and complexity of design rules are exploding Design rules cannot cover all the manufacture issues Routers can t handle the complex rule set efficiently Slower (more rules) More chip area (overhead) Design rules Routing Design Verification RET Yield Issues 36

37 Nannor s Solution: Acuma TM Stand-alone from the main flow More flexible More versatile Floorplan Placement Milkyway Advanced Design Rules Litho Analysis Critical Area Analysis More capable Plug-in and play Compatible with all design flows Interface with DFM analysis tools Routing Timing Verification OA LEF/DEF Lava Acuma TM 37

38 Acuma TM Layout Technology Provide efficient layout modification for advanced design rules. Enable advanced design rule implementation with reduced turn- around-time and full-chip capacity. Support local rip-up and reroute. Have 1 US patent granted and 3 US patents pending. 38

39 CONCLUSION Circuit Simulation Distributed Computing Stochastic Approach Application to other Areas DFM Power Forward Yield-Oriented Physical Design 39