Accelerating Innovation
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1 Accelerating Innovation In the Era of Exponentials Dr. Chi-Foon Chan President and co-chief Executive Officer, Synopsys, Inc. August 27, 2013 ASQED 1
2 Accelerating Technology Innovation Exciting time to be an Engineer The Era of Electronics Technology The Future Ahead ASQED 2
3 $1.76B FY12 Revenue ~84 Offices Worldwide System Design ~8,195 Employees ~4,431 Masters/ PhD Degrees Verification IP Implementation ~31% R&D/Revenue ~5,129 R&D Engineers ~1,100 Application Consultants ~1,889 Issued Patents ASQED 3 Manufacturing Advanced Technology Leadership Delivers Benefits at Every Node
4 What Happens in 204 Million s Sent >2 Million Search Queries 6 Million Facebook Views And the Future Growth is Exponential Today, the number of = the global networked devices population 1.3 Million Video Views By 2017, the number of devices 3x connected to IP networks will be as high as the global population ASQED 4 Source: Cisco Systems, VNI Global Mobile Data Traffic Forecast Update 2013 and Intel SmartTech Blog
5 Moore s Law Continues 1.0E+12 Transistor Count Trends Transistors per Die 1.0E E E+9 1.0E+8 1.0E+7 1.0E+6 1.0E+5 DRAM NAND Flash (SLC) NAND Flash (MLC) Intel PC MPU Intel Server MPU 64Kb 256Kb Mb Mb Gb 256Gb MLC/128Gb SLC 128Gb MLC/64Gb SLC 64Gb 4Gb 4Gb "Poulson" 2Gb "Tukwila" "Broadwell" 1Gb Itanium 2 "Ivy Bridge" "Gulftown" 256Mb Itanium 2 Core i7 "Bloomfield" Core 2 Duo 64Mb Pentium 4 "Prescott" Itanium Pentium 4 16Mb Pentium III Pentium II Pentium Pro Pentium 8Gb 1.0E+4 1.0E+3 4Kb 1Kb Kb E F 16F Source: Intel, SIA, IC Insights 2012 ASQED 5 Year
6 Designs Are Larger and Faster 60, MHz 50, Gate Count, K Gates 40,000 30,000 20, Clock Frequency 10, Expon. (Gate Count, K Gates) Expon. (Clock Frequency, MHz) Source: Synopsys Global User Survey, ASQED 6
7 Power Is a Growing Problem Leakage Power Dynamic Power W/cm nm 65nm 40nm 28nm 20nm Source: IBS ASQED 7
8 Functional Verification Costs Are Exploding $6.0B $5.0B Engineering Effort IT Infrastructure for Verification $4.0B $3.0B $2.0B $1.0B $0.0B Source: VCS User Companies, Synopsys ASQED 8
9 Chip Development Costs Are Increasing $300 $250 $200 Chip Design Software Dev. +116% Cost ($M) $150 $ % +96% $50 $0 +44% +75% +62% +54% 65nm (90M) 45/40nm (130M) 28nm (180M) 22/20nm (240M) 16/14nm (310M) Feature Dimension (Transistor Count) Source: IBS, December 2012 ASQED 9
10 Advanced Designs at Every Node st to tapeout at 65nm 1 st to tapeout at 45/40nm 1 st to tapeout at 32/28nm 1 st to tapeout at 22/20nm Q3'03 Q4'03 Q1'04 Q2'04 Q3'04 Q4'04 Q1'05 Q2'05 Q3'05 Q4'05 Q1'06 Q2'06 Q3'06 Q4'06 Q1'07 Q2'07 Q3'07 Q4'07 Q1'08 Q2'08 Q3'08 Q4'08 Q1'09 Q2'09 Q3'09 Q4'09 Q1'10 Q2'10 Q3'10 Q4'10 Q1'11 Q2'11 Q3'11 Q4'11 Q1'12 Q2'12 Q3'12 Q4'12 Q1'13 Q2'13 90nm Advanced Tapeout Counts 65nm ASQED 10 45/40nm 32/28nm 22/20nm 16/14nm 10nm
11 Companies Working Hard to Differentiate Recession Recovery Uncertainty ASQED 11 Semi Snapshot as of 7/23/2013
12 Source: IC Insights Report, August 02, ASQED 12
13 Source: IC Insights Report, August 02, ASQED 13
14 Buys Buys Forces Driving Consolidation Buys Buys - Wireless Critical Mass Differentiation Collaboration Shaping the Industry Buys Buys Buys Buys Buys Semiconductor MODEM Buys Buys Accelerating Innovation Buys Buys Buys ASQED 14
15 Accelerating Technology Innovation Differentiation The Era of Electronics Technology The Future Ahead ASQED 16
16 Prototyping Enables Earlier Software Development Traditional Flow Software Stack Synopsys Virtual Prototype Development Effort Hardware Development Software Development Time to Market Integration & Test Product Support & Maintenance Time in Market Prototype A simulation model for the targeted hardware Development Effort Software Higher Productivity Integration & Test Hardware Earlier TTM With Virtual Prototyping Higher Quality Product Support & Maintenance Time to Market Time in Market ASQED 17
17 Increasing Use of Silicon IP and Silicon IP Subsystems Application Processor Application CPU Application CPU RAM RAM ROM Graphic Core(s) Specialty I/O LVDS, Etc Graphics Processors I/O RAM RAM RAM RAM Flash Interface Flash Storage Memory I/Fs On-Chip Bus & Others Basic Peripherals (UARTs/Timers) RAM On-Chip Bus RAM RAM RAM DDR Interface DDR memory Memories & Logic Libraries Interfaces Interface Data Converters Analog Audio / Video I/F Headset Jack Microphone Audio Codecs Video Codecs USB PCIe SATA HDMI MIPI * Small boxes are standard cell library elements. ASQED 18 Analog Deeply embedded processors
18 Increasing Design Complexity 3 rd Party IP Usage Will Continue to Double Through Consumer Escalating Design Costs Wireless Communication Shorter Time Window for New Product Launch Data Processing Automotive Overall 3 rd party design IP use in 2012 Industrial Strong Growth in 3 rd Party IP Usage Wired Communication 0% 15% 30% 45% 60% 75% 90% Percentage of 3 rd Party IP Block Overall 3 rd party design IP use in 2017 Source: Gartner, Semi IP Market, March 2013 ASQED 19
19 Evolution of Implementation Technology 2002 Correlation 2005 Look-Ahead 2009 In-Design 2011 Exploration 2012 Co-Design Synthesis Synthesis Synthesis Synthesis Synthesis Signoff Design Planning Place & Route Signoff Place & Route Signoff Place & Route Signoff Place & Route Signoff Place & Route Custom DRC / LVS DRC / LVS DRC / LVS DRC / LVS DRC / LVS ASQED 20
20 Below 22nm Requires Advanced Solutions FinFET Double Patterning (DPT) Power Density / Integration Performance Performance Power Power Area 3D-IC Density / Integration Power Performance Delivering More Performance with Less Power Performance in a Smaller Area ASQED 21
21 FinFET Technology Must Be Supported Across the Entire SoC Design Process Gate Process Develop. Characterization Design Implementation IP TCAD Circuit Simulation Custom Design Implementation >= DPT spacing C 1 Trench Contact V0 M0 C2 C 3 Fin Sourc e C4 Fin Drain C5 Substrate 3D Lithography Extraction Physical Verification Signoff ASQED 22
22 a b c d a c b d TH TH SoC Design Requires Advanced Advanced multi-voltage techniques Low Power Design Techniques Multi-Voltage Power Gating (Shutdown) DVFS, AVFS Advanced Low Power Mainstream intent-driven techniques Well Biasing EN CLK Clock Gating FF LT ICG Low-VDD Standby Techniques Gate-Level Opt. Architect. Opt. Multi-Threshold Synthesis-based optimization techniques 16 bit 64 bit Ripple CLA Carry Skip Carry Select Carry Save Leakage Current Low V TH TH Nominal V Delay TH TH High V Basic ASQED 23
23 The Problem in Verification Is Time & Cost Heavy Setup and Debug Activity Issue is Engr. Resource and Time Heavy Regression Activity Issue is Compute Cost and Time Verification Reuse Debug Automation Faster Simulation Project Time Bugs Found Compute Cycles ASQED 24
24 Comprehensive SoC Verification Platform Manages Time-to-market & Verification Complexity Technology Must Address Performance Capacity Accuracy Productivity Standards Digital Low-Power AMS HW/SW ASQED 25
25 Accelerating Technology Innovation Collaboration 1. Industry The Era of Electronics 2. University 3. Government Technology The Future Ahead ASQED 26
26 Environmental Legal Ethical Technology Economics Different Disciplines ASQED 27
27 The Economist Morals and the Machine Teaching robots right from wrong June 2, 2012 Economist.com ASQED 28
28 A Car or a Computer on Four Wheels? California becomes latest state to OK driverless cars September 25, 2012 Sources: USA TODAY, California becomes latest state to OK driverless cars, September 25, The Economist, Look, no hands, September 1, ASQED 29
29 The New Green Hub Shifting Gears to Sustainable Development Source: Ecofriend.com Urban Reforestation: Sky-bridges & green connectors to give a new skyline to Kuala Lumpur ASQED 30
30 Purpose + Plan + Our Part How will we impact the future and accelerate innovation? Economy Technology Environmental Legal, Ethical Responsibility ASQED 31
31 ASQED 32 Thank You
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