Analog, Mixed-Signal, and Advanced-Node Custom Design Scalability, Convergence and Throughput

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1 Analog, Mixed-Signal, and Advanced-Node Custom Design Scalability, Convergence and Throughput Tom Beckley, Senior VP of R&D, Custom IC and Simulation Analog Semiconductor Leaders' Forum Seoul, Korea October 10, 2012

2 Key market trends are pressuring design delivery Automotive Apps, Video Mobility Cloud Low Power Cadence Design Systems, Inc. All rights reserved.

3 Automobiles full of analog and mixed-signal technology Inverter/converter and navigation unit Source: UBM TechInsights (EETimes, 5/14/2007) Cadence Design Systems, Inc. All rights reserved.

4 Enhancing convergence by reducing complexity Build designs that are robust and yield better results Traditional custom/analog design Time to market Mixed-signal design Advanced-node custom design Cadence Design Systems, Inc. All rights reserved.

5 Traditional custom/analog design Cadence Design Systems, Inc. All rights reserved.

6 SCHEMATIC New custom design methodology Include layout effects as early as possible Schematic entry MODGEN creation Constraint entry Device placement Test creation and initial simulations Rapid information exchange Net routing LAYOUT Pre-layout parasitic estimation In-design signoff Design centering Extraction Pre- and postlayout comparisons Cadence Design Systems, Inc. All rights reserved.

7 Traditional custom design Specification vs. Implementation Custom design intent is usually represented by schematics Plus text notes and specifications Incomplete information of electrical design intent is passed to layout No automated exchange of information between design and layout engineer Physical implementation may not meet electrical design requirements Manual process to verify design intent Re-use is challenging Cadence Design Systems, Inc. All rights reserved.

8 Using design constraints to maintain intent Schematic and layout are linked and tracked against the constraint Changes are flagged and accessible for discussion Tie your global design centers together Cadence Design Systems, Inc. All rights reserved.

9 Foundation of robust circuit design Efficiently manage verification by managing all the tests Cadence Design Systems, Inc. All rights reserved.

10 Analyze, repair, and prevent variability problems The technology exists to help, but must be applied intelligently Analyze Improved Monte Carlo performance Improved results visualization High-sigma yield estimation Repair Simulate calibration Leverage designer expertise with manual tuning Using the right tool to solve the right problem Prevent Size over corners Improve yield In-design analysis with worst case corners Cadence Design Systems, Inc. All rights reserved.

11 SCHEMATIC New design methodology Include layout effects as early as possible Schematic entry MODGEN creation Constraint entry Device placement Test creation and initial simulations Rapid information exchange Net routing LAYOUT Pre-layout parasitic estimation In-design signoff Design centering Extraction Pre- and postlayout comparisons Cadence Design Systems, Inc. All rights reserved.

12 Reusable layout structures - MODGENs Using groups of like items to advantage Cadence Design Systems, Inc. All rights reserved.

13 Rapid analog generation capability Constraints and MODGENs Focus on getting a quick but accurate placement to enable designers to quickly simulate with accurate layout effects MODGENS Constraints Cadence Design Systems, Inc. All rights reserved. Rapid Layout Generation

14 Rapid analog generation capability Analog Placer one-button click Designers get a quick but accurate placement driven by constraints and MODGENs to enable quick capturing of layout effects MODGEN MODGEN First solid placement MODGEN Using MODGEN, symmetry, and clustering constraints aid auto-placement MODGEN MODGEN MODGEN Cadence Design Systems, Inc. All rights reserved.

15 Presented by ST Microelectronics at DAC 2012 Final Floorplan Constraints 15 Modgens Blocks placement Guard-rings Distance min=snapshot of layout; created by ST tool of Constraint menu Fix DRC feature to fix constraints after layout parameter update Modgens + Guard rings are now grouped in templates Cadence Design Systems, Inc. All rights reserved.

16 Mixed-signal design Cadence Design Systems, Inc. All rights reserved.

17 Biggest mixed-signal methodology challenges Polling results from the Cadence mixed-signal seminar IP/Package Co-design 4% SoC Signoff 2% Don t know 6% Other 2% SoC Integration 8% SoC Floorplanning 5% AMS Verification 36% SOC Verification 19% AMS IP Modeling 18% Cadence Design Systems, Inc. All rights reserved.

18 Growing RF chip content More devices, more data traffic, more spectrum Connect smart mobile devices to WiFi and cellular networks 2016: video to account for 70% of all mobile data traffic Antenna Application Processor WiFi and Bluetooth support Dual mode n and ac (5G) Multiple radios antennas, transmitters, receivers RF Front End RF Transceiver GPS, WiFi, BT Source: BofA Merrill Lynch Global Research Estimates Baseband Processor (2G/3G/4G) Cadence Design Systems, Inc. All rights reserved.

19 Mixed-Signal SoC verification complexity How do I verify the digital content in this SoC? GPS Cell WiFi FM Bluetooth SD 3.0 SD 4.0 Memory Card UFS How do I verify the mixed-signal interconnect? RFFE DRAM LPDDR LPDDR 3 LPDDR 2 DigRF NAND FLASH NAND FLASH UFS emmc SDIO I2C CSI2 CSI3 Camera Interface Touch Screen Controller Applications Processor Multimedia Processor DSI Display Driver How do I design or verify the mixed-signal IP? AMBA4 ACE, AXI, AHB LLI OCP 2.0, 3.0 SLIMbus Audio Interface cjtag HDMI SLIMbus USB 2.0 USB 3.0 USB OTG SPMI GBT How do I abstract analog behavior? Motion Sensors USB Interface Power Control Test Port Trace Port External Display Driver Cadence Design Systems, Inc. All rights reserved.

20 So is it possible to verify your circuit without getting wrapped up in the gears? Yes, but one size doesn t fit all Cadence Design Systems, Inc. All rights reserved.

21 Productivity optimized Mixed-Signal Solution Digital-centric mixed-signal Analog-centric mixed-signal Automated interaction via OpenAccess Cadence Design Systems, Inc. All rights reserved.

22 Which path is best? Optimizing your verification methodology Which Analog block Analog Digital Real Analog block RN model Real Digital RTL Wreal Event Driven Simulation plus Hardware Acceleration Transistor Model behavior? N Schematic FAST Y Mixed-Signal plus Fastspice Y N Characterize loop Reuse lib Mixed-Signal Cadence Design Systems, Inc. All rights reserved.

23 What is real number modeling? Model the analog to go into the digital solver Model analog block operation as discrete real data Signal flow-based modeling approach using sampled data Keeps accuracy in value, but saves time by remaining event-based All sent to the digital solver for high performance simulation Real signal in VHDL Real variable in Verilog Real var in SystemVerilog Wreal net in Verilog-AMS Real in e (ideal for testbenches) module vco(vin, clk); input vin; wreal vin; output clk; reg clk; real freq,clk_delay; begin freq = center_freq + vco_gain*vin; clk_delay = 1.0/(2*freq); end always #(clk_delay) clk = ~clk; endmodule Cadence Design Systems, Inc. All rights reserved.

24 Global A/MS Company Verification process reduced three months Achieved 300x faster verification Improved time to market and quality Reduced re-spins Found and fixed errors early in the design cycle Cadence Design Systems, Inc. All rights reserved.

25 It s verified, but so what? How do I implement it?? Bringing the analog and digital domains together Verilog Import Verilog Digital P&R Custom Layout Schematic hierarchy Layout hierarchy OpenAccess DB Verilog Import Verilog Digital P&R Cadence Design Systems, Inc. All rights reserved.

26 Next steps in physical implementation And then to get rid of any need for importing the digital Verilog Verilog Custom Layout Digital P&R Schematic hierarchy Layout hierarchy OpenAccess DB Cadence Design Systems, Inc. All rights reserved.

27 Circuit Simulation Extraction and Physical Verification Timing and Power Sign-Off Mixed-signal design opening new doors What do we do to keep up with our digital brothers? Foundry Qualification (PDKs, Rule Decks, PiPD libs etc.) IP (DDR-PHY, PCIe, Wide-IO) CUSTOM??? DIGITAL Giga Hz - Giga Gates Design for Manufacturing (DFM) Cadence Design Systems, Inc. All rights reserved.

28 Circuit Simulation Extraction and Physical Verification Timing and Power Signoff Adopt new techniques of course Custom advanced node and 3D-IC can be done Foundry Qualification (PDKs, rule decks, PiPD libs etc.) IP (DDR-PHY, PCIe, Wide-IO) CUSTOM Advanced-Node and / or 3D-IC DIGITAL Giga-Hertz Giga-Gates Design for Manufacturing (DFM) Cadence Design Systems, Inc. All rights reserved.

29 Advanced-node design Cadence Design Systems, Inc. All rights reserved.

30 Financial investment in 20nm technology It s expensive for everyone 32/28nm node 22/20nm node Breakeven 30-40M units Breakeven M units EDA Costs Cadence Design Systems, Inc. All rights reserved.

31 Manufacturing complexity at 20nm and below Take everything you learned at 28nm and change Double patterning New transistors Layoutdependent effects 20nm Device variation New interconnect layers Difficult design rules Cadence Design Systems, Inc. All rights reserved.

32 New 3D devices (FinFET) The new transistor for <20nm FinFET advantages: Smaller area (50%) Higher frequency (40%) Less power (0.6v 1.1v) Less leakage Higher drive current Noise and latch-up are minimized No reverse-biased diodes to substrate Cadence Design Systems, Inc. All rights reserved.

33 Custom circuit design at advanced nodes 3 dimensions in variability Layout Dependent Effects (LDE) introduce a new, third dimension of variability to circuit design Impact device performance and characteristics significantly Begin to appear at 40nm and strongly influence 28/20nm design Layout Dependent Effects (New) At advanced nodes, designers have to account for LDE during circuit design phase Device effects have a first order impact on circuit performance Process Variation (standard) Mismatch Variation (standard) Cadence Design Systems, Inc. All rights reserved.

34 LDE example well proximity effect Threshold voltages aren t guaranteed static anymore V TH Distance to well Now the layout IS the design Additional detrimental effects: Shallow trench isolation Interconnect parasitics Dummy fill usage Lithography Cadence Design Systems, Inc. All rights reserved.

35 More to do on bigger data sets Estimations are used to cut corners Corners Monte Carlo Sensitivity Working with the schematic is fast but assumptions are made about the layout. Assumptions that don t hold up as well at advanced nodes Pre-layout Schematic? Working with layout gives the exact information but is cumbersome and it s time consuming waiting for a full DRC layout to get information back to the designer Parasitics Lithography Design Rules Full-layout DRC clean Cadence Design Systems, Inc. All rights reserved.

36 What is the fastest way across no man s land? Analog Synthesis? Generate a bunch of auto-layouts and you pick one that is close to start with. But why bother creating 9 layouts you don t want?? Rapid Prototyping? Not bad. Controlled prototyping works well for some circuits but still requires designers to make assumptions about layout Partial Layout? A winner! Layout a few critical devices/nets and extract out the physical parasitics for direct analysis in the spec environment Cadence Design Systems, Inc. All rights reserved.

37 New methodology Variability Aware Design Understand parasitics and variability effects earlier Schematic entry Traditional methodology Test creation Functional simulation Design exploration Constraint entry MODGEN creation Partial placement and critical net routing NEW: Partial Layout helps refine the design much faster with the added benefit of tools of such as Layout Dependent Effect placement analysis and Electrically Aware routing In-design verification Parasitic simulation Design centering Final layout Traditional methodology Signoff verification and extraction Extracted simulation Yield optimization with final parasitics Cadence Design Systems, Inc. All rights reserved.

38 Electrically aware design ( EAD ) Understand electrical impact in-design rather than post-design Capacitance computed Electromigration current violation Resistance computed Layout-aware re-simulation Cadence Design Systems, Inc. All rights reserved.

39 Example of EAD in-design EM checking 1. Route to end of strap on M2 near first vertical finger on left 2. Once route attaches to strap, the extraction is completed and currents computed through route, strap and fingers 3. Too much current is flowing through strap to supply M1 vertical finger on right, resulting in a EM current limit violation shown in red Highlight EM violations on layout using colormap. EM Analysis Module 3. Current flowing more uniformly through strap to supply vertical finger, resulting in no EM related current limit violations Highlight EM violations on layout using colormap. 5. Once route attaches to strap, the extraction is completed and currents computed through route, strap and fingers 4. Route modified automatically or manually to attach in middle of strap, additional wire widening may also occur EM Analysis Module Cadence Design Systems, Inc. All rights reserved.

40 Advanced 20nm methodologies New problems require new design approach plans Using in-design verification Color-transparent interactive use model Local interconnect aware wire editor and router New use models for Interactive Design Rule checking Interactive color manipulation and stitching Interactive pattern detection for complex design rules Hint-based odd-cycle fixing Colored track-based routing and integration of clusterbased and track-based coloring methods Shape-based (not pin-based) cell abutment Cadence Design Systems, Inc. All rights reserved.

41 20nm routing challenges New local interconnect, vias and pin2trunk Recognize local interconnect parallel layer stacks Li2-LiPO strapping and PO-LiPO strapping Via filtering Center-to-center LiPO spacing Cadence Design Systems, Inc. All rights reserved.

42 3D-IC design and analysis Cadence Design Systems, Inc. All rights reserved.

43 3D-IC interposer methodology STEP 1: Top die implementation Bump assignment RDL Routing Wafer-level DFT/BIST Digital Die 45nm Memory Die 65nm STEP 2 : Interposer implementation Bump alignment adjust TSV/bump assignment Interposer routing STEP 3 : Interposer analysis RC extraction DRC/LVS Silicon Interposer 65nm STEP 4 : Stacked system Interdie DRC/LVS IR drop analysis SI/PI analysis Package-level DFT/BIST Cadence Design Systems, Inc. All rights reserved.

44 Custom implementation for 3D-IC Support of multi-chip visualization with background views 3D-IC floorplanning and editing (bump creation and alignment, TSVs) Support of bump, TSV and reverse side routing Connectivity extraction maintained through TSV connections Two Die Display (Overlap) Simultaneous editing between the two dies in the same process Cadence Design Systems, Inc. All rights reserved.

45 Silicon interposer and stack analysis Stacked system analysis DRC/LVS Extraction SSN/PDN and RLC IR drop analysis Timing analysis System-level EMI Cadence Design Systems, Inc. All rights reserved.

46 Summary: the Cadence 20nm solution Tools + ecosystem + methodology = design success Virtuoso Custom/Analog Encounter Digital Extraction and Simulation (Cadence QRC and MMSIM) Extraction Timing Power (Cadence QRC, ETS, and EPS) Physical verification for DRC and LVS (Cadence Physical Verification System) Design for Manufacturing (DFM) (Cadence Litho Electrical and Physical Analyzers, CMP Predictor) IP & Foundries ARM Cadence TSMC Samsung GlobalFoundries IBM ICF STMicroelectronics Cadence Design Systems, Inc. All rights reserved.

47 Cadence Design Systems, Inc. All rights reserved.