Introduction Lecturer: Gil Rahav Semester B, EE Dept. BGU. Freescale Semiconductors Israel

Transcription

1 Design מבוא לתכנון VLSI ספרתי Introduction Lecturer: Semester B, EE Dept. BGU. Freescale Semiconductors Israel 1

2 IC Products Processors CPU, DSP, Controllers Memory chips RAM, ROM, EEPROM Analog Mobile communication, audio/video processing Programmable PLA, FPGA Embedded systems Used in cars, factories Network cards System-on-chip (SoC) 2

3 Why VLSI? Integration improves the design: lower parasitics = higher speed; lower power; physically smaller. Integration reduces manufacturing cost-(almost) no manual assembly. 3

4 Why build integrated Circuit? IC Technology drives the whole innovative devices and systems which effects the way we live. ICs are much smaller. Consume less power than discrete component. Easier to design and manufacture. More reliable than discrete system. Can design more complex system. The growth of electronic industry. 4

5 Example of VLSI application Electronic system in cars. Digital electronics control VCRs Transaction processing system, ATM Personal computers and Workstations Medical electronic systems. etc. 5

6 The advantageous of digital ICs over the discrete components (1/2) Size much smaller both transistor and wires. leads to smaller parasitic resistances, capacitances and inductances Speed communication within the chips are much faster than between a chips on PCB (Printed Circuit Board). High speed of circuits on-chip due to smaller size. 6

7 The advantageous of digital ICs over the discrete components (2/2) Power Consumption Logic operation within the chip consumes much less power. smaller size -> smaller parasitic capacitances and resistance -> require less power to drive the circuit. 7

8 Advantages of IC at System Level(1/2) Smaller Physical Size can make a small electronic appliances. ie. portabletv, handheld cellular telephone Lower Power Consumption reduce total power consumption on a whole electronic circuit. Cheaper power supply which leads to a simpler cabinet for power supply. Less heat, Fan may no longer be necessary. 8

9 Advantages of IC at System Level(2/2) Reduce Cost Reducing in number of components. Power Supply requirement. Cabinets The cost of building a whole system is reduce eventhough Ics cost more. 9

10 Cost factors in ICs For large-volume ICs: packaging is largest cost; testing is second-largest cost. For low-volume ICs, design costs may swamp all manufacturing costs. 10

11 Integrated Circuit Manufacturing Technology Let us build a system faster, and more complex system Economics In 1960s,Gordon Moore said that the number of transistor would grow exponentially. The number of transistors per chip has doubled about once a year. IC plant is very expensive. $2-3billion or more. Is it worth to invest in IC business? 11

12 Moore s Law In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months (i.e., grow exponentially with time). Amazing visionary million transistor/chip barrier was crossed in the 1980 s transistors, 1 MHz clock (Intel 4004) Million, 2 GHz clock (Intel P4) Million transistor (HP PA-8500) Source: Intel web page ( 12

13 Die Size Growth 100 Die size grows by 14% to satisfy Moore s Law Die size (mm) P6 Pentium proc ~7% growth per year ~2X growth in 10 years Year

14 10000 Clock Frequency Lead microprocessors frequency doubles every 2 years X every 2 years 14 Frequency (Mhz) P6 Pentium proc Year

15 Challenges in VLSI design Multiple levels of abstraction: transistors to CPUs. Multiple and conflicting constraints: low cost and high performance are often at odds. Short design time: Late products are often irrelevant. 15

16 Jobs in VLSI Layout designers Circuit designers Architects Test engineers Fabrication engineers System designers CAD tool programmers 16

17 The VLSI design process May be part of larger product design. Major levels of abstraction: specification; architecture; logic design; circuit design; layout. 17

18 Design Abstraction Levels 18

19 VLSI Levels of Abstraction Specification (what the chip does, inputs/outputs) Architecture major resources, connections Register-Transfer logic blocks, FSMs, connections Logic gates, flip-flops, latches, connections 19 Circuit transistors, parasitics, connections Layout mask layers, polygons

20 Dealing with complexity Divide-and-conquer: limit the number of components you deal with at any one time. Group several components into larger components: transistors form gates; gates form functional units; functional units form processing elements; etc. 20

21 Hierarchical name Interior view of a component: components and wires that make it up. Exterior view of a component = type: body; pins. cout a b Full adder cin sum 21

22 Instantiating component types Each instance has its own name: add1 (type full adder) add2 (type full adder). Each instance is a separate copy of the type: Add1.a cout Add2.a a Add1(Full adder) sum a Add2(Full adder) sum b cin b cin 22

23 A hierarchical logic design box1 box2 x z 23

24 Net lists and component lists Net list: net1: top.in1 in1.in net2: i1.out xxx.b topin1: top.n1 xxx.xin1 topin2: top.n2 xxx.xin2 botin1: top.n3 xxx.xin3 net3: xxx.out i2.in outnet: i2.out top.out Component list: top: in1=net1 n1=topin1 n2=topin2 n3=botin1 out=outnet i1: in=net1 out=net2 xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet 24

25 Component hierarchy top i1 xxx i2 25

26 Hierarchical names Typical hierarchical name: top/i1.foo component pin 26

27 Transistor schematic φ' + D Q' φ 27

28 Mixed schematic φ' D Q' φ inverter 28

29 Levels of abstraction Specification: function, cost, etc. Architecture: large blocks. Logic: gates + registers. Circuits: transistor sizes for speed, power. Layout: determines parasitics. 29

30 Circuit abstraction Continuous voltages and time: + v v t t 30

31 Digital abstraction Discrete levels, discrete time: a a cout sum b a t t b full sum adder cin t b t t a b cout full sum adder cin sum t 31

32 Register-transfer abstraction Abstract components, abstract data types:

33 Register-transfer abstraction Abstract components, abstract data types:

34 Top-down vs. bottom-up design Top-down design adds functional detail. Create lower levels of abstraction from upper levels. Bottom-up design creates abstractions from low-level behavior. Good design needs both top-down and bottom-up efforts. 34

35 Design abstractions English Executable program Sequential machines Logic gates transistors rectangles specification behavior registertransfer logic circuit layout Throughput, design time Function units, clock cycles Literals, logic depth nanoseconds microns 35

36 Design validation Must check at every step that errors haven t been introducedthe longer an error remains, the more expensive it becomes to remove it. Forward checking: compare results of less- and moreabstract stages. Back annotation: copy performance numbers to earlier stages. 36

37 Manufacturing test Not the same as design validation: just because the design is right doesn t mean that every chip coming off the line will be right. Must quickly check whether manufacturing defects destroy function of chip. Must also speed-grade. 37

38 38 VLSI Design Cycle

39 IC Design Steps Specifications High-level Description Functional Description Behavioral HDL, C Structural HDL 39

40 Specifications IC Design Steps (cont.) High-level Description Functional Description Placed & Routed Design Packaging 40 Physical Design Fabri- cation Gate-level Design Technology Mapping Logic Description Synthesis X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Figs. [ Sherwani]

41 VLSI Design Cycle (2/9) System Specification Specification of the size, speed, power and functionality of the VLSI system. Architectural Design Decisions on the architecture, e.g., RISC/CISC, # of ALU s, pipeline structure, cache size, etc. Such decisions can provide an accurate estimation of the system performance, die size, power consumption, etc. 41

42 VLSI Design Cycle (3/9) Functional Design Identify main functional units and their interconnections. No details of implementation. 42

43 VLSI Design Cycle (4/9) Logic Design Design the logic, e.g., boolean expressions, control flow, word width, register allocation, etc. The outcome is called an RTL (Register Transfer Level) description. RTL is expressed in a HDL (Hardware Description Language), e.g., VHDL and Verilog. X = (AB+CD)(E+F) Y= (A(B+C) + Z + D) 43

44 VLSI Design Cycle (5/9) Circuit Design Design the circuit including gates, transistors, interconnections, etc. The outcome is called a netlist. 44

45 VLSI Design Cycle (6/9) Net list: net1: top.in1 in1.in net2: i1.out xxx.b topin1: top.n1 xxx.xin1 topin2: top.n2 xxx.xin2 botin1: top.n3 xxx.xin3 net3: xxx.out i2.in outnet: i2.out top.out Component list: top: in1=net1 n1=topin1 n2=topin2 n3=botin1 out=outnet i1: in=net1 out=net2 xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet 45

46 VLSI Design Cycle (7/9) Component hierarchy top i1 xxx i2 46

47 VLSI Design Cycle (8/9) Physical Design Convert the netlist into a geometric representation. The outcome is called a layout. 47

48 VLSI Design Cycle (9/9) Fabrication Process includes lithography, polishing, deposition, diffusion, etc., to produce a chip. Packaging Put together the chips on a PCB (Printed Circuit Board) or an MCM (Multi-Chip Module) 48

49 VLSI Design Cycle 49 System Specification Architectural Design Architectural Specification Functional Design Timing & relationship between functional units Logic Design RTL in HDL Circuit Design or Logic Synthesis Netlist Layout Chips Physical Design Fabrication Packaging Packaged and tested chips

50 Physical Design Cycle (1/6) Circuit Partitioning Floorplanning & Placement Clock Tree Routing Layout Compaction 50 Extraction and Verification

51 Physical Design Cycle (2/6) Circuit Partitioning Partition a large circuit into sub-circuits (called blocks). Factors like #blocks, block sizes, interconnection between blocks, etc., are considered. 51

52 Physical Design Cycle (3/6) Floorplanning Set up a plan for a good layout. Place the modules (modules can be blocks, functional units, etc.) at an early stage when details like shape, area, I/O pin positions of the modules,, are not yet fixed. Deadspace 52

53 Physical Design Cycle (4/6) Placement Exact placement of the modules (modules can be gates, standard cells, etc.) when details of the module design are known. The goal is to minimize the delay, total area and interconnect cost. v Feedthrough Standard cell type 1 Standard cell type 2 53

54 Physical Design Cycle (5/6) Routing Complete the interconnections between modules. Factors like critical path, clock skew, wire spacing, etc., are considered. Include global routing and detailed routing. Feedthrough v Type 1 standard cel1 Type 2 standard cell 54

55 Physical Design Cycle (6/6) Compaction Compress the layout from all directions to minimize the total chip area. Verification Check the correctness of the layout. Include DRC (Design Rule Checking), circuit extraction (generate a circuit from the layout to compare with the original netlist), performance verification (extract geometric information to compute resistance, capacitance, delay, etc.) 55

56 Design Styles Full-Custom ASICs Some (possibly all) logic cells are customized and all mask layers are customized Semicustom ASICs All logic cells are predesigned (defined in cell library) and some (possibly all) of the mask layers are customized Types: Standard-cell based and Gate-array-based ASICs Programmable ASICs All logic cells are predesigned and none of the mask layers are customized Types: PLD (Programmable Logic Device) and FPGA (Field Programmable Gate Array) 56

57 Full-custom ASICs (1/3) Engineers design some or all of the logic cells, circuits, or layout specifically for one ASIC Full-custom ICs are the most expensive to manufacture and to design Manufacturing lead time (the time it takes just to make an IC not including design time) is typically 8 weeks 57

58 Full-custom ASICs (2/3) When does it make sense? there are no suitable existing cell libraries available existing logic cells are not fast enough logic cells are not small enough logic cells consume too much power ASIC is so specialized that some circuits must be custom designed Trends: fewer and fewer full-custom ICs are being designed (excluding mixed analog/digital ASICs) 58

59 Full Custom Design (3/3) 59

60 Standard-Cell-Based ASICs (1/5) Cell-Based ASIC (CBIC) uses pre-designed cells (AND, OR gates, multiplexers, flip-flops,...) Standard-cell areas are built of rows of standard cells Standard-cell areas can be used in combination with larger predesigned cells (microcontrollers, or even microprocessors), known as megacells A cell-based ASIC (CBIC) die with a single standard-cell area combined with 4 fixed blocks 60

61 Standard-Cell-Based ASICs(2/5) Characteristics custom blocks can be embedded; ASIC designer defines only the placement of the standard cells and the interconnect in a CBIC standard cells can be placed anywhere on a silicon => all mask layers of a CBIC are customized manufacturing lead time is 8 weeks 61

62 Standard-Cell-Based ASICs (3/5) Advantages designers save time, money, and reduce risks using a predesigned, pretested, and precharacterized standard-cell library standard cells in the library are constructed using full-custom; each standard cell can be optimized individually (for example, to maximize speed, minimize area, etc); Disadvantages time or expense of designing or buying the standard-cell library time needed to fabricate all layers of the ASIC for each new design 62

63 Standard-Cell-Based ASICs(4/5) Standard-cells are designed to fit horizontally together to form rows Internal construction of a cell - 25 microns wide (lambda is 0.25) - AB: abutment box - BB: bounding box - Power supplies: VDD, GND - Each different shaded and labeled pattern represents a different layer - Connections: A1, B1, Z 63

64 64 Standard-Cell-Based ASICs (5/5) Routing the CBIC - Interconnections between cells use spaces (called channels) between rows - 2 separate layers of metal interconnect (metal1 and metal2) running at right angles to each other - Feedthrough: refers either to the piece of metal that is used to pass a signal through a cell or to a space in a cell waiting to be used as a feedthrough

65 Programmable Logic Devices(1/2) PLDs standard ICs, available in standard configurations sold in high volume to many different customers PLDs may be configured or programmed to create a part customized to specific application Characteristics no customized mask layers or logic cells fast design turnaround a single large block of programmable interconnect a matrix of logic macrocells that usually consists of programmable array logic followed by a flip-flop or latch 65

66 Programmable Logic Devices(2/2) Types of PLDs PROM: uses metal fuse that can be blown permanently) EPROM: used programmable MOS transistors whose characteristics are altering by applying a high voltage PAL Programmable Array Logic programmable AND logic array or AND plane, and fixed OR plane PLA Programmable Logic Array programmable AND plane followed by programmable OR plane Depending on how the PLD is programmed erasable PLD (EPLD) mask-programmed PLD 66

67 Field-Programmable Gate Arrays (FPGA) FPGA a step above the PLD in complexity; it is usually larger and more complex than a PLD rapidly growing in importance Characteristics none of mask layers are customized a method for programming basic cells and the interconnect the core is regular array of programmable basic logic cells (combinational + sequential) a matrix of programmable interconnect that surrounds the basic cells programmable I/O cells around the core design turnaround is a few hours 67

68 Digital Logic Circuit Definitions PLD Programmable Logic Devices SPLD Simple PLD HCPLD High Capacity PLD PLA Programmable Logic Array PAL Programmable Array Logic CPLD Complex PLD FPGA Field Programmable Gate Array 68

69 Cell development (Analog/digital) Schematic entry (transistor symbols) Analog simulation (SPICE models) Layout (layer definitions) Design Rule Checking, DRC ( design rules) Extraction (extraction rules and parameters) Electrical Rule Checking, ERC (ERC rules) Layout Versus Schematic, LVS ( LVS rules) Analog simulation. Characterization: delay, setup, hold, loading sensitivity,etc. Generation of digital simulation model with back annotation. Generation of synthesis model Generation of black-box for place & route 69

70 Digital design Behavioral simulation Synthesis (synthesis models) Gate level simulation (gate models) Floor planning Loading estimation (loading estimation model) Simulation/timing verification with estimated back-annotation Place and route (place and route rules) Design Rule Check, DRC (DRC rules) Loading extraction (rules and parameters) Simulation/timing verification with real back-annotation Design export Testing: Test generation, Fault simulation, Vector translation 70

71 Design entry Layout Drawing geometrical shapes: Requires detailed knowledge about CMOS technology Defines layout hierarchy Defines layer masks Requires detailed knowledge about design rules (hundreds of rules) Requires detailed knowledge about circuit design Slow and tedious Optimum performance can be obtained 71

72 Schematic Drawing electrical circuit: Defines electrical hierarchy Defines electrical connections Defines circuit: transistors, resistors,,, Requires good circuit design knowledge for analog design Requires good logic design knowledge for digital design (boolean logic, state machines) Gives good overview of design hierarchy Significant amount of time used for manual optimization Transistor level Gate level Module level 72

73 73 Behavioral + Synthesis Writing behavior (text): Synthesis tool required to map into gates Defines behavioral hierarchy Defines algorithm Defines architecture Often integrated with graphical block diagram tool. module add_and_mult( a,b,c, out) input[31:0] a,b,c; output[31:0] out; wire[31:0] internal_add; adder32 multiplier32 endmodule add1(a,b, internal_add); mult1( internal_add, c, out); assign #(test.logic_delay) bsr_clk = ~(m_extest m_sample m_intest) clk_dr, bsr_shift = (m_extest m_sample m_intest) & shift_dr,; clk) begin if (set) coarse <= #(test.ff_delay) offset; else if (coarse == count_roll_over) coarse <= #(test.ff_delay) 0; else coarse <= #(test.ff_delay) coarse + 1; end

74 Verification Design Rule Check (DRC): Checks geometrical shapes: width, length, spacing, overlap, etc. Electrical rule check (ERC): Checks electrical circuit: Extraction: Extracts electrical circuit: Layout versus schematic (LVS): Compares electrical circuits: (schematic and extracted layout) unconnected inputs shorted outputs correct power and ground connection transistors, connections, capacitance, resistance transistors: parallel or serial a b IN? Vdd Out Gnd EXT LVS 74

75 Simulation 75 Simulates behavior of designed circuit Input: Output: Models (transistor, gates, macro) Textual netlist (schematic, extracted layout, behavioral) User defined stimulus Circuit response (waveforms, patterns), Warnings Transistor level simulation using analog simulator (SPICE) Time domain Frequency domain Noise Gate level simulation using digital simulator Logic functionality Timing: Operating frequency, delay, setup & hold violations Timing calculator needed to calculate delays from extracted parameters Behavioral simulation System and IC definition ( algorithm, architecture ) Partitioning Complexity estimation Normally same simulator

76 Gate level models Border between transistor domain (analog) and digital domain Digital gate level models introduced to speed up digital simulation. Gate level model contains: Logic behavior Delays depending on: operating conditions, process, loading, signal slew rates Setup and hold timing violation checks Gate level model parameters extracted from transistor level simulations and characterization of real gates. 76

77 Place and Route Generates final chip from gate level netlist Goals: Placement: Minimum chip size Maximum chip speed. Placing all gates to minimize distance between connected gates Floor planning tool using design hierarchy Specialized algorithms ( min cut, simulated annealing, etc.) Timing driven Manual intervention Very compute intensive Hierarchy based floor planning Min cut Keep cutting design into equal sized pieces Simulated annealing High temperature: move gates randomly Low temperature: Move gates locally 77 For each cut: Move gates around until minimum connection across cut

78 Routing: Channel based: Channel less: Often split in two steps: Routing only in channels between gates (few metal layers: 2) Routing over gates (many metal layers: 3-6) Global route: Find a coarse route depending on local routing density Detailed route: Generate routing layout Channel based Channel less 78

79 Delay Performance of sub-micron CMOS IC s are to a large extent determined by place & route. Loading delays bigger than intrinsic gate delays Wire R-C delays becomes important in sub-micron Clock distribution over complete chip gets critical at operating frequencies above 100Mhz. Number of wires 200ps Wire load delay 100ps Local connections 50ps 25ps Gate delay Global connections 1.0u 0.5u 0.25u 0.1u Technology Wire length 79

80 Design tool framework 80 Design tools from one vendor normally integrated into a framework which enables tools to exchange data. Common data base Automatic translation from one type to another (Allows third part tools to be integrated into framework) Few standards to allow transport of designs between tools from different vendors. VHDL and Verilog behavioral models and netlists EDIF netlist, SPICE netlist for analog simulation GDSII layout Standard Delay Format (SDF) for gate delays. Small vendors must be compatible with large vendors. Transporting designs between tools from different vendors may cause problems

81 Hardware describing languages (HDL) Describe behavior not implementation Make model independent of technology Model complete systems Specification of sub-module functions Speed up simulation of large systems Standardized text format CAE tool independent 81

82 VHDL Very High speed integrated circuit Description Language Initiated by American department of defense as a specification language. Standardized by IEEE Verilog First real commercial HDL language from gateway automation (now Cadence) Default standard among chip designers for many years Until a few years ago, proprietary language of Cadence. Now also a IEEE standard because of severe competition from VHDL. Result: multiple vendors 82

83 Compiled/Interpreted Compiled: Description compiled into C and then into binary or directly into binary Fast execution Slow compilation Interpreted: Description interpreted at run time Slow execution Fast compilation Many interactive features VHDL normally compiled Verilog exists in both interpreted and compiled versions 83

84 HDL design entry Text: Tool independent Good for describing algorithms Bad for getting an overview of a large design 84

85 Add-on tools Block diagrams to get overview of hierarchy Graphical description of final state machines (FSM) Generates synthesizable HDL code Flowcharts Language sensitive editors Waveform display tools From Visual HDL, Summit design 85

86 Synthesis and Technology dependence Algorithm 0% technology dependent Architecture 10% technology dependent For i = 0 ; i = 15 sum = sum + data[i] Data[0] Data[15] i Data[0] Data[15] Behavioral synthesis Register level 20% technology dependent Clear address Clock MEM Sum Clear sum Sum Logic synthesis Gate level 100% technology dependent 86

87 Logic synthesis HDL compilation (from VHDL or Verilog) Registers: Where storage is required Logic: Boolean equations, if-then-else, case, etc. Logic optimization Logic minimization (similar to Karnaugh maps) Finds logic sharing between equations Maps into gates available in given technology Uses local optimization rules 3 logic gates 6 basic CMOS gates 3 basic CMOS gates 87

88 Timing optimization Estimate loading of wires Defined timing constraints (clock frequency, delay, etc.) Perform transformations until all constraints fulfilled Arriving late Arriving late Complex logic Arriving late Complex logic 0 Complex logic 0 1 Arriving late 1 88

89 Synthesis goals Combined timing - size optimization Smallest circuit complying to all timing constraints Size Design space Requirements Delay Best solution found as a combination of special optimization algorithms and evaluation of many alternative solutions (Similar to simulated annealing) 89

90 Problems in synthesis Dealing with single late signal Mapping into complex library elements (special directives required) Regular data path structures: Adders: ripple carry, carry look ahead, carry select,etc. Multipliers, etc. Use special guidance to select special adders, multipliers, etc.. Performance of sub-micron technologies are dominated by wiring delays (wire capacitance + R-C delays) Synthesis in many cases does a better job than a manually optimized logic design. (in much shorter time) 90

91 Timing estimation in synthesis Delay Wire loading Timing optimization is based on a wire loading model. Loading of gate = input capacitance of following gates + wire capacitance Gate loading known by synthesizer Wire loading must be estimated R-C delay calculation very complicated Relative number Average Average 200ps Wire load delay 100ps 50ps 25ps Gate delay Small chip Large chip 1.0u 0.5u 0.25u 0.1u Technology Wire capacitance 91

92 Estimate wire capacitance from number of gates connected to wire. Wire capacitance Large chip Small chip Advantage: Disadvantage: Number of gates per wire Simple model Bad estimate of long wires (which limits circuit performance) 92

93 Estimate using floor plan Inside local region: Estimate as function of number of gates and size of region Between regions: Use estimate of physical distance between routing regions. Region 1 Region 2 Region 3 Advantage: Disadvantage: Realistic estimate Synthesizer most work with complete design In sub-micro CMOS technologies Synthesis and Place & Route must work hand in hand 93

94 Trends in synthesis Integration of synthesis and P&R Synthesizable standard modules (Processor, PCI interface, Digital filters, etc.) Automatic insertion of scan path for production testing. Synthesis for low power Synthesis of self-timed circuits (asynchronous) Behavioral synthesis Formal verification 94

95 Technology Trends Processor Logic capacity Clock frequency Cost per function Memory DRAM capacity: (4x every 3 years) Speed: Cost per bit: increases ~ 30% per year increases ~ 20% per year decreases ~20% per year increases ~ 60% per year increases ~ 10% per year decreases ~25% per year 95

96 These trends have brought many changes and new challenges to circuit design. 96

97 Complicated Design Too many transistors and no way to handle them manually. Solutions: CAD Hierarchical design Design re-use 97

98 Power and Noise Huge power consumption and heat dissipation becomes a problem Noise and cross talk. Solutions: Better physical design 98

99 Interconnect Area Too many interconnects Solutions: More interconnect layers (made possible by Chemical- Mechanical Polishing) CAD tools for 3-D routing 99

100 Interconnect Delay Interconnect delay becomes a dominating factor in circuit performance Solutions: Use copper wire Interconnect optimization in physical design, e.g., wire sizing, buffer insertion, buffer sizing. 100

101 The Process of Design Design Implementation Debug Design Initial concept: what is the function performed by the object? Constraints: How fast? How much area? How much cost? Refine abstract functional blocks into more concrete realizations Implementation Assemble primitives into more complex building blocks Composition via wiring Choose among alternatives to improve the design Debug Faulty systems: design flaws, composition flaws, component flaws Design to make debugging easier Hypothesis formation and troubleshooting skills 101